source: S-port/trunk/Core/Src/system_stm32f4xx.c

Last change on this file was 1, checked in by AlexLir, 3 years ago
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1/**
2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32f4xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 *
22 ******************************************************************************
23 * @attention
24 *
25 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
26 * All rights reserved.</center></h2>
27 *
28 * This software component is licensed by ST under BSD 3-Clause license,
29 * the "License"; You may not use this file except in compliance with the
30 * License. You may obtain a copy of the License at:
31 * opensource.org/licenses/BSD-3-Clause
32 *
33 ******************************************************************************
34 */
35
36/** @addtogroup CMSIS
37 * @{
38 */
39
40/** @addtogroup stm32f4xx_system
41 * @{
42 */
43
44/** @addtogroup STM32F4xx_System_Private_Includes
45 * @{
46 */
47
48
49#include "stm32f4xx.h"
50
51#if !defined (HSE_VALUE)
52 #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
53#endif /* HSE_VALUE */
54
55#if !defined (HSI_VALUE)
56 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
57#endif /* HSI_VALUE */
58
59/**
60 * @}
61 */
62
63/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
64 * @{
65 */
66
67/**
68 * @}
69 */
70
71/** @addtogroup STM32F4xx_System_Private_Defines
72 * @{
73 */
74
75/************************* Miscellaneous Configuration ************************/
76/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
77#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
78 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
79 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
80/* #define DATA_IN_ExtSRAM */
81#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
82 STM32F412Zx || STM32F412Vx */
83
84#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
85 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
86/* #define DATA_IN_ExtSDRAM */
87#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
88 STM32F479xx */
89
90/* Note: Following vector table addresses must be defined in line with linker
91 configuration. */
92/*!< Uncomment the following line if you need to relocate the vector table
93 anywhere in Flash or Sram, else the vector table is kept at the automatic
94 remap of boot address selected */
95#define USER_VECT_TAB_ADDRESS
96#if defined(USER_VECT_TAB_ADDRESS)
97/*!< Uncomment the following line if you need to relocate your vector Table
98 in Sram else user remap will be done in Flash. */
99/* #define VECT_TAB_SRAM */
100#if defined(VECT_TAB_SRAM)
101#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
102 This value must be a multiple of 0x200. */
103#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
104 This value must be a multiple of 0x200. */
105#else
106#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
107 This value must be a multiple of 0x200. */
108#define VECT_TAB_OFFSET 0x00020000U /*!< Vector Table base offset field.
109 This value must be a multiple of 0x200. */
110#endif /* VECT_TAB_SRAM */
111#endif /* USER_VECT_TAB_ADDRESS */
112/******************************************************************************/
113
114/**
115 * @}
116 */
117
118/** @addtogroup STM32F4xx_System_Private_Macros
119 * @{
120 */
121
122/**
123 * @}
124 */
125
126/** @addtogroup STM32F4xx_System_Private_Variables
127 * @{
128 */
129 /* This variable is updated in three ways:
130 1) by calling CMSIS function SystemCoreClockUpdate()
131 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
132 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
133 Note: If you use this function to configure the system clock; then there
134 is no need to call the 2 first functions listed above, since SystemCoreClock
135 variable is updated automatically.
136 */
137uint32_t SystemCoreClock = 168000000;
138const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
139const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
140/**
141 * @}
142 */
143
144/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
145 * @{
146 */
147
148#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
149 static void SystemInit_ExtMemCtl(void);
150#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
151
152/**
153 * @}
154 */
155
156/** @addtogroup STM32F4xx_System_Private_Functions
157 * @{
158 */
159
160/**
161 * @brief Setup the microcontroller system
162 * Initialize the FPU setting, vector table location and External memory
163 * configuration.
164 * @param None
165 * @retval None
166 */
167void SystemInit(void)
168{
169 /* FPU settings ------------------------------------------------------------*/
170 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
171 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
172 #endif
173
174#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
175 SystemInit_ExtMemCtl();
176#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
177
178// RCC->CR |= 0x00000001U;
179// RCC->CFGR &= 0xF0FF0000U;
180// /* Reset HSEON, CSSON and PLLON bits */
181// RCC->CR &= 0xFEF6FFFFU;
182
183// /* Reset HSEBYP bit */
184// RCC->CR &= 0xFFFBFFFFU;
185
186// /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
187// RCC->CFGR &= 0xFF80FFFFU;
188//
189// /* Reset PLL2ON and PLL3ON bits */
190// RCC->CR &= 0xEBFFFFFFU;
191
192// /* Disable all interrupts and clear pending bits */
193// RCC->CIR = 0x00FF0000U;
194
195 /* Configure the Vector Table location -------------------------------------*/
196#if defined(USER_VECT_TAB_ADDRESS)
197 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
198#endif /* USER_VECT_TAB_ADDRESS */
199}
200
201/**
202 * @brief Update SystemCoreClock variable according to Clock Register Values.
203 * The SystemCoreClock variable contains the core clock (HCLK), it can
204 * be used by the user application to setup the SysTick timer or configure
205 * other parameters.
206 *
207 * @note Each time the core clock (HCLK) changes, this function must be called
208 * to update SystemCoreClock variable value. Otherwise, any configuration
209 * based on this variable will be incorrect.
210 *
211 * @note - The system frequency computed by this function is not the real
212 * frequency in the chip. It is calculated based on the predefined
213 * constant and the selected clock source:
214 *
215 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
216 *
217 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
218 *
219 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
220 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
221 *
222 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
223 * 16 MHz) but the real value may vary depending on the variations
224 * in voltage and temperature.
225 *
226 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
227 * depends on the application requirements), user has to ensure that HSE_VALUE
228 * is same as the real frequency of the crystal used. Otherwise, this function
229 * may have wrong result.
230 *
231 * - The result of this function could be not correct when using fractional
232 * value for HSE crystal.
233 *
234 * @param None
235 * @retval None
236 */
237void SystemCoreClockUpdate(void)
238{
239 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
240
241 /* Get SYSCLK source -------------------------------------------------------*/
242 tmp = RCC->CFGR & RCC_CFGR_SWS;
243
244 switch (tmp)
245 {
246 case 0x00: /* HSI used as system clock source */
247 SystemCoreClock = HSI_VALUE;
248 break;
249 case 0x04: /* HSE used as system clock source */
250 SystemCoreClock = HSE_VALUE;
251 break;
252 case 0x08: /* PLL used as system clock source */
253
254 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
255 SYSCLK = PLL_VCO / PLL_P
256 */
257 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
258 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
259
260 if (pllsource != 0)
261 {
262 /* HSE used as PLL clock source */
263 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
264 }
265 else
266 {
267 /* HSI used as PLL clock source */
268 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
269 }
270
271 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
272 SystemCoreClock = pllvco/pllp;
273 break;
274 default:
275 SystemCoreClock = HSI_VALUE;
276 break;
277 }
278 /* Compute HCLK frequency --------------------------------------------------*/
279 /* Get HCLK prescaler */
280 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
281 /* HCLK frequency */
282 SystemCoreClock >>= tmp;
283}
284
285#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
286#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
287 || defined(STM32F469xx) || defined(STM32F479xx)
288/**
289 * @brief Setup the external memory controller.
290 * Called in startup_stm32f4xx.s before jump to main.
291 * This function configures the external memories (SRAM/SDRAM)
292 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
293 * @param None
294 * @retval None
295 */
296void SystemInit_ExtMemCtl(void)
297{
298 __IO uint32_t tmp = 0x00;
299
300 register uint32_t tmpreg = 0, timeout = 0xFFFF;
301 register __IO uint32_t index;
302
303 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
304 RCC->AHB1ENR |= 0x000001F8;
305
306 /* Delay after an RCC peripheral clock enabling */
307 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
308
309 /* Connect PDx pins to FMC Alternate function */
310 GPIOD->AFR[0] = 0x00CCC0CC;
311 GPIOD->AFR[1] = 0xCCCCCCCC;
312 /* Configure PDx pins in Alternate function mode */
313 GPIOD->MODER = 0xAAAA0A8A;
314 /* Configure PDx pins speed to 100 MHz */
315 GPIOD->OSPEEDR = 0xFFFF0FCF;
316 /* Configure PDx pins Output type to push-pull */
317 GPIOD->OTYPER = 0x00000000;
318 /* No pull-up, pull-down for PDx pins */
319 GPIOD->PUPDR = 0x00000000;
320
321 /* Connect PEx pins to FMC Alternate function */
322 GPIOE->AFR[0] = 0xC00CC0CC;
323 GPIOE->AFR[1] = 0xCCCCCCCC;
324 /* Configure PEx pins in Alternate function mode */
325 GPIOE->MODER = 0xAAAA828A;
326 /* Configure PEx pins speed to 100 MHz */
327 GPIOE->OSPEEDR = 0xFFFFC3CF;
328 /* Configure PEx pins Output type to push-pull */
329 GPIOE->OTYPER = 0x00000000;
330 /* No pull-up, pull-down for PEx pins */
331 GPIOE->PUPDR = 0x00000000;
332
333 /* Connect PFx pins to FMC Alternate function */
334 GPIOF->AFR[0] = 0xCCCCCCCC;
335 GPIOF->AFR[1] = 0xCCCCCCCC;
336 /* Configure PFx pins in Alternate function mode */
337 GPIOF->MODER = 0xAA800AAA;
338 /* Configure PFx pins speed to 50 MHz */
339 GPIOF->OSPEEDR = 0xAA800AAA;
340 /* Configure PFx pins Output type to push-pull */
341 GPIOF->OTYPER = 0x00000000;
342 /* No pull-up, pull-down for PFx pins */
343 GPIOF->PUPDR = 0x00000000;
344
345 /* Connect PGx pins to FMC Alternate function */
346 GPIOG->AFR[0] = 0xCCCCCCCC;
347 GPIOG->AFR[1] = 0xCCCCCCCC;
348 /* Configure PGx pins in Alternate function mode */
349 GPIOG->MODER = 0xAAAAAAAA;
350 /* Configure PGx pins speed to 50 MHz */
351 GPIOG->OSPEEDR = 0xAAAAAAAA;
352 /* Configure PGx pins Output type to push-pull */
353 GPIOG->OTYPER = 0x00000000;
354 /* No pull-up, pull-down for PGx pins */
355 GPIOG->PUPDR = 0x00000000;
356
357 /* Connect PHx pins to FMC Alternate function */
358 GPIOH->AFR[0] = 0x00C0CC00;
359 GPIOH->AFR[1] = 0xCCCCCCCC;
360 /* Configure PHx pins in Alternate function mode */
361 GPIOH->MODER = 0xAAAA08A0;
362 /* Configure PHx pins speed to 50 MHz */
363 GPIOH->OSPEEDR = 0xAAAA08A0;
364 /* Configure PHx pins Output type to push-pull */
365 GPIOH->OTYPER = 0x00000000;
366 /* No pull-up, pull-down for PHx pins */
367 GPIOH->PUPDR = 0x00000000;
368
369 /* Connect PIx pins to FMC Alternate function */
370 GPIOI->AFR[0] = 0xCCCCCCCC;
371 GPIOI->AFR[1] = 0x00000CC0;
372 /* Configure PIx pins in Alternate function mode */
373 GPIOI->MODER = 0x0028AAAA;
374 /* Configure PIx pins speed to 50 MHz */
375 GPIOI->OSPEEDR = 0x0028AAAA;
376 /* Configure PIx pins Output type to push-pull */
377 GPIOI->OTYPER = 0x00000000;
378 /* No pull-up, pull-down for PIx pins */
379 GPIOI->PUPDR = 0x00000000;
380
381/*-- FMC Configuration -------------------------------------------------------*/
382 /* Enable the FMC interface clock */
383 RCC->AHB3ENR |= 0x00000001;
384 /* Delay after an RCC peripheral clock enabling */
385 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
386
387 FMC_Bank5_6->SDCR[0] = 0x000019E4;
388 FMC_Bank5_6->SDTR[0] = 0x01115351;
389
390 /* SDRAM initialization sequence */
391 /* Clock enable command */
392 FMC_Bank5_6->SDCMR = 0x00000011;
393 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
394 while((tmpreg != 0) && (timeout-- > 0))
395 {
396 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
397 }
398
399 /* Delay */
400 for (index = 0; index<1000; index++);
401
402 /* PALL command */
403 FMC_Bank5_6->SDCMR = 0x00000012;
404 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
405 timeout = 0xFFFF;
406 while((tmpreg != 0) && (timeout-- > 0))
407 {
408 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
409 }
410
411 /* Auto refresh command */
412 FMC_Bank5_6->SDCMR = 0x00000073;
413 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
414 timeout = 0xFFFF;
415 while((tmpreg != 0) && (timeout-- > 0))
416 {
417 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
418 }
419
420 /* MRD register program */
421 FMC_Bank5_6->SDCMR = 0x00046014;
422 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
423 timeout = 0xFFFF;
424 while((tmpreg != 0) && (timeout-- > 0))
425 {
426 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
427 }
428
429 /* Set refresh count */
430 tmpreg = FMC_Bank5_6->SDRTR;
431 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
432
433 /* Disable write protection */
434 tmpreg = FMC_Bank5_6->SDCR[0];
435 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
436
437#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
438 /* Configure and enable Bank1_SRAM2 */
439 FMC_Bank1->BTCR[2] = 0x00001011;
440 FMC_Bank1->BTCR[3] = 0x00000201;
441 FMC_Bank1E->BWTR[2] = 0x0fffffff;
442#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
443#if defined(STM32F469xx) || defined(STM32F479xx)
444 /* Configure and enable Bank1_SRAM2 */
445 FMC_Bank1->BTCR[2] = 0x00001091;
446 FMC_Bank1->BTCR[3] = 0x00110212;
447 FMC_Bank1E->BWTR[2] = 0x0fffffff;
448#endif /* STM32F469xx || STM32F479xx */
449
450 (void)(tmp);
451}
452#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
453#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
454/**
455 * @brief Setup the external memory controller.
456 * Called in startup_stm32f4xx.s before jump to main.
457 * This function configures the external memories (SRAM/SDRAM)
458 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
459 * @param None
460 * @retval None
461 */
462void SystemInit_ExtMemCtl(void)
463{
464 __IO uint32_t tmp = 0x00;
465#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
466 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
467#if defined (DATA_IN_ExtSDRAM)
468 register uint32_t tmpreg = 0, timeout = 0xFFFF;
469 register __IO uint32_t index;
470
471#if defined(STM32F446xx)
472 /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
473 clock */
474 RCC->AHB1ENR |= 0x0000007D;
475#else
476 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
477 clock */
478 RCC->AHB1ENR |= 0x000001F8;
479#endif /* STM32F446xx */
480 /* Delay after an RCC peripheral clock enabling */
481 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
482
483#if defined(STM32F446xx)
484 /* Connect PAx pins to FMC Alternate function */
485 GPIOA->AFR[0] |= 0xC0000000;
486 GPIOA->AFR[1] |= 0x00000000;
487 /* Configure PDx pins in Alternate function mode */
488 GPIOA->MODER |= 0x00008000;
489 /* Configure PDx pins speed to 50 MHz */
490 GPIOA->OSPEEDR |= 0x00008000;
491 /* Configure PDx pins Output type to push-pull */
492 GPIOA->OTYPER |= 0x00000000;
493 /* No pull-up, pull-down for PDx pins */
494 GPIOA->PUPDR |= 0x00000000;
495
496 /* Connect PCx pins to FMC Alternate function */
497 GPIOC->AFR[0] |= 0x00CC0000;
498 GPIOC->AFR[1] |= 0x00000000;
499 /* Configure PDx pins in Alternate function mode */
500 GPIOC->MODER |= 0x00000A00;
501 /* Configure PDx pins speed to 50 MHz */
502 GPIOC->OSPEEDR |= 0x00000A00;
503 /* Configure PDx pins Output type to push-pull */
504 GPIOC->OTYPER |= 0x00000000;
505 /* No pull-up, pull-down for PDx pins */
506 GPIOC->PUPDR |= 0x00000000;
507#endif /* STM32F446xx */
508
509 /* Connect PDx pins to FMC Alternate function */
510 GPIOD->AFR[0] = 0x000000CC;
511 GPIOD->AFR[1] = 0xCC000CCC;
512 /* Configure PDx pins in Alternate function mode */
513 GPIOD->MODER = 0xA02A000A;
514 /* Configure PDx pins speed to 50 MHz */
515 GPIOD->OSPEEDR = 0xA02A000A;
516 /* Configure PDx pins Output type to push-pull */
517 GPIOD->OTYPER = 0x00000000;
518 /* No pull-up, pull-down for PDx pins */
519 GPIOD->PUPDR = 0x00000000;
520
521 /* Connect PEx pins to FMC Alternate function */
522 GPIOE->AFR[0] = 0xC00000CC;
523 GPIOE->AFR[1] = 0xCCCCCCCC;
524 /* Configure PEx pins in Alternate function mode */
525 GPIOE->MODER = 0xAAAA800A;
526 /* Configure PEx pins speed to 50 MHz */
527 GPIOE->OSPEEDR = 0xAAAA800A;
528 /* Configure PEx pins Output type to push-pull */
529 GPIOE->OTYPER = 0x00000000;
530 /* No pull-up, pull-down for PEx pins */
531 GPIOE->PUPDR = 0x00000000;
532
533 /* Connect PFx pins to FMC Alternate function */
534 GPIOF->AFR[0] = 0xCCCCCCCC;
535 GPIOF->AFR[1] = 0xCCCCCCCC;
536 /* Configure PFx pins in Alternate function mode */
537 GPIOF->MODER = 0xAA800AAA;
538 /* Configure PFx pins speed to 50 MHz */
539 GPIOF->OSPEEDR = 0xAA800AAA;
540 /* Configure PFx pins Output type to push-pull */
541 GPIOF->OTYPER = 0x00000000;
542 /* No pull-up, pull-down for PFx pins */
543 GPIOF->PUPDR = 0x00000000;
544
545 /* Connect PGx pins to FMC Alternate function */
546 GPIOG->AFR[0] = 0xCCCCCCCC;
547 GPIOG->AFR[1] = 0xCCCCCCCC;
548 /* Configure PGx pins in Alternate function mode */
549 GPIOG->MODER = 0xAAAAAAAA;
550 /* Configure PGx pins speed to 50 MHz */
551 GPIOG->OSPEEDR = 0xAAAAAAAA;
552 /* Configure PGx pins Output type to push-pull */
553 GPIOG->OTYPER = 0x00000000;
554 /* No pull-up, pull-down for PGx pins */
555 GPIOG->PUPDR = 0x00000000;
556
557#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
558 || defined(STM32F469xx) || defined(STM32F479xx)
559 /* Connect PHx pins to FMC Alternate function */
560 GPIOH->AFR[0] = 0x00C0CC00;
561 GPIOH->AFR[1] = 0xCCCCCCCC;
562 /* Configure PHx pins in Alternate function mode */
563 GPIOH->MODER = 0xAAAA08A0;
564 /* Configure PHx pins speed to 50 MHz */
565 GPIOH->OSPEEDR = 0xAAAA08A0;
566 /* Configure PHx pins Output type to push-pull */
567 GPIOH->OTYPER = 0x00000000;
568 /* No pull-up, pull-down for PHx pins */
569 GPIOH->PUPDR = 0x00000000;
570
571 /* Connect PIx pins to FMC Alternate function */
572 GPIOI->AFR[0] = 0xCCCCCCCC;
573 GPIOI->AFR[1] = 0x00000CC0;
574 /* Configure PIx pins in Alternate function mode */
575 GPIOI->MODER = 0x0028AAAA;
576 /* Configure PIx pins speed to 50 MHz */
577 GPIOI->OSPEEDR = 0x0028AAAA;
578 /* Configure PIx pins Output type to push-pull */
579 GPIOI->OTYPER = 0x00000000;
580 /* No pull-up, pull-down for PIx pins */
581 GPIOI->PUPDR = 0x00000000;
582#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
583
584/*-- FMC Configuration -------------------------------------------------------*/
585 /* Enable the FMC interface clock */
586 RCC->AHB3ENR |= 0x00000001;
587 /* Delay after an RCC peripheral clock enabling */
588 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
589
590 /* Configure and enable SDRAM bank1 */
591#if defined(STM32F446xx)
592 FMC_Bank5_6->SDCR[0] = 0x00001954;
593#else
594 FMC_Bank5_6->SDCR[0] = 0x000019E4;
595#endif /* STM32F446xx */
596 FMC_Bank5_6->SDTR[0] = 0x01115351;
597
598 /* SDRAM initialization sequence */
599 /* Clock enable command */
600 FMC_Bank5_6->SDCMR = 0x00000011;
601 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
602 while((tmpreg != 0) && (timeout-- > 0))
603 {
604 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
605 }
606
607 /* Delay */
608 for (index = 0; index<1000; index++);
609
610 /* PALL command */
611 FMC_Bank5_6->SDCMR = 0x00000012;
612 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
613 timeout = 0xFFFF;
614 while((tmpreg != 0) && (timeout-- > 0))
615 {
616 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
617 }
618
619 /* Auto refresh command */
620#if defined(STM32F446xx)
621 FMC_Bank5_6->SDCMR = 0x000000F3;
622#else
623 FMC_Bank5_6->SDCMR = 0x00000073;
624#endif /* STM32F446xx */
625 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
626 timeout = 0xFFFF;
627 while((tmpreg != 0) && (timeout-- > 0))
628 {
629 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
630 }
631
632 /* MRD register program */
633#if defined(STM32F446xx)
634 FMC_Bank5_6->SDCMR = 0x00044014;
635#else
636 FMC_Bank5_6->SDCMR = 0x00046014;
637#endif /* STM32F446xx */
638 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
639 timeout = 0xFFFF;
640 while((tmpreg != 0) && (timeout-- > 0))
641 {
642 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
643 }
644
645 /* Set refresh count */
646 tmpreg = FMC_Bank5_6->SDRTR;
647#if defined(STM32F446xx)
648 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
649#else
650 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
651#endif /* STM32F446xx */
652
653 /* Disable write protection */
654 tmpreg = FMC_Bank5_6->SDCR[0];
655 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
656#endif /* DATA_IN_ExtSDRAM */
657#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
658
659#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
660 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
661 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
662
663#if defined(DATA_IN_ExtSRAM)
664/*-- GPIOs Configuration -----------------------------------------------------*/
665 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
666 RCC->AHB1ENR |= 0x00000078;
667 /* Delay after an RCC peripheral clock enabling */
668 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
669
670 /* Connect PDx pins to FMC Alternate function */
671 GPIOD->AFR[0] = 0x00CCC0CC;
672 GPIOD->AFR[1] = 0xCCCCCCCC;
673 /* Configure PDx pins in Alternate function mode */
674 GPIOD->MODER = 0xAAAA0A8A;
675 /* Configure PDx pins speed to 100 MHz */
676 GPIOD->OSPEEDR = 0xFFFF0FCF;
677 /* Configure PDx pins Output type to push-pull */
678 GPIOD->OTYPER = 0x00000000;
679 /* No pull-up, pull-down for PDx pins */
680 GPIOD->PUPDR = 0x00000000;
681
682 /* Connect PEx pins to FMC Alternate function */
683 GPIOE->AFR[0] = 0xC00CC0CC;
684 GPIOE->AFR[1] = 0xCCCCCCCC;
685 /* Configure PEx pins in Alternate function mode */
686 GPIOE->MODER = 0xAAAA828A;
687 /* Configure PEx pins speed to 100 MHz */
688 GPIOE->OSPEEDR = 0xFFFFC3CF;
689 /* Configure PEx pins Output type to push-pull */
690 GPIOE->OTYPER = 0x00000000;
691 /* No pull-up, pull-down for PEx pins */
692 GPIOE->PUPDR = 0x00000000;
693
694 /* Connect PFx pins to FMC Alternate function */
695 GPIOF->AFR[0] = 0x00CCCCCC;
696 GPIOF->AFR[1] = 0xCCCC0000;
697 /* Configure PFx pins in Alternate function mode */
698 GPIOF->MODER = 0xAA000AAA;
699 /* Configure PFx pins speed to 100 MHz */
700 GPIOF->OSPEEDR = 0xFF000FFF;
701 /* Configure PFx pins Output type to push-pull */
702 GPIOF->OTYPER = 0x00000000;
703 /* No pull-up, pull-down for PFx pins */
704 GPIOF->PUPDR = 0x00000000;
705
706 /* Connect PGx pins to FMC Alternate function */
707 GPIOG->AFR[0] = 0x00CCCCCC;
708 GPIOG->AFR[1] = 0x000000C0;
709 /* Configure PGx pins in Alternate function mode */
710 GPIOG->MODER = 0x00085AAA;
711 /* Configure PGx pins speed to 100 MHz */
712 GPIOG->OSPEEDR = 0x000CAFFF;
713 /* Configure PGx pins Output type to push-pull */
714 GPIOG->OTYPER = 0x00000000;
715 /* No pull-up, pull-down for PGx pins */
716 GPIOG->PUPDR = 0x00000000;
717
718/*-- FMC/FSMC Configuration --------------------------------------------------*/
719 /* Enable the FMC/FSMC interface clock */
720 RCC->AHB3ENR |= 0x00000001;
721
722#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
723 /* Delay after an RCC peripheral clock enabling */
724 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
725 /* Configure and enable Bank1_SRAM2 */
726 FMC_Bank1->BTCR[2] = 0x00001011;
727 FMC_Bank1->BTCR[3] = 0x00000201;
728 FMC_Bank1E->BWTR[2] = 0x0fffffff;
729#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
730#if defined(STM32F469xx) || defined(STM32F479xx)
731 /* Delay after an RCC peripheral clock enabling */
732 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
733 /* Configure and enable Bank1_SRAM2 */
734 FMC_Bank1->BTCR[2] = 0x00001091;
735 FMC_Bank1->BTCR[3] = 0x00110212;
736 FMC_Bank1E->BWTR[2] = 0x0fffffff;
737#endif /* STM32F469xx || STM32F479xx */
738#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
739 || defined(STM32F412Zx) || defined(STM32F412Vx)
740 /* Delay after an RCC peripheral clock enabling */
741 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
742 /* Configure and enable Bank1_SRAM2 */
743 FSMC_Bank1->BTCR[2] = 0x00001011;
744 FSMC_Bank1->BTCR[3] = 0x00000201;
745 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
746#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
747
748#endif /* DATA_IN_ExtSRAM */
749#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
750 STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
751 (void)(tmp);
752}
753#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
754/**
755 * @}
756 */
757
758/**
759 * @}
760 */
761
762/**
763 * @}
764 */
765/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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