source: S-port/trunk/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s@ 1

Last change on this file since 1 was 1, checked in by AlexLir, 2 years ago
File size: 19.2 KB
Line 
1/**
2 ******************************************************************************
3 * @file startup_stm32f410rx.s
4 * @author MCD Application Team
5 * @brief STM32F410Rx Devices vector table for GCC based toolchains.
6 * This module performs:
7 * - Set the initial SP
8 * - Set the initial PC == Reset_Handler,
9 * - Set the vector table entries with the exceptions ISR address
10 * - Branches to main in the C library (which eventually
11 * calls main()).
12 * After Reset the Cortex-M4 processor is in Thread mode,
13 * priority is Privileged, and the Stack is set to Main.
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18 * All rights reserved.</center></h2>
19 *
20 * This software component is licensed by ST under BSD 3-Clause license,
21 * the "License"; You may not use this file except in compliance with the
22 * License. You may obtain a copy of the License at:
23 * opensource.org/licenses/BSD-3-Clause
24 *
25 ******************************************************************************
26 */
27
28 .syntax unified
29 .cpu cortex-m4
30 .fpu softvfp
31 .thumb
32
33.global g_pfnVectors
34.global Default_Handler
35
36/* start address for the initialization values of the .data section.
37defined in linker script */
38.word _sidata
39/* start address for the .data section. defined in linker script */
40.word _sdata
41/* end address for the .data section. defined in linker script */
42.word _edata
43/* start address for the .bss section. defined in linker script */
44.word _sbss
45/* end address for the .bss section. defined in linker script */
46.word _ebss
47/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
48
49/**
50 * @brief This is the code that gets called when the processor first
51 * starts execution following a reset event. Only the absolutely
52 * necessary set is performed, after which the application
53 * supplied main() routine is called.
54 * @param None
55 * @retval : None
56*/
57
58 .section .text.Reset_Handler
59 .weak Reset_Handler
60 .type Reset_Handler, %function
61Reset_Handler:
62 ldr sp, =_estack /* set stack pointer */
63
64/* Copy the data segment initializers from flash to SRAM */
65 ldr r0, =_sdata
66 ldr r1, =_edata
67 ldr r2, =_sidata
68 movs r3, #0
69 b LoopCopyDataInit
70
71CopyDataInit:
72 ldr r4, [r2, r3]
73 str r4, [r0, r3]
74 adds r3, r3, #4
75
76LoopCopyDataInit:
77 adds r4, r0, r3
78 cmp r4, r1
79 bcc CopyDataInit
80
81/* Zero fill the bss segment. */
82 ldr r2, =_sbss
83 ldr r4, =_ebss
84 movs r3, #0
85 b LoopFillZerobss
86
87FillZerobss:
88 str r3, [r2]
89 adds r2, r2, #4
90
91LoopFillZerobss:
92 cmp r2, r4
93 bcc FillZerobss
94
95/* Call the clock system intitialization function.*/
96 bl SystemInit
97/* Call static constructors */
98 bl __libc_init_array
99/* Call the application's entry point.*/
100 bl main
101 bx lr
102.size Reset_Handler, .-Reset_Handler
103
104/**
105 * @brief This is the code that gets called when the processor receives an
106 * unexpected interrupt. This simply enters an infinite loop, preserving
107 * the system state for examination by a debugger.
108 * @param None
109 * @retval None
110*/
111 .section .text.Default_Handler,"ax",%progbits
112Default_Handler:
113Infinite_Loop:
114 b Infinite_Loop
115 .size Default_Handler, .-Default_Handler
116/******************************************************************************
117*
118* The minimal vector table for a Cortex M3. Note that the proper constructs
119* must be placed on this to ensure that it ends up at physical address
120* 0x0000.0000.
121*
122*******************************************************************************/
123 .section .isr_vector,"a",%progbits
124 .type g_pfnVectors, %object
125 .size g_pfnVectors, .-g_pfnVectors
126
127g_pfnVectors:
128 .word _estack
129 .word Reset_Handler
130 .word NMI_Handler
131 .word HardFault_Handler
132 .word MemManage_Handler
133 .word BusFault_Handler
134 .word UsageFault_Handler
135 .word 0
136 .word 0
137 .word 0
138 .word 0
139 .word SVC_Handler
140 .word DebugMon_Handler
141 .word 0
142 .word PendSV_Handler
143 .word SysTick_Handler
144
145 /* External Interrupts */
146 .word WWDG_IRQHandler /* Window WatchDog */
147 .word PVD_IRQHandler /* PVD through EXTI Line detection */
148 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
149 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
150 .word FLASH_IRQHandler /* FLASH */
151 .word RCC_IRQHandler /* RCC */
152 .word EXTI0_IRQHandler /* EXTI Line0 */
153 .word EXTI1_IRQHandler /* EXTI Line1 */
154 .word EXTI2_IRQHandler /* EXTI Line2 */
155 .word EXTI3_IRQHandler /* EXTI Line3 */
156 .word EXTI4_IRQHandler /* EXTI Line4 */
157 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
158 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
159 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
160 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
161 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
162 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
163 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
164 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
165 .word 0 /* Reserved */
166 .word 0 /* Reserved */
167 .word 0 /* Reserved */
168 .word 0 /* Reserved */
169 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
170 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
171 .word TIM1_UP_IRQHandler /* TIM1 Update */
172 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
173 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
174 .word 0 /* Reserved */
175 .word 0 /* Reserved */
176 .word 0 /* Reserved */
177 .word I2C1_EV_IRQHandler /* I2C1 Event */
178 .word I2C1_ER_IRQHandler /* I2C1 Error */
179 .word I2C2_EV_IRQHandler /* I2C2 Event */
180 .word I2C2_ER_IRQHandler /* I2C2 Error */
181 .word SPI1_IRQHandler /* SPI1 */
182 .word SPI2_IRQHandler /* SPI2 */
183 .word USART1_IRQHandler /* USART1 */
184 .word USART2_IRQHandler /* USART2 */
185 .word 0 /* Reserved */
186 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
187 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
188 .word 0 /* Reserved */
189 .word 0 /* Reserved */
190 .word 0 /* Reserved */
191 .word 0 /* Reserved */
192 .word 0 /* Reserved */
193 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
194 .word 0 /* Reserved */
195 .word 0 /* Reserved */
196 .word TIM5_IRQHandler /* TIM5 */
197 .word 0 /* Reserved */
198 .word 0 /* Reserved */
199 .word 0 /* Reserved */
200 .word TIM6_DAC_IRQHandler /* TIM6 and DAC */
201 .word 0 /* Reserved */
202 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
203 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
204 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
205 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
206 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
207 .word 0 /* Reserved */
208 .word 0 /* Reserved */
209 .word 0 /* Reserved */
210 .word 0 /* Reserved */
211 .word 0 /* Reserved */
212 .word 0 /* Reserved */
213 .word 0 /* Reserved */
214 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
215 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
216 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
217 .word USART6_IRQHandler /* USART6 */
218 .word 0 /* Reserved */
219 .word 0 /* Reserved */
220 .word 0 /* Reserved */
221 .word 0 /* Reserved */
222 .word 0 /* Reserved */
223 .word 0 /* Reserved */
224 .word 0 /* Reserved */
225 .word 0 /* Reserved */
226 .word RNG_IRQHandler /* RNG */
227 .word FPU_IRQHandler /* FPU */
228 .word 0 /* Reserved */
229 .word 0 /* Reserved */
230 .word 0 /* Reserved */
231 .word SPI5_IRQHandler /* SPI5 */
232 .word 0 /* Reserved */
233 .word 0 /* Reserved */
234 .word 0 /* Reserved */
235 .word 0 /* Reserved */
236 .word 0 /* Reserved */
237 .word 0 /* Reserved */
238 .word 0 /* Reserved */
239 .word 0 /* Reserved */
240 .word 0 /* Reserved */
241 .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */
242 .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */
243 .word LPTIM1_IRQHandler /* LP TIM1 */
244
245/*******************************************************************************
246*
247* Provide weak aliases for each Exception handler to the Default_Handler.
248* As they are weak aliases, any function with the same name will override
249* this definition.
250*
251*******************************************************************************/
252 .weak NMI_Handler
253 .thumb_set NMI_Handler,Default_Handler
254
255 .weak HardFault_Handler
256 .thumb_set HardFault_Handler,Default_Handler
257
258 .weak MemManage_Handler
259 .thumb_set MemManage_Handler,Default_Handler
260
261 .weak BusFault_Handler
262 .thumb_set BusFault_Handler,Default_Handler
263
264 .weak UsageFault_Handler
265 .thumb_set UsageFault_Handler,Default_Handler
266
267 .weak SVC_Handler
268 .thumb_set SVC_Handler,Default_Handler
269
270 .weak DebugMon_Handler
271 .thumb_set DebugMon_Handler,Default_Handler
272
273 .weak PendSV_Handler
274 .thumb_set PendSV_Handler,Default_Handler
275
276 .weak SysTick_Handler
277 .thumb_set SysTick_Handler,Default_Handler
278
279 .weak WWDG_IRQHandler
280 .thumb_set WWDG_IRQHandler,Default_Handler
281
282 .weak PVD_IRQHandler
283 .thumb_set PVD_IRQHandler,Default_Handler
284
285 .weak TAMP_STAMP_IRQHandler
286 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
287
288 .weak RTC_WKUP_IRQHandler
289 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
290
291 .weak FLASH_IRQHandler
292 .thumb_set FLASH_IRQHandler,Default_Handler
293
294 .weak RCC_IRQHandler
295 .thumb_set RCC_IRQHandler,Default_Handler
296
297 .weak EXTI0_IRQHandler
298 .thumb_set EXTI0_IRQHandler,Default_Handler
299
300 .weak EXTI1_IRQHandler
301 .thumb_set EXTI1_IRQHandler,Default_Handler
302
303 .weak EXTI2_IRQHandler
304 .thumb_set EXTI2_IRQHandler,Default_Handler
305
306 .weak EXTI3_IRQHandler
307 .thumb_set EXTI3_IRQHandler,Default_Handler
308
309 .weak EXTI4_IRQHandler
310 .thumb_set EXTI4_IRQHandler,Default_Handler
311
312 .weak DMA1_Stream0_IRQHandler
313 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
314
315 .weak DMA1_Stream1_IRQHandler
316 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
317
318 .weak DMA1_Stream2_IRQHandler
319 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
320
321 .weak DMA1_Stream3_IRQHandler
322 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
323
324 .weak DMA1_Stream4_IRQHandler
325 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
326
327 .weak DMA1_Stream5_IRQHandler
328 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
329
330 .weak DMA1_Stream6_IRQHandler
331 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
332
333 .weak ADC_IRQHandler
334 .thumb_set ADC_IRQHandler,Default_Handler
335
336 .weak EXTI9_5_IRQHandler
337 .thumb_set EXTI9_5_IRQHandler,Default_Handler
338
339 .weak TIM1_BRK_TIM9_IRQHandler
340 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
341
342 .weak TIM1_UP_IRQHandler
343 .thumb_set TIM1_UP_IRQHandler,Default_Handler
344
345 .weak TIM1_TRG_COM_TIM11_IRQHandler
346 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
347
348 .weak TIM1_CC_IRQHandler
349 .thumb_set TIM1_CC_IRQHandler,Default_Handler
350
351 .weak I2C1_EV_IRQHandler
352 .thumb_set I2C1_EV_IRQHandler,Default_Handler
353
354 .weak I2C1_ER_IRQHandler
355 .thumb_set I2C1_ER_IRQHandler,Default_Handler
356
357 .weak I2C2_EV_IRQHandler
358 .thumb_set I2C2_EV_IRQHandler,Default_Handler
359
360 .weak I2C2_ER_IRQHandler
361 .thumb_set I2C2_ER_IRQHandler,Default_Handler
362
363 .weak SPI1_IRQHandler
364 .thumb_set SPI1_IRQHandler,Default_Handler
365
366 .weak SPI2_IRQHandler
367 .thumb_set SPI2_IRQHandler,Default_Handler
368
369 .weak USART1_IRQHandler
370 .thumb_set USART1_IRQHandler,Default_Handler
371
372 .weak USART2_IRQHandler
373 .thumb_set USART2_IRQHandler,Default_Handler
374
375 .weak EXTI15_10_IRQHandler
376 .thumb_set EXTI15_10_IRQHandler,Default_Handler
377
378 .weak RTC_Alarm_IRQHandler
379 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
380
381 .weak DMA1_Stream7_IRQHandler
382 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
383
384 .weak TIM5_IRQHandler
385 .thumb_set TIM5_IRQHandler,Default_Handler
386
387 .weak TIM6_DAC_IRQHandler
388 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
389
390 .weak DMA2_Stream0_IRQHandler
391 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
392
393 .weak DMA2_Stream1_IRQHandler
394 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
395
396 .weak DMA2_Stream2_IRQHandler
397 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
398
399 .weak DMA2_Stream3_IRQHandler
400 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
401
402 .weak DMA2_Stream4_IRQHandler
403 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
404
405 .weak DMA2_Stream5_IRQHandler
406 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
407
408 .weak DMA2_Stream6_IRQHandler
409 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
410
411 .weak DMA2_Stream7_IRQHandler
412 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
413
414 .weak USART6_IRQHandler
415 .thumb_set USART6_IRQHandler,Default_Handler
416
417 .weak RNG_IRQHandler
418 .thumb_set RNG_IRQHandler,Default_Handler
419
420 .weak FPU_IRQHandler
421 .thumb_set FPU_IRQHandler,Default_Handler
422
423 .weak SPI5_IRQHandler
424 .thumb_set SPI5_IRQHandler,Default_Handler
425
426 .weak FMPI2C1_EV_IRQHandler
427 .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler
428
429 .weak FMPI2C1_ER_IRQHandler
430 .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler
431
432 .weak LPTIM1_IRQHandler
433 .thumb_set LPTIM1_IRQHandler,Default_Handler
434/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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