[1] | 1 | /**************************************************************************//**
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| 2 | * @file cmsis_armcc.h
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| 3 | * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
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| 4 | * @version V5.0.4
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| 5 | * @date 10. January 2018
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| 6 | ******************************************************************************/
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| 7 | /*
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| 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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| 9 | *
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| 10 | * SPDX-License-Identifier: Apache-2.0
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| 11 | *
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| 12 | * Licensed under the Apache License, Version 2.0 (the License); you may
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| 13 | * not use this file except in compliance with the License.
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| 14 | * You may obtain a copy of the License at
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| 15 | *
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| 16 | * www.apache.org/licenses/LICENSE-2.0
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| 17 | *
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| 18 | * Unless required by applicable law or agreed to in writing, software
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| 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 21 | * See the License for the specific language governing permissions and
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| 22 | * limitations under the License.
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| 23 | */
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| 24 |
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| 25 | #ifndef __CMSIS_ARMCC_H
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| 26 | #define __CMSIS_ARMCC_H
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| 27 |
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| 28 |
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| 29 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
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| 30 | #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
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| 31 | #endif
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| 32 |
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| 33 | /* CMSIS compiler control architecture macros */
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| 34 | #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
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| 35 | (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
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| 36 | #define __ARM_ARCH_6M__ 1
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| 37 | #endif
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| 38 |
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| 39 | #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
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| 40 | #define __ARM_ARCH_7M__ 1
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| 41 | #endif
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| 42 |
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| 43 | #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
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| 44 | #define __ARM_ARCH_7EM__ 1
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| 45 | #endif
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| 46 |
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| 47 | /* __ARM_ARCH_8M_BASE__ not applicable */
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| 48 | /* __ARM_ARCH_8M_MAIN__ not applicable */
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| 49 |
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| 50 |
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| 51 | /* CMSIS compiler specific defines */
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| 52 | #ifndef __ASM
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| 53 | #define __ASM __asm
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| 54 | #endif
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| 55 | #ifndef __INLINE
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| 56 | #define __INLINE __inline
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| 57 | #endif
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| 58 | #ifndef __STATIC_INLINE
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| 59 | #define __STATIC_INLINE static __inline
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| 60 | #endif
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| 61 | #ifndef __STATIC_FORCEINLINE
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| 62 | #define __STATIC_FORCEINLINE static __forceinline
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| 63 | #endif
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| 64 | #ifndef __NO_RETURN
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| 65 | #define __NO_RETURN __declspec(noreturn)
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| 66 | #endif
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| 67 | #ifndef __USED
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| 68 | #define __USED __attribute__((used))
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| 69 | #endif
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| 70 | #ifndef __WEAK
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| 71 | #define __WEAK __attribute__((weak))
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| 72 | #endif
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| 73 | #ifndef __PACKED
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| 74 | #define __PACKED __attribute__((packed))
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| 75 | #endif
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| 76 | #ifndef __PACKED_STRUCT
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| 77 | #define __PACKED_STRUCT __packed struct
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| 78 | #endif
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| 79 | #ifndef __PACKED_UNION
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| 80 | #define __PACKED_UNION __packed union
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| 81 | #endif
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| 82 | #ifndef __UNALIGNED_UINT32 /* deprecated */
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| 83 | #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
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| 84 | #endif
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| 85 | #ifndef __UNALIGNED_UINT16_WRITE
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| 86 | #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
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| 87 | #endif
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| 88 | #ifndef __UNALIGNED_UINT16_READ
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| 89 | #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
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| 90 | #endif
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| 91 | #ifndef __UNALIGNED_UINT32_WRITE
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| 92 | #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
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| 93 | #endif
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| 94 | #ifndef __UNALIGNED_UINT32_READ
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| 95 | #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
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| 96 | #endif
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| 97 | #ifndef __ALIGNED
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| 98 | #define __ALIGNED(x) __attribute__((aligned(x)))
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| 99 | #endif
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| 100 | #ifndef __RESTRICT
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| 101 | #define __RESTRICT __restrict
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| 102 | #endif
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| 103 |
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| 104 | /* ########################### Core Function Access ########################### */
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| 105 | /** \ingroup CMSIS_Core_FunctionInterface
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| 106 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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| 107 | @{
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| 108 | */
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| 109 |
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| 110 | /**
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| 111 | \brief Enable IRQ Interrupts
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| 112 | \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
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| 113 | Can only be executed in Privileged modes.
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| 114 | */
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| 115 | /* intrinsic void __enable_irq(); */
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| 116 |
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| 117 |
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| 118 | /**
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| 119 | \brief Disable IRQ Interrupts
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| 120 | \details Disables IRQ interrupts by setting the I-bit in the CPSR.
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| 121 | Can only be executed in Privileged modes.
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| 122 | */
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| 123 | /* intrinsic void __disable_irq(); */
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| 124 |
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| 125 | /**
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| 126 | \brief Get Control Register
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| 127 | \details Returns the content of the Control Register.
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| 128 | \return Control Register value
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| 129 | */
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| 130 | __STATIC_INLINE uint32_t __get_CONTROL(void)
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| 131 | {
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| 132 | register uint32_t __regControl __ASM("control");
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| 133 | return(__regControl);
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| 134 | }
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| 135 |
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| 136 |
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| 137 | /**
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| 138 | \brief Set Control Register
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| 139 | \details Writes the given value to the Control Register.
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| 140 | \param [in] control Control Register value to set
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| 141 | */
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| 142 | __STATIC_INLINE void __set_CONTROL(uint32_t control)
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| 143 | {
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| 144 | register uint32_t __regControl __ASM("control");
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| 145 | __regControl = control;
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| 146 | }
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| 147 |
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| 148 |
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| 149 | /**
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| 150 | \brief Get IPSR Register
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| 151 | \details Returns the content of the IPSR Register.
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| 152 | \return IPSR Register value
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| 153 | */
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| 154 | __STATIC_INLINE uint32_t __get_IPSR(void)
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| 155 | {
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| 156 | register uint32_t __regIPSR __ASM("ipsr");
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| 157 | return(__regIPSR);
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| 158 | }
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| 159 |
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| 160 |
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| 161 | /**
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| 162 | \brief Get APSR Register
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| 163 | \details Returns the content of the APSR Register.
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| 164 | \return APSR Register value
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| 165 | */
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| 166 | __STATIC_INLINE uint32_t __get_APSR(void)
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| 167 | {
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| 168 | register uint32_t __regAPSR __ASM("apsr");
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| 169 | return(__regAPSR);
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| 170 | }
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| 171 |
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| 172 |
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| 173 | /**
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| 174 | \brief Get xPSR Register
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| 175 | \details Returns the content of the xPSR Register.
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| 176 | \return xPSR Register value
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| 177 | */
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| 178 | __STATIC_INLINE uint32_t __get_xPSR(void)
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| 179 | {
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| 180 | register uint32_t __regXPSR __ASM("xpsr");
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| 181 | return(__regXPSR);
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| 182 | }
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| 183 |
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| 184 |
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| 185 | /**
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| 186 | \brief Get Process Stack Pointer
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| 187 | \details Returns the current value of the Process Stack Pointer (PSP).
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| 188 | \return PSP Register value
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| 189 | */
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| 190 | __STATIC_INLINE uint32_t __get_PSP(void)
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| 191 | {
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| 192 | register uint32_t __regProcessStackPointer __ASM("psp");
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| 193 | return(__regProcessStackPointer);
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| 194 | }
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| 195 |
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| 196 |
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| 197 | /**
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| 198 | \brief Set Process Stack Pointer
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| 199 | \details Assigns the given value to the Process Stack Pointer (PSP).
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| 200 | \param [in] topOfProcStack Process Stack Pointer value to set
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| 201 | */
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| 202 | __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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| 203 | {
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| 204 | register uint32_t __regProcessStackPointer __ASM("psp");
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| 205 | __regProcessStackPointer = topOfProcStack;
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| 206 | }
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| 207 |
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| 208 |
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| 209 | /**
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| 210 | \brief Get Main Stack Pointer
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| 211 | \details Returns the current value of the Main Stack Pointer (MSP).
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| 212 | \return MSP Register value
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| 213 | */
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| 214 | __STATIC_INLINE uint32_t __get_MSP(void)
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| 215 | {
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| 216 | register uint32_t __regMainStackPointer __ASM("msp");
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| 217 | return(__regMainStackPointer);
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| 218 | }
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| 219 |
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| 220 |
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| 221 | /**
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| 222 | \brief Set Main Stack Pointer
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| 223 | \details Assigns the given value to the Main Stack Pointer (MSP).
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| 224 | \param [in] topOfMainStack Main Stack Pointer value to set
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| 225 | */
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| 226 | __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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| 227 | {
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| 228 | register uint32_t __regMainStackPointer __ASM("msp");
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| 229 | __regMainStackPointer = topOfMainStack;
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| 230 | }
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| 231 |
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| 232 |
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| 233 | /**
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| 234 | \brief Get Priority Mask
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| 235 | \details Returns the current state of the priority mask bit from the Priority Mask Register.
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| 236 | \return Priority Mask value
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| 237 | */
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| 238 | __STATIC_INLINE uint32_t __get_PRIMASK(void)
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| 239 | {
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| 240 | register uint32_t __regPriMask __ASM("primask");
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| 241 | return(__regPriMask);
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| 242 | }
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| 243 |
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| 244 |
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| 245 | /**
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| 246 | \brief Set Priority Mask
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| 247 | \details Assigns the given value to the Priority Mask Register.
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| 248 | \param [in] priMask Priority Mask
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| 249 | */
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| 250 | __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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| 251 | {
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| 252 | register uint32_t __regPriMask __ASM("primask");
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| 253 | __regPriMask = (priMask);
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| 254 | }
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| 255 |
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| 256 |
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| 257 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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| 258 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
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| 259 |
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| 260 | /**
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| 261 | \brief Enable FIQ
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| 262 | \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
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| 263 | Can only be executed in Privileged modes.
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| 264 | */
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| 265 | #define __enable_fault_irq __enable_fiq
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| 266 |
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| 267 |
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| 268 | /**
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| 269 | \brief Disable FIQ
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| 270 | \details Disables FIQ interrupts by setting the F-bit in the CPSR.
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| 271 | Can only be executed in Privileged modes.
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| 272 | */
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| 273 | #define __disable_fault_irq __disable_fiq
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| 274 |
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| 275 |
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| 276 | /**
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| 277 | \brief Get Base Priority
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| 278 | \details Returns the current value of the Base Priority register.
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| 279 | \return Base Priority register value
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| 280 | */
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| 281 | __STATIC_INLINE uint32_t __get_BASEPRI(void)
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| 282 | {
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| 283 | register uint32_t __regBasePri __ASM("basepri");
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| 284 | return(__regBasePri);
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| 285 | }
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| 286 |
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| 287 |
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| 288 | /**
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| 289 | \brief Set Base Priority
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| 290 | \details Assigns the given value to the Base Priority register.
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| 291 | \param [in] basePri Base Priority value to set
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| 292 | */
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| 293 | __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
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| 294 | {
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| 295 | register uint32_t __regBasePri __ASM("basepri");
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| 296 | __regBasePri = (basePri & 0xFFU);
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| 297 | }
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| 298 |
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| 299 |
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| 300 | /**
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| 301 | \brief Set Base Priority with condition
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| 302 | \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
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| 303 | or the new value increases the BASEPRI priority level.
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| 304 | \param [in] basePri Base Priority value to set
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| 305 | */
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| 306 | __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
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| 307 | {
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| 308 | register uint32_t __regBasePriMax __ASM("basepri_max");
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| 309 | __regBasePriMax = (basePri & 0xFFU);
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| 310 | }
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| 311 |
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| 312 |
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| 313 | /**
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| 314 | \brief Get Fault Mask
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| 315 | \details Returns the current value of the Fault Mask register.
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| 316 | \return Fault Mask register value
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| 317 | */
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| 318 | __STATIC_INLINE uint32_t __get_FAULTMASK(void)
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| 319 | {
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| 320 | register uint32_t __regFaultMask __ASM("faultmask");
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| 321 | return(__regFaultMask);
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| 322 | }
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| 323 |
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| 324 |
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| 325 | /**
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| 326 | \brief Set Fault Mask
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| 327 | \details Assigns the given value to the Fault Mask register.
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| 328 | \param [in] faultMask Fault Mask value to set
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| 329 | */
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| 330 | __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
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| 331 | {
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| 332 | register uint32_t __regFaultMask __ASM("faultmask");
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| 333 | __regFaultMask = (faultMask & (uint32_t)1U);
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| 334 | }
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| 335 |
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| 336 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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| 337 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
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| 338 |
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| 339 |
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| 340 | /**
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| 341 | \brief Get FPSCR
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| 342 | \details Returns the current value of the Floating Point Status/Control register.
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| 343 | \return Floating Point Status/Control register value
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| 344 | */
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| 345 | __STATIC_INLINE uint32_t __get_FPSCR(void)
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| 346 | {
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| 347 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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| 348 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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| 349 | register uint32_t __regfpscr __ASM("fpscr");
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| 350 | return(__regfpscr);
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| 351 | #else
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| 352 | return(0U);
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| 353 | #endif
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| 354 | }
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| 355 |
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| 356 |
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| 357 | /**
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| 358 | \brief Set FPSCR
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| 359 | \details Assigns the given value to the Floating Point Status/Control register.
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| 360 | \param [in] fpscr Floating Point Status/Control value to set
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| 361 | */
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| 362 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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| 363 | {
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| 364 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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| 365 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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| 366 | register uint32_t __regfpscr __ASM("fpscr");
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| 367 | __regfpscr = (fpscr);
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| 368 | #else
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| 369 | (void)fpscr;
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| 370 | #endif
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| 371 | }
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| 372 |
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| 373 |
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| 374 | /*@} end of CMSIS_Core_RegAccFunctions */
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| 375 |
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| 376 |
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| 377 | /* ########################## Core Instruction Access ######################### */
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| 378 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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| 379 | Access to dedicated instructions
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| 380 | @{
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| 381 | */
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| 382 |
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| 383 | /**
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| 384 | \brief No Operation
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| 385 | \details No Operation does nothing. This instruction can be used for code alignment purposes.
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| 386 | */
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| 387 | #define __NOP __nop
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| 388 |
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| 389 |
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| 390 | /**
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| 391 | \brief Wait For Interrupt
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| 392 | \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
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| 393 | */
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| 394 | #define __WFI __wfi
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| 395 |
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| 396 |
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| 397 | /**
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| 398 | \brief Wait For Event
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| 399 | \details Wait For Event is a hint instruction that permits the processor to enter
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| 400 | a low-power state until one of a number of events occurs.
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| 401 | */
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| 402 | #define __WFE __wfe
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| 403 |
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| 404 |
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| 405 | /**
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| 406 | \brief Send Event
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| 407 | \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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| 408 | */
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| 409 | #define __SEV __sev
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| 410 |
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| 411 |
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| 412 | /**
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| 413 | \brief Instruction Synchronization Barrier
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| 414 | \details Instruction Synchronization Barrier flushes the pipeline in the processor,
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| 415 | so that all instructions following the ISB are fetched from cache or memory,
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| 416 | after the instruction has been completed.
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| 417 | */
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| 418 | #define __ISB() do {\
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| 419 | __schedule_barrier();\
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| 420 | __isb(0xF);\
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| 421 | __schedule_barrier();\
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| 422 | } while (0U)
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| 423 |
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| 424 | /**
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| 425 | \brief Data Synchronization Barrier
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| 426 | \details Acts as a special kind of Data Memory Barrier.
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| 427 | It completes when all explicit memory accesses before this instruction complete.
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| 428 | */
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| 429 | #define __DSB() do {\
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| 430 | __schedule_barrier();\
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| 431 | __dsb(0xF);\
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| 432 | __schedule_barrier();\
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| 433 | } while (0U)
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| 434 |
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| 435 | /**
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| 436 | \brief Data Memory Barrier
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| 437 | \details Ensures the apparent order of the explicit memory operations before
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| 438 | and after the instruction, without ensuring their completion.
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| 439 | */
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| 440 | #define __DMB() do {\
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| 441 | __schedule_barrier();\
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| 442 | __dmb(0xF);\
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| 443 | __schedule_barrier();\
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| 444 | } while (0U)
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| 445 |
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| 446 |
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| 447 | /**
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| 448 | \brief Reverse byte order (32 bit)
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| 449 | \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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| 450 | \param [in] value Value to reverse
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| 451 | \return Reversed value
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| 452 | */
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| 453 | #define __REV __rev
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| 454 |
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| 455 |
|
---|
| 456 | /**
|
---|
| 457 | \brief Reverse byte order (16 bit)
|
---|
| 458 | \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
---|
| 459 | \param [in] value Value to reverse
|
---|
| 460 | \return Reversed value
|
---|
| 461 | */
|
---|
| 462 | #ifndef __NO_EMBEDDED_ASM
|
---|
| 463 | __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
---|
| 464 | {
|
---|
| 465 | rev16 r0, r0
|
---|
| 466 | bx lr
|
---|
| 467 | }
|
---|
| 468 | #endif
|
---|
| 469 |
|
---|
| 470 |
|
---|
| 471 | /**
|
---|
| 472 | \brief Reverse byte order (16 bit)
|
---|
| 473 | \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
---|
| 474 | \param [in] value Value to reverse
|
---|
| 475 | \return Reversed value
|
---|
| 476 | */
|
---|
| 477 | #ifndef __NO_EMBEDDED_ASM
|
---|
| 478 | __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
---|
| 479 | {
|
---|
| 480 | revsh r0, r0
|
---|
| 481 | bx lr
|
---|
| 482 | }
|
---|
| 483 | #endif
|
---|
| 484 |
|
---|
| 485 |
|
---|
| 486 | /**
|
---|
| 487 | \brief Rotate Right in unsigned value (32 bit)
|
---|
| 488 | \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
---|
| 489 | \param [in] op1 Value to rotate
|
---|
| 490 | \param [in] op2 Number of Bits to rotate
|
---|
| 491 | \return Rotated value
|
---|
| 492 | */
|
---|
| 493 | #define __ROR __ror
|
---|
| 494 |
|
---|
| 495 |
|
---|
| 496 | /**
|
---|
| 497 | \brief Breakpoint
|
---|
| 498 | \details Causes the processor to enter Debug state.
|
---|
| 499 | Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
---|
| 500 | \param [in] value is ignored by the processor.
|
---|
| 501 | If required, a debugger can use it to store additional information about the breakpoint.
|
---|
| 502 | */
|
---|
| 503 | #define __BKPT(value) __breakpoint(value)
|
---|
| 504 |
|
---|
| 505 |
|
---|
| 506 | /**
|
---|
| 507 | \brief Reverse bit order of value
|
---|
| 508 | \details Reverses the bit order of the given value.
|
---|
| 509 | \param [in] value Value to reverse
|
---|
| 510 | \return Reversed value
|
---|
| 511 | */
|
---|
| 512 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
---|
| 513 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
---|
| 514 | #define __RBIT __rbit
|
---|
| 515 | #else
|
---|
| 516 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
---|
| 517 | {
|
---|
| 518 | uint32_t result;
|
---|
| 519 | uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
---|
| 520 |
|
---|
| 521 | result = value; /* r will be reversed bits of v; first get LSB of v */
|
---|
| 522 | for (value >>= 1U; value != 0U; value >>= 1U)
|
---|
| 523 | {
|
---|
| 524 | result <<= 1U;
|
---|
| 525 | result |= value & 1U;
|
---|
| 526 | s--;
|
---|
| 527 | }
|
---|
| 528 | result <<= s; /* shift when v's highest bits are zero */
|
---|
| 529 | return result;
|
---|
| 530 | }
|
---|
| 531 | #endif
|
---|
| 532 |
|
---|
| 533 |
|
---|
| 534 | /**
|
---|
| 535 | \brief Count leading zeros
|
---|
| 536 | \details Counts the number of leading zeros of a data value.
|
---|
| 537 | \param [in] value Value to count the leading zeros
|
---|
| 538 | \return number of leading zeros in value
|
---|
| 539 | */
|
---|
| 540 | #define __CLZ __clz
|
---|
| 541 |
|
---|
| 542 |
|
---|
| 543 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
---|
| 544 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
---|
| 545 |
|
---|
| 546 | /**
|
---|
| 547 | \brief LDR Exclusive (8 bit)
|
---|
| 548 | \details Executes a exclusive LDR instruction for 8 bit value.
|
---|
| 549 | \param [in] ptr Pointer to data
|
---|
| 550 | \return value of type uint8_t at (*ptr)
|
---|
| 551 | */
|
---|
| 552 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
---|
| 553 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
---|
| 554 | #else
|
---|
| 555 | #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
---|
| 556 | #endif
|
---|
| 557 |
|
---|
| 558 |
|
---|
| 559 | /**
|
---|
| 560 | \brief LDR Exclusive (16 bit)
|
---|
| 561 | \details Executes a exclusive LDR instruction for 16 bit values.
|
---|
| 562 | \param [in] ptr Pointer to data
|
---|
| 563 | \return value of type uint16_t at (*ptr)
|
---|
| 564 | */
|
---|
| 565 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
---|
| 566 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
---|
| 567 | #else
|
---|
| 568 | #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
---|
| 569 | #endif
|
---|
| 570 |
|
---|
| 571 |
|
---|
| 572 | /**
|
---|
| 573 | \brief LDR Exclusive (32 bit)
|
---|
| 574 | \details Executes a exclusive LDR instruction for 32 bit values.
|
---|
| 575 | \param [in] ptr Pointer to data
|
---|
| 576 | \return value of type uint32_t at (*ptr)
|
---|
| 577 | */
|
---|
| 578 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
---|
| 579 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
---|
| 580 | #else
|
---|
| 581 | #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
---|
| 582 | #endif
|
---|
| 583 |
|
---|
| 584 |
|
---|
| 585 | /**
|
---|
| 586 | \brief STR Exclusive (8 bit)
|
---|
| 587 | \details Executes a exclusive STR instruction for 8 bit values.
|
---|
| 588 | \param [in] value Value to store
|
---|
| 589 | \param [in] ptr Pointer to location
|
---|
| 590 | \return 0 Function succeeded
|
---|
| 591 | \return 1 Function failed
|
---|
| 592 | */
|
---|
| 593 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
---|
| 594 | #define __STREXB(value, ptr) __strex(value, ptr)
|
---|
| 595 | #else
|
---|
| 596 | #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
---|
| 597 | #endif
|
---|
| 598 |
|
---|
| 599 |
|
---|
| 600 | /**
|
---|
| 601 | \brief STR Exclusive (16 bit)
|
---|
| 602 | \details Executes a exclusive STR instruction for 16 bit values.
|
---|
| 603 | \param [in] value Value to store
|
---|
| 604 | \param [in] ptr Pointer to location
|
---|
| 605 | \return 0 Function succeeded
|
---|
| 606 | \return 1 Function failed
|
---|
| 607 | */
|
---|
| 608 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
---|
| 609 | #define __STREXH(value, ptr) __strex(value, ptr)
|
---|
| 610 | #else
|
---|
| 611 | #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
---|
| 612 | #endif
|
---|
| 613 |
|
---|
| 614 |
|
---|
| 615 | /**
|
---|
| 616 | \brief STR Exclusive (32 bit)
|
---|
| 617 | \details Executes a exclusive STR instruction for 32 bit values.
|
---|
| 618 | \param [in] value Value to store
|
---|
| 619 | \param [in] ptr Pointer to location
|
---|
| 620 | \return 0 Function succeeded
|
---|
| 621 | \return 1 Function failed
|
---|
| 622 | */
|
---|
| 623 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
---|
| 624 | #define __STREXW(value, ptr) __strex(value, ptr)
|
---|
| 625 | #else
|
---|
| 626 | #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
---|
| 627 | #endif
|
---|
| 628 |
|
---|
| 629 |
|
---|
| 630 | /**
|
---|
| 631 | \brief Remove the exclusive lock
|
---|
| 632 | \details Removes the exclusive lock which is created by LDREX.
|
---|
| 633 | */
|
---|
| 634 | #define __CLREX __clrex
|
---|
| 635 |
|
---|
| 636 |
|
---|
| 637 | /**
|
---|
| 638 | \brief Signed Saturate
|
---|
| 639 | \details Saturates a signed value.
|
---|
| 640 | \param [in] value Value to be saturated
|
---|
| 641 | \param [in] sat Bit position to saturate to (1..32)
|
---|
| 642 | \return Saturated value
|
---|
| 643 | */
|
---|
| 644 | #define __SSAT __ssat
|
---|
| 645 |
|
---|
| 646 |
|
---|
| 647 | /**
|
---|
| 648 | \brief Unsigned Saturate
|
---|
| 649 | \details Saturates an unsigned value.
|
---|
| 650 | \param [in] value Value to be saturated
|
---|
| 651 | \param [in] sat Bit position to saturate to (0..31)
|
---|
| 652 | \return Saturated value
|
---|
| 653 | */
|
---|
| 654 | #define __USAT __usat
|
---|
| 655 |
|
---|
| 656 |
|
---|
| 657 | /**
|
---|
| 658 | \brief Rotate Right with Extend (32 bit)
|
---|
| 659 | \details Moves each bit of a bitstring right by one bit.
|
---|
| 660 | The carry input is shifted in at the left end of the bitstring.
|
---|
| 661 | \param [in] value Value to rotate
|
---|
| 662 | \return Rotated value
|
---|
| 663 | */
|
---|
| 664 | #ifndef __NO_EMBEDDED_ASM
|
---|
| 665 | __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
---|
| 666 | {
|
---|
| 667 | rrx r0, r0
|
---|
| 668 | bx lr
|
---|
| 669 | }
|
---|
| 670 | #endif
|
---|
| 671 |
|
---|
| 672 |
|
---|
| 673 | /**
|
---|
| 674 | \brief LDRT Unprivileged (8 bit)
|
---|
| 675 | \details Executes a Unprivileged LDRT instruction for 8 bit value.
|
---|
| 676 | \param [in] ptr Pointer to data
|
---|
| 677 | \return value of type uint8_t at (*ptr)
|
---|
| 678 | */
|
---|
| 679 | #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
---|
| 680 |
|
---|
| 681 |
|
---|
| 682 | /**
|
---|
| 683 | \brief LDRT Unprivileged (16 bit)
|
---|
| 684 | \details Executes a Unprivileged LDRT instruction for 16 bit values.
|
---|
| 685 | \param [in] ptr Pointer to data
|
---|
| 686 | \return value of type uint16_t at (*ptr)
|
---|
| 687 | */
|
---|
| 688 | #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
---|
| 689 |
|
---|
| 690 |
|
---|
| 691 | /**
|
---|
| 692 | \brief LDRT Unprivileged (32 bit)
|
---|
| 693 | \details Executes a Unprivileged LDRT instruction for 32 bit values.
|
---|
| 694 | \param [in] ptr Pointer to data
|
---|
| 695 | \return value of type uint32_t at (*ptr)
|
---|
| 696 | */
|
---|
| 697 | #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
---|
| 698 |
|
---|
| 699 |
|
---|
| 700 | /**
|
---|
| 701 | \brief STRT Unprivileged (8 bit)
|
---|
| 702 | \details Executes a Unprivileged STRT instruction for 8 bit values.
|
---|
| 703 | \param [in] value Value to store
|
---|
| 704 | \param [in] ptr Pointer to location
|
---|
| 705 | */
|
---|
| 706 | #define __STRBT(value, ptr) __strt(value, ptr)
|
---|
| 707 |
|
---|
| 708 |
|
---|
| 709 | /**
|
---|
| 710 | \brief STRT Unprivileged (16 bit)
|
---|
| 711 | \details Executes a Unprivileged STRT instruction for 16 bit values.
|
---|
| 712 | \param [in] value Value to store
|
---|
| 713 | \param [in] ptr Pointer to location
|
---|
| 714 | */
|
---|
| 715 | #define __STRHT(value, ptr) __strt(value, ptr)
|
---|
| 716 |
|
---|
| 717 |
|
---|
| 718 | /**
|
---|
| 719 | \brief STRT Unprivileged (32 bit)
|
---|
| 720 | \details Executes a Unprivileged STRT instruction for 32 bit values.
|
---|
| 721 | \param [in] value Value to store
|
---|
| 722 | \param [in] ptr Pointer to location
|
---|
| 723 | */
|
---|
| 724 | #define __STRT(value, ptr) __strt(value, ptr)
|
---|
| 725 |
|
---|
| 726 | #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
---|
| 727 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
---|
| 728 |
|
---|
| 729 | /**
|
---|
| 730 | \brief Signed Saturate
|
---|
| 731 | \details Saturates a signed value.
|
---|
| 732 | \param [in] value Value to be saturated
|
---|
| 733 | \param [in] sat Bit position to saturate to (1..32)
|
---|
| 734 | \return Saturated value
|
---|
| 735 | */
|
---|
| 736 | __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
---|
| 737 | {
|
---|
| 738 | if ((sat >= 1U) && (sat <= 32U))
|
---|
| 739 | {
|
---|
| 740 | const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
---|
| 741 | const int32_t min = -1 - max ;
|
---|
| 742 | if (val > max)
|
---|
| 743 | {
|
---|
| 744 | return max;
|
---|
| 745 | }
|
---|
| 746 | else if (val < min)
|
---|
| 747 | {
|
---|
| 748 | return min;
|
---|
| 749 | }
|
---|
| 750 | }
|
---|
| 751 | return val;
|
---|
| 752 | }
|
---|
| 753 |
|
---|
| 754 | /**
|
---|
| 755 | \brief Unsigned Saturate
|
---|
| 756 | \details Saturates an unsigned value.
|
---|
| 757 | \param [in] value Value to be saturated
|
---|
| 758 | \param [in] sat Bit position to saturate to (0..31)
|
---|
| 759 | \return Saturated value
|
---|
| 760 | */
|
---|
| 761 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
---|
| 762 | {
|
---|
| 763 | if (sat <= 31U)
|
---|
| 764 | {
|
---|
| 765 | const uint32_t max = ((1U << sat) - 1U);
|
---|
| 766 | if (val > (int32_t)max)
|
---|
| 767 | {
|
---|
| 768 | return max;
|
---|
| 769 | }
|
---|
| 770 | else if (val < 0)
|
---|
| 771 | {
|
---|
| 772 | return 0U;
|
---|
| 773 | }
|
---|
| 774 | }
|
---|
| 775 | return (uint32_t)val;
|
---|
| 776 | }
|
---|
| 777 |
|
---|
| 778 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
---|
| 779 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
---|
| 780 |
|
---|
| 781 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
---|
| 782 |
|
---|
| 783 |
|
---|
| 784 | /* ################### Compiler specific Intrinsics ########################### */
|
---|
| 785 | /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
---|
| 786 | Access to dedicated SIMD instructions
|
---|
| 787 | @{
|
---|
| 788 | */
|
---|
| 789 |
|
---|
| 790 | #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
---|
| 791 |
|
---|
| 792 | #define __SADD8 __sadd8
|
---|
| 793 | #define __QADD8 __qadd8
|
---|
| 794 | #define __SHADD8 __shadd8
|
---|
| 795 | #define __UADD8 __uadd8
|
---|
| 796 | #define __UQADD8 __uqadd8
|
---|
| 797 | #define __UHADD8 __uhadd8
|
---|
| 798 | #define __SSUB8 __ssub8
|
---|
| 799 | #define __QSUB8 __qsub8
|
---|
| 800 | #define __SHSUB8 __shsub8
|
---|
| 801 | #define __USUB8 __usub8
|
---|
| 802 | #define __UQSUB8 __uqsub8
|
---|
| 803 | #define __UHSUB8 __uhsub8
|
---|
| 804 | #define __SADD16 __sadd16
|
---|
| 805 | #define __QADD16 __qadd16
|
---|
| 806 | #define __SHADD16 __shadd16
|
---|
| 807 | #define __UADD16 __uadd16
|
---|
| 808 | #define __UQADD16 __uqadd16
|
---|
| 809 | #define __UHADD16 __uhadd16
|
---|
| 810 | #define __SSUB16 __ssub16
|
---|
| 811 | #define __QSUB16 __qsub16
|
---|
| 812 | #define __SHSUB16 __shsub16
|
---|
| 813 | #define __USUB16 __usub16
|
---|
| 814 | #define __UQSUB16 __uqsub16
|
---|
| 815 | #define __UHSUB16 __uhsub16
|
---|
| 816 | #define __SASX __sasx
|
---|
| 817 | #define __QASX __qasx
|
---|
| 818 | #define __SHASX __shasx
|
---|
| 819 | #define __UASX __uasx
|
---|
| 820 | #define __UQASX __uqasx
|
---|
| 821 | #define __UHASX __uhasx
|
---|
| 822 | #define __SSAX __ssax
|
---|
| 823 | #define __QSAX __qsax
|
---|
| 824 | #define __SHSAX __shsax
|
---|
| 825 | #define __USAX __usax
|
---|
| 826 | #define __UQSAX __uqsax
|
---|
| 827 | #define __UHSAX __uhsax
|
---|
| 828 | #define __USAD8 __usad8
|
---|
| 829 | #define __USADA8 __usada8
|
---|
| 830 | #define __SSAT16 __ssat16
|
---|
| 831 | #define __USAT16 __usat16
|
---|
| 832 | #define __UXTB16 __uxtb16
|
---|
| 833 | #define __UXTAB16 __uxtab16
|
---|
| 834 | #define __SXTB16 __sxtb16
|
---|
| 835 | #define __SXTAB16 __sxtab16
|
---|
| 836 | #define __SMUAD __smuad
|
---|
| 837 | #define __SMUADX __smuadx
|
---|
| 838 | #define __SMLAD __smlad
|
---|
| 839 | #define __SMLADX __smladx
|
---|
| 840 | #define __SMLALD __smlald
|
---|
| 841 | #define __SMLALDX __smlaldx
|
---|
| 842 | #define __SMUSD __smusd
|
---|
| 843 | #define __SMUSDX __smusdx
|
---|
| 844 | #define __SMLSD __smlsd
|
---|
| 845 | #define __SMLSDX __smlsdx
|
---|
| 846 | #define __SMLSLD __smlsld
|
---|
| 847 | #define __SMLSLDX __smlsldx
|
---|
| 848 | #define __SEL __sel
|
---|
| 849 | #define __QADD __qadd
|
---|
| 850 | #define __QSUB __qsub
|
---|
| 851 |
|
---|
| 852 | #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
---|
| 853 | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
---|
| 854 |
|
---|
| 855 | #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
---|
| 856 | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
---|
| 857 |
|
---|
| 858 | #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
---|
| 859 | ((int64_t)(ARG3) << 32U) ) >> 32U))
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| 860 |
|
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| 861 | #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
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| 862 | /*@} end of group CMSIS_SIMD_intrinsics */
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| 863 |
|
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| 864 |
|
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| 865 | #endif /* __CMSIS_ARMCC_H */
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