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core_armv8mml.h

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1	/************************************************************************//
2	* @file core_armv8mml.h
3	* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
4	* @version V5.0.7
5	* @date 06. July 2018
6	******************************************************************************/
7	/*
8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9	*
10	* SPDX-License-Identifier: Apache-2.0
11	*
12	* Licensed under the Apache License, Version 2.0 (the License); you may
13	* not use this file except in compliance with the License.
14	* You may obtain a copy of the License at
15	*
16	* www.apache.org/licenses/LICENSE-2.0
17	*
18	* Unless required by applicable law or agreed to in writing, software
19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21	* See the License for the specific language governing permissions and
22	* limitations under the License.
23	*/
24
25	#if defined ( __ICCARM__ )
26	#pragma system_include /* treat file as system include file for MISRA check */
27	#elif defined (__clang__)
28	#pragma clang system_header /* treat file as system include file */
29	#endif
30
31	#ifndef __CORE_ARMV8MML_H_GENERIC
32	#define __CORE_ARMV8MML_H_GENERIC
33
34	#include <stdint.h>
35
36	#ifdef __cplusplus
37	extern "C" {
38	#endif
39
40	/**
41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42	CMSIS violates the following MISRA-C:2004 rules:
43
44	\li Required Rule 8.5, object/function definition in header file.<br>
45	Function definitions in header files are used to allow 'inlining'.
46
47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48	Unions are used for effective representation of core registers.
49
50	\li Advisory Rule 19.7, Function-like macro defined.<br>
51	Function-like macros are used to allow more efficient code.
52	*/
53
54
55	/*******************************************************************************
56	* CMSIS definitions
57	******************************************************************************/
58	/**
59	\ingroup Cortex_ARMv8MML
60	@{
61	*/
62
63	#include "cmsis_version.h"
64
65	/* CMSIS Armv8MML definitions */
66	#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
67	#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
68	#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) \| \
69	__ARMv8MML_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
70
71	#define __CORTEX_M (81U) /!< Cortex-M Core /
72
73	/** __FPU_USED indicates whether an FPU is used or not.
74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
75	*/
76	#if defined ( __CC_ARM )
77	#if defined __TARGET_FPU_VFP
78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79	#define __FPU_USED 1U
80	#else
81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82	#define __FPU_USED 0U
83	#endif
84	#else
85	#define __FPU_USED 0U
86	#endif
87
88	#if defined(__ARM_FEATURE_DSP)
89	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
90	#define __DSP_USED 1U
91	#else
92	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
93	#define __DSP_USED 0U
94	#endif
95	#else
96	#define __DSP_USED 0U
97	#endif
98
99	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
100	#if defined __ARM_PCS_VFP
101	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
102	#define __FPU_USED 1U
103	#else
104	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
105	#define __FPU_USED 0U
106	#endif
107	#else
108	#define __FPU_USED 0U
109	#endif
110
111	#if defined(__ARM_FEATURE_DSP)
112	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
113	#define __DSP_USED 1U
114	#else
115	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
116	#define __DSP_USED 0U
117	#endif
118	#else
119	#define __DSP_USED 0U
120	#endif
121
122	#elif defined ( __GNUC__ )
123	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
125	#define __FPU_USED 1U
126	#else
127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128	#define __FPU_USED 0U
129	#endif
130	#else
131	#define __FPU_USED 0U
132	#endif
133
134	#if defined(__ARM_FEATURE_DSP)
135	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
136	#define __DSP_USED 1U
137	#else
138	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
139	#define __DSP_USED 0U
140	#endif
141	#else
142	#define __DSP_USED 0U
143	#endif
144
145	#elif defined ( __ICCARM__ )
146	#if defined __ARMVFP__
147	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
148	#define __FPU_USED 1U
149	#else
150	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
151	#define __FPU_USED 0U
152	#endif
153	#else
154	#define __FPU_USED 0U
155	#endif
156
157	#if defined(__ARM_FEATURE_DSP)
158	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
159	#define __DSP_USED 1U
160	#else
161	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
162	#define __DSP_USED 0U
163	#endif
164	#else
165	#define __DSP_USED 0U
166	#endif
167
168	#elif defined ( __TI_ARM__ )
169	#if defined __TI_VFP_SUPPORT__
170	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
171	#define __FPU_USED 1U
172	#else
173	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
174	#define __FPU_USED 0U
175	#endif
176	#else
177	#define __FPU_USED 0U
178	#endif
179
180	#elif defined ( __TASKING__ )
181	#if defined __FPU_VFP__
182	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
183	#define __FPU_USED 1U
184	#else
185	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
186	#define __FPU_USED 0U
187	#endif
188	#else
189	#define __FPU_USED 0U
190	#endif
191
192	#elif defined ( __CSMC__ )
193	#if ( __CSMC__ & 0x400U)
194	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
195	#define __FPU_USED 1U
196	#else
197	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
198	#define __FPU_USED 0U
199	#endif
200	#else
201	#define __FPU_USED 0U
202	#endif
203
204	#endif
205
206	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
207
208
209	#ifdef __cplusplus
210	}
211	#endif
212
213	#endif /* __CORE_ARMV8MML_H_GENERIC */
214
215	#ifndef __CMSIS_GENERIC
216
217	#ifndef __CORE_ARMV8MML_H_DEPENDANT
218	#define __CORE_ARMV8MML_H_DEPENDANT
219
220	#ifdef __cplusplus
221	extern "C" {
222	#endif
223
224	/* check device defines and use defaults */
225	#if defined __CHECK_DEVICE_DEFINES
226	#ifndef __ARMv8MML_REV
227	#define __ARMv8MML_REV 0x0000U
228	#warning "__ARMv8MML_REV not defined in device header file; using default!"
229	#endif
230
231	#ifndef __FPU_PRESENT
232	#define __FPU_PRESENT 0U
233	#warning "__FPU_PRESENT not defined in device header file; using default!"
234	#endif
235
236	#ifndef __MPU_PRESENT
237	#define __MPU_PRESENT 0U
238	#warning "__MPU_PRESENT not defined in device header file; using default!"
239	#endif
240
241	#ifndef __SAUREGION_PRESENT
242	#define __SAUREGION_PRESENT 0U
243	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
244	#endif
245
246	#ifndef __DSP_PRESENT
247	#define __DSP_PRESENT 0U
248	#warning "__DSP_PRESENT not defined in device header file; using default!"
249	#endif
250
251	#ifndef __NVIC_PRIO_BITS
252	#define __NVIC_PRIO_BITS 3U
253	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
254	#endif
255
256	#ifndef __Vendor_SysTickConfig
257	#define __Vendor_SysTickConfig 0U
258	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
259	#endif
260	#endif
261
262	/* IO definitions (access restrictions to peripheral registers) */
263	/**
264	\defgroup CMSIS_glob_defs CMSIS Global Defines
265
266	<strong>IO Type Qualifiers</strong> are used
267	\li to specify the access to peripheral variables.
268	\li for automatic generation of peripheral register debug information.
269	*/
270	#ifdef __cplusplus
271	#define __I volatile /!< Defines 'read only' permissions /
272	#else
273	#define __I volatile const /!< Defines 'read only' permissions /
274	#endif
275	#define __O volatile /!< Defines 'write only' permissions /
276	#define __IO volatile /!< Defines 'read / write' permissions /
277
278	/* following defines should be used for structure members */
279	#define __IM volatile const /! Defines 'read only' structure member permissions /
280	#define __OM volatile /! Defines 'write only' structure member permissions /
281	#define __IOM volatile /! Defines 'read / write' structure member permissions /
282
283	/@} end of group ARMv8MML /
284
285
286
287	/*******************************************************************************
288	* Register Abstraction
289	Core Register contain:
290	- Core Register
291	- Core NVIC Register
292	- Core SCB Register
293	- Core SysTick Register
294	- Core Debug Register
295	- Core MPU Register
296	- Core SAU Register
297	- Core FPU Register
298	******************************************************************************/
299	/**
300	\defgroup CMSIS_core_register Defines and Type Definitions
301	\brief Type definitions and defines for Cortex-M processor based devices.
302	*/
303
304	/**
305	\ingroup CMSIS_core_register
306	\defgroup CMSIS_CORE Status and Control Registers
307	\brief Core Register type definitions.
308	@{
309	*/
310
311	/**
312	\brief Union type to access the Application Program Status Register (APSR).
313	*/
314	typedef union
315	{
316	struct
317	{
318	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
319	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
320	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
321	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
322	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
323	uint32_t C:1; /!< bit: 29 Carry condition code flag /
324	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
325	uint32_t N:1; /!< bit: 31 Negative condition code flag /
326	} b; /!< Structure used for bit access /
327	uint32_t w; /!< Type used for word access /
328	} APSR_Type;
329
330	/* APSR Register Definitions */
331	#define APSR_N_Pos 31U /!< APSR: N Position /
332	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
333
334	#define APSR_Z_Pos 30U /!< APSR: Z Position /
335	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
336
337	#define APSR_C_Pos 29U /!< APSR: C Position /
338	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
339
340	#define APSR_V_Pos 28U /!< APSR: V Position /
341	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
342
343	#define APSR_Q_Pos 27U /!< APSR: Q Position /
344	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
345
346	#define APSR_GE_Pos 16U /!< APSR: GE Position /
347	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
348
349
350	/**
351	\brief Union type to access the Interrupt Program Status Register (IPSR).
352	*/
353	typedef union
354	{
355	struct
356	{
357	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
358	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
359	} b; /!< Structure used for bit access /
360	uint32_t w; /!< Type used for word access /
361	} IPSR_Type;
362
363	/* IPSR Register Definitions */
364	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
365	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
366
367
368	/**
369	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
370	*/
371	typedef union
372	{
373	struct
374	{
375	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
376	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
377	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
378	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
379	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
380	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
381	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
382	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
383	uint32_t C:1; /!< bit: 29 Carry condition code flag /
384	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
385	uint32_t N:1; /!< bit: 31 Negative condition code flag /
386	} b; /!< Structure used for bit access /
387	uint32_t w; /!< Type used for word access /
388	} xPSR_Type;
389
390	/* xPSR Register Definitions */
391	#define xPSR_N_Pos 31U /!< xPSR: N Position /
392	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
393
394	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
395	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
396
397	#define xPSR_C_Pos 29U /!< xPSR: C Position /
398	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
399
400	#define xPSR_V_Pos 28U /!< xPSR: V Position /
401	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
402
403	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
404	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
405
406	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
407	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
408
409	#define xPSR_T_Pos 24U /!< xPSR: T Position /
410	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
411
412	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
413	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
414
415	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
416	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
417
418
419	/**
420	\brief Union type to access the Control Registers (CONTROL).
421	*/
422	typedef union
423	{
424	struct
425	{
426	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
427	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
428	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
429	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
430	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
431	} b; /!< Structure used for bit access /
432	uint32_t w; /!< Type used for word access /
433	} CONTROL_Type;
434
435	/* CONTROL Register Definitions */
436	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
437	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
438
439	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
440	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
441
442	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
443	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
444
445	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
446	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
447
448	/@} end of group CMSIS_CORE /
449
450
451	/**
452	\ingroup CMSIS_core_register
453	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
454	\brief Type definitions for the NVIC Registers
455	@{
456	*/
457
458	/**
459	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
460	*/
461	typedef struct
462	{
463	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
464	uint32_t RESERVED0[16U];
465	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
466	uint32_t RSERVED1[16U];
467	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
468	uint32_t RESERVED2[16U];
469	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
470	uint32_t RESERVED3[16U];
471	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
472	uint32_t RESERVED4[16U];
473	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
474	uint32_t RESERVED5[16U];
475	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
476	uint32_t RESERVED6[580U];
477	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
478	} NVIC_Type;
479
480	/* Software Triggered Interrupt Register Definitions */
481	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
482	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
483
484	/@} end of group CMSIS_NVIC /
485
486
487	/**
488	\ingroup CMSIS_core_register
489	\defgroup CMSIS_SCB System Control Block (SCB)
490	\brief Type definitions for the System Control Block Registers
491	@{
492	*/
493
494	/**
495	\brief Structure type to access the System Control Block (SCB).
496	*/
497	typedef struct
498	{
499	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
500	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
501	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
502	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
503	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
504	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
505	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
506	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
507	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
508	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
509	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
510	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
511	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
512	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
513	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
514	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
515	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
516	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
517	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
518	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
519	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
520	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
521	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
522	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
523	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
524	uint32_t RESERVED3[92U];
525	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
526	uint32_t RESERVED4[15U];
527	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
528	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
529	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
530	uint32_t RESERVED5[1U];
531	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
532	uint32_t RESERVED6[1U];
533	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
534	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
535	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
536	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
537	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
538	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
539	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
540	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
541	uint32_t RESERVED7[6U];
542	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
543	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
544	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
545	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
546	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
547	uint32_t RESERVED8[1U];
548	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
549	} SCB_Type;
550
551	/* SCB CPUID Register Definitions */
552	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
553	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
554
555	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
556	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
557
558	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
559	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
560
561	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
562	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
563
564	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
565	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
566
567	/* SCB Interrupt Control State Register Definitions */
568	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
569	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
570
571	#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /!< SCB ICSR: NMIPENDSET Position, backward compatibility /
572	#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /!< SCB ICSR: NMIPENDSET Mask, backward compatibility /
573
574	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
575	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
576
577	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
578	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
579
580	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
581	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
582
583	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
584	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
585
586	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
587	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
588
589	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
590	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
591
592	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
593	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
594
595	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
596	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
597
598	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
599	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
600
601	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
602	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
603
604	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
605	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
606
607	/* SCB Vector Table Offset Register Definitions */
608	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
609	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
610
611	/* SCB Application Interrupt and Reset Control Register Definitions */
612	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
613	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
614
615	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
616	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
617
618	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
619	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
620
621	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
622	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
623
624	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
625	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
626
627	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
628	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
629
630	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
631	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
632
633	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
634	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
635
636	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
637	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
638
639	/* SCB System Control Register Definitions */
640	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
641	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
642
643	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
644	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
645
646	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
647	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
648
649	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
650	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
651
652	/* SCB Configuration Control Register Definitions */
653	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
654	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
655
656	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
657	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
658
659	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
660	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
661
662	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
663	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
664
665	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
666	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
667
668	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
669	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
670
671	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
672	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
673
674	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
675	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
676
677	/* SCB System Handler Control and State Register Definitions */
678	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
679	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
680
681	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
682	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
683
684	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
685	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
686
687	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
688	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
689
690	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
691	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
692
693	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
694	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
695
696	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
697	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
698
699	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
700	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
701
702	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
703	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
704
705	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
706	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
707
708	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
709	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
710
711	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
712	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
713
714	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
715	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
716
717	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
718	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
719
720	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
721	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
722
723	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
724	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
725
726	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
727	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
728
729	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
730	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
731
732	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
733	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
734
735	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
736	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
737
738	/* SCB Configurable Fault Status Register Definitions */
739	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
740	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
741
742	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
743	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
744
745	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
746	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
747
748	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
749	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
750	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
751
752	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
753	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
754
755	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
756	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
757
758	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
759	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
760
761	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
762	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
763
764	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
765	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
766
767	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
768	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
769	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
770
771	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
772	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
773
774	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
775	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
776
777	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
778	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
779
780	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
781	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
782
783	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
784	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
785
786	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
787	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
788
789	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
790	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
791	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
792
793	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
794	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
795
796	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
797	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
798
799	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
800	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
801
802	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
803	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
804
805	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
806	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
807
808	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
809	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
810
811	/* SCB Hard Fault Status Register Definitions */
812	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
813	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
814
815	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
816	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
817
818	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
819	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
820
821	/* SCB Debug Fault Status Register Definitions */
822	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
823	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
824
825	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
826	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
827
828	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
829	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
830
831	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
832	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
833
834	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
835	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
836
837	/* SCB Non-Secure Access Control Register Definitions */
838	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
839	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
840
841	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
842	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
843
844	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
845	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
846
847	/* SCB Cache Level ID Register Definitions */
848	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
849	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
850
851	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
852	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
853
854	/* SCB Cache Type Register Definitions */
855	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
856	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
857
858	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
859	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
860
861	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
862	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
863
864	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
865	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
866
867	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
868	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
869
870	/* SCB Cache Size ID Register Definitions */
871	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
872	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
873
874	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
875	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
876
877	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
878	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
879
880	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
881	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
882
883	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
884	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
885
886	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
887	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
888
889	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
890	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
891
892	/* SCB Cache Size Selection Register Definitions */
893	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
894	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
895
896	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
897	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
898
899	/* SCB Software Triggered Interrupt Register Definitions */
900	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
901	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
902
903	/* SCB D-Cache Invalidate by Set-way Register Definitions */
904	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
905	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
906
907	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
908	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
909
910	/* SCB D-Cache Clean by Set-way Register Definitions */
911	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
912	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
913
914	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
915	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
916
917	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
918	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
919	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
920
921	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
922	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
923
924	/* Instruction Tightly-Coupled Memory Control Register Definitions */
925	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
926	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
927
928	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
929	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
930
931	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
932	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
933
934	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
935	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
936
937	/* Data Tightly-Coupled Memory Control Register Definitions */
938	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
939	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
940
941	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
942	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
943
944	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
945	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
946
947	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
948	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
949
950	/* AHBP Control Register Definitions */
951	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
952	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
953
954	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
955	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
956
957	/* L1 Cache Control Register Definitions */
958	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
959	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
960
961	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
962	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
963
964	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
965	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
966
967	/* AHBS Control Register Definitions */
968	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
969	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
970
971	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
972	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
973
974	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
975	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
976
977	/* Auxiliary Bus Fault Status Register Definitions */
978	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
979	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
980
981	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
982	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
983
984	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
985	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
986
987	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
988	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
989
990	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
991	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
992
993	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
994	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
995
996	/@} end of group CMSIS_SCB /
997
998
999	/**
1000	\ingroup CMSIS_core_register
1001	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
1002	\brief Type definitions for the System Control and ID Register not in the SCB
1003	@{
1004	*/
1005
1006	/**
1007	\brief Structure type to access the System Control and ID Register not in the SCB.
1008	*/
1009	typedef struct
1010	{
1011	uint32_t RESERVED0[1U];
1012	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
1013	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
1014	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
1015	} SCnSCB_Type;
1016
1017	/* Interrupt Controller Type Register Definitions */
1018	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
1019	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
1020
1021	/@} end of group CMSIS_SCnotSCB /
1022
1023
1024	/**
1025	\ingroup CMSIS_core_register
1026	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
1027	\brief Type definitions for the System Timer Registers.
1028	@{
1029	*/
1030
1031	/**
1032	\brief Structure type to access the System Timer (SysTick).
1033	*/
1034	typedef struct
1035	{
1036	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
1037	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
1038	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
1039	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
1040	} SysTick_Type;
1041
1042	/* SysTick Control / Status Register Definitions */
1043	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
1044	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
1045
1046	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
1047	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
1048
1049	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
1050	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
1051
1052	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
1053	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
1054
1055	/* SysTick Reload Register Definitions */
1056	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
1057	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
1058
1059	/* SysTick Current Register Definitions */
1060	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
1061	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
1062
1063	/* SysTick Calibration Register Definitions */
1064	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
1065	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
1066
1067	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
1068	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
1069
1070	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
1071	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
1072
1073	/@} end of group CMSIS_SysTick /
1074
1075
1076	/**
1077	\ingroup CMSIS_core_register
1078	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1079	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1080	@{
1081	*/
1082
1083	/**
1084	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1085	*/
1086	typedef struct
1087	{
1088	__OM union
1089	{
1090	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
1091	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
1092	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
1093	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
1094	uint32_t RESERVED0[864U];
1095	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
1096	uint32_t RESERVED1[15U];
1097	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
1098	uint32_t RESERVED2[15U];
1099	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
1100	uint32_t RESERVED3[29U];
1101	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
1102	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
1103	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
1104	uint32_t RESERVED4[43U];
1105	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
1106	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
1107	uint32_t RESERVED5[1U];
1108	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
1109	uint32_t RESERVED6[4U];
1110	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
1111	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
1112	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
1113	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
1114	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
1115	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
1116	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
1117	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
1118	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
1119	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
1120	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
1121	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
1122	} ITM_Type;
1123
1124	/* ITM Stimulus Port Register Definitions */
1125	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
1126	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
1127
1128	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
1129	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
1130
1131	/* ITM Trace Privilege Register Definitions */
1132	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
1133	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
1134
1135	/* ITM Trace Control Register Definitions */
1136	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
1137	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
1138
1139	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
1140	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
1141
1142	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
1143	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
1144
1145	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
1146	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
1147
1148	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
1149	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
1150
1151	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
1152	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
1153
1154	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
1155	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
1156
1157	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
1158	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
1159
1160	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
1161	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
1162
1163	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
1164	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
1165
1166	/* ITM Integration Write Register Definitions */
1167	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
1168	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
1169
1170	/* ITM Integration Read Register Definitions */
1171	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
1172	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
1173
1174	/* ITM Integration Mode Control Register Definitions */
1175	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
1176	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
1177
1178	/* ITM Lock Status Register Definitions */
1179	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
1180	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
1181
1182	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
1183	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
1184
1185	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
1186	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
1187
1188	/@}/ /* end of group CMSIS_ITM */
1189
1190
1191	/**
1192	\ingroup CMSIS_core_register
1193	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1194	\brief Type definitions for the Data Watchpoint and Trace (DWT)
1195	@{
1196	*/
1197
1198	/**
1199	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1200	*/
1201	typedef struct
1202	{
1203	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
1204	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
1205	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
1206	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
1207	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
1208	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
1209	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
1210	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
1211	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
1212	uint32_t RESERVED1[1U];
1213	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
1214	uint32_t RESERVED2[1U];
1215	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
1216	uint32_t RESERVED3[1U];
1217	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
1218	uint32_t RESERVED4[1U];
1219	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
1220	uint32_t RESERVED5[1U];
1221	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
1222	uint32_t RESERVED6[1U];
1223	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
1224	uint32_t RESERVED7[1U];
1225	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
1226	uint32_t RESERVED8[1U];
1227	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
1228	uint32_t RESERVED9[1U];
1229	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
1230	uint32_t RESERVED10[1U];
1231	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
1232	uint32_t RESERVED11[1U];
1233	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
1234	uint32_t RESERVED12[1U];
1235	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
1236	uint32_t RESERVED13[1U];
1237	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
1238	uint32_t RESERVED14[1U];
1239	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
1240	uint32_t RESERVED15[1U];
1241	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
1242	uint32_t RESERVED16[1U];
1243	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
1244	uint32_t RESERVED17[1U];
1245	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
1246	uint32_t RESERVED18[1U];
1247	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
1248	uint32_t RESERVED19[1U];
1249	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
1250	uint32_t RESERVED20[1U];
1251	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
1252	uint32_t RESERVED21[1U];
1253	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
1254	uint32_t RESERVED22[1U];
1255	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
1256	uint32_t RESERVED23[1U];
1257	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
1258	uint32_t RESERVED24[1U];
1259	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
1260	uint32_t RESERVED25[1U];
1261	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
1262	uint32_t RESERVED26[1U];
1263	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
1264	uint32_t RESERVED27[1U];
1265	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
1266	uint32_t RESERVED28[1U];
1267	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
1268	uint32_t RESERVED29[1U];
1269	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
1270	uint32_t RESERVED30[1U];
1271	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
1272	uint32_t RESERVED31[1U];
1273	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
1274	uint32_t RESERVED32[934U];
1275	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
1276	uint32_t RESERVED33[1U];
1277	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
1278	} DWT_Type;
1279
1280	/* DWT Control Register Definitions */
1281	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
1282	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
1283
1284	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
1285	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
1286
1287	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
1288	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
1289
1290	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
1291	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
1292
1293	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
1294	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
1295
1296	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
1297	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
1298
1299	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
1300	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
1301
1302	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
1303	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
1304
1305	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
1306	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
1307
1308	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
1309	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
1310
1311	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
1312	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
1313
1314	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
1315	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
1316
1317	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
1318	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
1319
1320	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
1321	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
1322
1323	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
1324	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
1325
1326	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
1327	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
1328
1329	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
1330	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
1331
1332	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
1333	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
1334
1335	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
1336	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
1337
1338	/* DWT CPI Count Register Definitions */
1339	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
1340	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
1341
1342	/* DWT Exception Overhead Count Register Definitions */
1343	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
1344	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
1345
1346	/* DWT Sleep Count Register Definitions */
1347	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
1348	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
1349
1350	/* DWT LSU Count Register Definitions */
1351	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
1352	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
1353
1354	/* DWT Folded-instruction Count Register Definitions */
1355	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
1356	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
1357
1358	/* DWT Comparator Function Register Definitions */
1359	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
1360	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
1361
1362	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
1363	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
1364
1365	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
1366	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
1367
1368	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
1369	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
1370
1371	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
1372	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
1373
1374	/@}/ /* end of group CMSIS_DWT */
1375
1376
1377	/**
1378	\ingroup CMSIS_core_register
1379	\defgroup CMSIS_TPI Trace Port Interface (TPI)
1380	\brief Type definitions for the Trace Port Interface (TPI)
1381	@{
1382	*/
1383
1384	/**
1385	\brief Structure type to access the Trace Port Interface Register (TPI).
1386	*/
1387	typedef struct
1388	{
1389	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register /
1390	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register /
1391	uint32_t RESERVED0[2U];
1392	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
1393	uint32_t RESERVED1[55U];
1394	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
1395	uint32_t RESERVED2[131U];
1396	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
1397	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
1398	__IOM uint32_t PSCR; /!< Offset: 0x308 (R/W) Periodic Synchronization Control Register /
1399	uint32_t RESERVED3[809U];
1400	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) Software Lock Access Register /
1401	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) Software Lock Status Register /
1402	uint32_t RESERVED4[4U];
1403	__IM uint32_t TYPE; /!< Offset: 0xFC8 (R/ ) Device Identifier Register /
1404	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) Device Type Register /
1405	} TPI_Type;
1406
1407	/* TPI Asynchronous Clock Prescaler Register Definitions */
1408	#define TPI_ACPR_SWOSCALER_Pos 0U /!< TPI ACPR: SWOSCALER Position /
1409	#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/) /!< TPI ACPR: SWOSCALER Mask /
1410
1411	/* TPI Selected Pin Protocol Register Definitions */
1412	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
1413	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
1414
1415	/* TPI Formatter and Flush Status Register Definitions */
1416	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
1417	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
1418
1419	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
1420	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
1421
1422	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
1423	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
1424
1425	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
1426	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
1427
1428	/* TPI Formatter and Flush Control Register Definitions */
1429	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
1430	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
1431
1432	#define TPI_FFCR_FOnMan_Pos 6U /!< TPI FFCR: FOnMan Position /
1433	#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /!< TPI FFCR: FOnMan Mask /
1434
1435	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
1436	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
1437
1438	/* TPI Periodic Synchronization Control Register Definitions */
1439	#define TPI_PSCR_PSCount_Pos 0U /!< TPI PSCR: PSCount Position /
1440	#define TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/) /!< TPI PSCR: TPSCount Mask /
1441
1442	/* TPI Software Lock Status Register Definitions */
1443	#define TPI_LSR_nTT_Pos 1U /!< TPI LSR: Not thirty-two bit. Position /
1444	#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /!< TPI LSR: Not thirty-two bit. Mask /
1445
1446	#define TPI_LSR_SLK_Pos 1U /!< TPI LSR: Software Lock status Position /
1447	#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /!< TPI LSR: Software Lock status Mask /
1448
1449	#define TPI_LSR_SLI_Pos 0U /!< TPI LSR: Software Lock implemented Position /
1450	#define TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/) /!< TPI LSR: Software Lock implemented Mask /
1451
1452	/* TPI DEVID Register Definitions */
1453	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
1454	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
1455
1456	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
1457	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
1458
1459	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
1460	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
1461
1462	#define TPI_DEVID_FIFOSZ_Pos 6U /!< TPI DEVID: FIFO depth Position /
1463	#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /!< TPI DEVID: FIFO depth Mask /
1464
1465	/* TPI DEVTYPE Register Definitions */
1466	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
1467	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
1468
1469	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
1470	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
1471
1472	/@}/ /* end of group CMSIS_TPI */
1473
1474
1475	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1476	/**
1477	\ingroup CMSIS_core_register
1478	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
1479	\brief Type definitions for the Memory Protection Unit (MPU)
1480	@{
1481	*/
1482
1483	/**
1484	\brief Structure type to access the Memory Protection Unit (MPU).
1485	*/
1486	typedef struct
1487	{
1488	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
1489	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
1490	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
1491	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
1492	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
1493	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
1494	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
1495	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
1496	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
1497	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
1498	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
1499	uint32_t RESERVED0[1];
1500	union {
1501	__IOM uint32_t MAIR[2];
1502	struct {
1503	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
1504	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
1505	};
1506	};
1507	} MPU_Type;
1508
1509	#define MPU_TYPE_RALIASES 4U
1510
1511	/* MPU Type Register Definitions */
1512	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
1513	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
1514
1515	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
1516	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
1517
1518	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
1519	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
1520
1521	/* MPU Control Register Definitions */
1522	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
1523	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
1524
1525	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
1526	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
1527
1528	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
1529	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
1530
1531	/* MPU Region Number Register Definitions */
1532	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
1533	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
1534
1535	/* MPU Region Base Address Register Definitions */
1536	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
1537	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
1538
1539	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
1540	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
1541
1542	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
1543	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
1544
1545	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
1546	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
1547
1548	/* MPU Region Limit Address Register Definitions */
1549	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
1550	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
1551
1552	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
1553	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
1554
1555	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
1556	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
1557
1558	/* MPU Memory Attribute Indirection Register 0 Definitions */
1559	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
1560	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
1561
1562	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
1563	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
1564
1565	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
1566	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
1567
1568	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
1569	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
1570
1571	/* MPU Memory Attribute Indirection Register 1 Definitions */
1572	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
1573	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
1574
1575	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
1576	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
1577
1578	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
1579	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
1580
1581	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
1582	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
1583
1584	/@} end of group CMSIS_MPU /
1585	#endif
1586
1587
1588	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1589	/**
1590	\ingroup CMSIS_core_register
1591	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
1592	\brief Type definitions for the Security Attribution Unit (SAU)
1593	@{
1594	*/
1595
1596	/**
1597	\brief Structure type to access the Security Attribution Unit (SAU).
1598	*/
1599	typedef struct
1600	{
1601	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
1602	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
1603	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1604	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
1605	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
1606	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
1607	#else
1608	uint32_t RESERVED0[3];
1609	#endif
1610	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
1611	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
1612	} SAU_Type;
1613
1614	/* SAU Control Register Definitions */
1615	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
1616	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
1617
1618	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
1619	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
1620
1621	/* SAU Type Register Definitions */
1622	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
1623	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
1624
1625	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1626	/* SAU Region Number Register Definitions */
1627	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
1628	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
1629
1630	/* SAU Region Base Address Register Definitions */
1631	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
1632	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
1633
1634	/* SAU Region Limit Address Register Definitions */
1635	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
1636	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
1637
1638	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
1639	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
1640
1641	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
1642	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
1643
1644	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1645
1646	/* Secure Fault Status Register Definitions */
1647	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
1648	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
1649
1650	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
1651	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
1652
1653	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
1654	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
1655
1656	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
1657	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
1658
1659	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
1660	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
1661
1662	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
1663	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
1664
1665	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
1666	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
1667
1668	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
1669	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
1670
1671	/@} end of group CMSIS_SAU /
1672	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1673
1674
1675	/**
1676	\ingroup CMSIS_core_register
1677	\defgroup CMSIS_FPU Floating Point Unit (FPU)
1678	\brief Type definitions for the Floating Point Unit (FPU)
1679	@{
1680	*/
1681
1682	/**
1683	\brief Structure type to access the Floating Point Unit (FPU).
1684	*/
1685	typedef struct
1686	{
1687	uint32_t RESERVED0[1U];
1688	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
1689	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
1690	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
1691	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
1692	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
1693	} FPU_Type;
1694
1695	/* Floating-Point Context Control Register Definitions */
1696	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
1697	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
1698
1699	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
1700	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
1701
1702	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
1703	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
1704
1705	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
1706	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
1707
1708	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
1709	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
1710
1711	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
1712	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
1713
1714	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
1715	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
1716
1717	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
1718	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
1719
1720	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
1721	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
1722
1723	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
1724	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
1725
1726	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
1727	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
1728
1729	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
1730	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
1731
1732	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
1733	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
1734
1735	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
1736	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
1737
1738	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
1739	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
1740
1741	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
1742	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
1743
1744	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
1745	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
1746
1747	/* Floating-Point Context Address Register Definitions */
1748	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
1749	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
1750
1751	/* Floating-Point Default Status Control Register Definitions */
1752	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
1753	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
1754
1755	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
1756	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
1757
1758	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
1759	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
1760
1761	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
1762	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
1763
1764	/* Media and FP Feature Register 0 Definitions */
1765	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
1766	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
1767
1768	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
1769	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
1770
1771	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
1772	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
1773
1774	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
1775	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
1776
1777	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
1778	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
1779
1780	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
1781	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
1782
1783	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
1784	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
1785
1786	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
1787	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
1788
1789	/* Media and FP Feature Register 1 Definitions */
1790	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
1791	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
1792
1793	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
1794	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
1795
1796	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
1797	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
1798
1799	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
1800	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
1801
1802	/@} end of group CMSIS_FPU /
1803
1804
1805	/**
1806	\ingroup CMSIS_core_register
1807	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1808	\brief Type definitions for the Core Debug Registers
1809	@{
1810	*/
1811
1812	/**
1813	\brief Structure type to access the Core Debug Register (CoreDebug).
1814	*/
1815	typedef struct
1816	{
1817	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
1818	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
1819	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
1820	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
1821	uint32_t RESERVED4[1U];
1822	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
1823	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
1824	} CoreDebug_Type;
1825
1826	/* Debug Halting Control and Status Register Definitions */
1827	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
1828	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
1829
1830	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
1831	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
1832
1833	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
1834	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
1835
1836	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
1837	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
1838
1839	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
1840	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
1841
1842	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
1843	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
1844
1845	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
1846	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
1847
1848	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
1849	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
1850
1851	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
1852	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
1853
1854	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
1855	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
1856
1857	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
1858	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
1859
1860	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
1861	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
1862
1863	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
1864	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
1865
1866	/* Debug Core Register Selector Register Definitions */
1867	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
1868	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
1869
1870	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
1871	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
1872
1873	/* Debug Exception and Monitor Control Register Definitions */
1874	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
1875	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
1876
1877	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
1878	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
1879
1880	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
1881	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
1882
1883	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
1884	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
1885
1886	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
1887	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
1888
1889	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
1890	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
1891
1892	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
1893	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
1894
1895	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
1896	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
1897
1898	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
1899	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
1900
1901	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
1902	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
1903
1904	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
1905	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
1906
1907	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
1908	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
1909
1910	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
1911	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
1912
1913	/* Debug Authentication Control Register Definitions */
1914	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
1915	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
1916
1917	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
1918	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
1919
1920	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
1921	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
1922
1923	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
1924	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
1925
1926	/* Debug Security Control and Status Register Definitions */
1927	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
1928	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
1929
1930	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
1931	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
1932
1933	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
1934	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
1935
1936	/@} end of group CMSIS_CoreDebug /
1937
1938
1939	/**
1940	\ingroup CMSIS_core_register
1941	\defgroup CMSIS_core_bitfield Core register bit field macros
1942	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1943	@{
1944	*/
1945
1946	/**
1947	\brief Mask and shift a bit field value for use in a register bit range.
1948	\param[in] field Name of the register bit field.
1949	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1950	\return Masked and shifted value.
1951	*/
1952	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1953
1954	/**
1955	\brief Mask and shift a register value to extract a bit filed value.
1956	\param[in] field Name of the register bit field.
1957	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1958	\return Masked and shifted bit field value.
1959	*/
1960	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1961
1962	/@} end of group CMSIS_core_bitfield /
1963
1964
1965	/**
1966	\ingroup CMSIS_core_register
1967	\defgroup CMSIS_core_base Core Definitions
1968	\brief Definitions for base addresses, unions, and structures.
1969	@{
1970	*/
1971
1972	/* Memory mapping of Core Hardware */
1973	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
1974	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
1975	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
1976	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
1977	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
1978	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
1979	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
1980	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
1981
1982	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
1983	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
1984	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
1985	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
1986	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
1987	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
1988	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
1989	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
1990
1991	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1992	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
1993	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
1994	#endif
1995
1996	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1997	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
1998	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
1999	#endif
2000
2001	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
2002	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
2003
2004	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2005	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
2006	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
2007	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
2008	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
2009	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
2010
2011	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
2012	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
2013	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
2014	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
2015	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
2016
2017	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2018	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
2019	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
2020	#endif
2021
2022	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
2023	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
2024
2025	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2026	/@} /
2027
2028
2029
2030	/*******************************************************************************
2031	* Hardware Abstraction Layer
2032	Core Function Interface contains:
2033	- Core NVIC Functions
2034	- Core SysTick Functions
2035	- Core Debug Functions
2036	- Core Register Access Functions
2037	******************************************************************************/
2038	/**
2039	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
2040	*/
2041
2042
2043
2044	/* ########################## NVIC functions #################################### */
2045	/**
2046	\ingroup CMSIS_Core_FunctionInterface
2047	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
2048	\brief Functions that manage interrupts and exceptions via the NVIC.
2049	@{
2050	*/
2051
2052	#ifdef CMSIS_NVIC_VIRTUAL
2053	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2054	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2055	#endif
2056	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2057	#else
2058	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2059	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2060	#define NVIC_EnableIRQ __NVIC_EnableIRQ
2061	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2062	#define NVIC_DisableIRQ __NVIC_DisableIRQ
2063	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2064	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2065	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2066	#define NVIC_GetActive __NVIC_GetActive
2067	#define NVIC_SetPriority __NVIC_SetPriority
2068	#define NVIC_GetPriority __NVIC_GetPriority
2069	#define NVIC_SystemReset __NVIC_SystemReset
2070	#endif /* CMSIS_NVIC_VIRTUAL */
2071
2072	#ifdef CMSIS_VECTAB_VIRTUAL
2073	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2074	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2075	#endif
2076	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2077	#else
2078	#define NVIC_SetVector __NVIC_SetVector
2079	#define NVIC_GetVector __NVIC_GetVector
2080	#endif /* (CMSIS_VECTAB_VIRTUAL) */
2081
2082	#define NVIC_USER_IRQ_OFFSET 16
2083
2084
2085	/* Special LR values for Secure/Non-Secure call handling and exception handling */
2086
2087	/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2088	#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2089
2090	/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2091	#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2092	#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2093	#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2094	#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2095	#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2096	#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
2097	#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2098
2099	/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2101	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2102	#else
2103	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2104	#endif
2105
2106
2107	/**
2108	\brief Set Priority Grouping
2109	\details Sets the priority grouping field using the required unlock sequence.
2110	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2111	Only values from 0..7 are used.
2112	In case of a conflict between priority grouping and available
2113	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2114	\param [in] PriorityGroup Priority grouping field.
2115	*/
2116	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2117	{
2118	uint32_t reg_value;
2119	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2120
2121	reg_value = SCB->AIRCR; /* read old register configuration */
2122	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2123	reg_value = (reg_value \|
2124	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
2125	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2126	SCB->AIRCR = reg_value;
2127	}
2128
2129
2130	/**
2131	\brief Get Priority Grouping
2132	\details Reads the priority grouping field from the NVIC Interrupt Controller.
2133	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2134	*/
2135	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2136	{
2137	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2138	}
2139
2140
2141	/**
2142	\brief Enable Interrupt
2143	\details Enables a device specific interrupt in the NVIC interrupt controller.
2144	\param [in] IRQn Device specific interrupt number.
2145	\note IRQn must not be negative.
2146	*/
2147	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2148	{
2149	if ((int32_t)(IRQn) >= 0)
2150	{
2151	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2152	}
2153	}
2154
2155
2156	/**
2157	\brief Get Interrupt Enable status
2158	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2159	\param [in] IRQn Device specific interrupt number.
2160	\return 0 Interrupt is not enabled.
2161	\return 1 Interrupt is enabled.
2162	\note IRQn must not be negative.
2163	*/
2164	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2165	{
2166	if ((int32_t)(IRQn) >= 0)
2167	{
2168	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2169	}
2170	else
2171	{
2172	return(0U);
2173	}
2174	}
2175
2176
2177	/**
2178	\brief Disable Interrupt
2179	\details Disables a device specific interrupt in the NVIC interrupt controller.
2180	\param [in] IRQn Device specific interrupt number.
2181	\note IRQn must not be negative.
2182	*/
2183	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2184	{
2185	if ((int32_t)(IRQn) >= 0)
2186	{
2187	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2188	__DSB();
2189	__ISB();
2190	}
2191	}
2192
2193
2194	/**
2195	\brief Get Pending Interrupt
2196	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2197	\param [in] IRQn Device specific interrupt number.
2198	\return 0 Interrupt status is not pending.
2199	\return 1 Interrupt status is pending.
2200	\note IRQn must not be negative.
2201	*/
2202	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2203	{
2204	if ((int32_t)(IRQn) >= 0)
2205	{
2206	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2207	}
2208	else
2209	{
2210	return(0U);
2211	}
2212	}
2213
2214
2215	/**
2216	\brief Set Pending Interrupt
2217	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2218	\param [in] IRQn Device specific interrupt number.
2219	\note IRQn must not be negative.
2220	*/
2221	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2222	{
2223	if ((int32_t)(IRQn) >= 0)
2224	{
2225	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2226	}
2227	}
2228
2229
2230	/**
2231	\brief Clear Pending Interrupt
2232	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2233	\param [in] IRQn Device specific interrupt number.
2234	\note IRQn must not be negative.
2235	*/
2236	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2237	{
2238	if ((int32_t)(IRQn) >= 0)
2239	{
2240	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2241	}
2242	}
2243
2244
2245	/**
2246	\brief Get Active Interrupt
2247	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2248	\param [in] IRQn Device specific interrupt number.
2249	\return 0 Interrupt status is not active.
2250	\return 1 Interrupt status is active.
2251	\note IRQn must not be negative.
2252	*/
2253	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2254	{
2255	if ((int32_t)(IRQn) >= 0)
2256	{
2257	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2258	}
2259	else
2260	{
2261	return(0U);
2262	}
2263	}
2264
2265
2266	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2267	/**
2268	\brief Get Interrupt Target State
2269	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2270	\param [in] IRQn Device specific interrupt number.
2271	\return 0 if interrupt is assigned to Secure
2272	\return 1 if interrupt is assigned to Non Secure
2273	\note IRQn must not be negative.
2274	*/
2275	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2276	{
2277	if ((int32_t)(IRQn) >= 0)
2278	{
2279	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2280	}
2281	else
2282	{
2283	return(0U);
2284	}
2285	}
2286
2287
2288	/**
2289	\brief Set Interrupt Target State
2290	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2291	\param [in] IRQn Device specific interrupt number.
2292	\return 0 if interrupt is assigned to Secure
2293	1 if interrupt is assigned to Non Secure
2294	\note IRQn must not be negative.
2295	*/
2296	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2297	{
2298	if ((int32_t)(IRQn) >= 0)
2299	{
2300	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2301	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2302	}
2303	else
2304	{
2305	return(0U);
2306	}
2307	}
2308
2309
2310	/**
2311	\brief Clear Interrupt Target State
2312	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2313	\param [in] IRQn Device specific interrupt number.
2314	\return 0 if interrupt is assigned to Secure
2315	1 if interrupt is assigned to Non Secure
2316	\note IRQn must not be negative.
2317	*/
2318	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2319	{
2320	if ((int32_t)(IRQn) >= 0)
2321	{
2322	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2323	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2324	}
2325	else
2326	{
2327	return(0U);
2328	}
2329	}
2330	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2331
2332
2333	/**
2334	\brief Set Interrupt Priority
2335	\details Sets the priority of a device specific interrupt or a processor exception.
2336	The interrupt number can be positive to specify a device specific interrupt,
2337	or negative to specify a processor exception.
2338	\param [in] IRQn Interrupt number.
2339	\param [in] priority Priority to set.
2340	\note The priority cannot be set for every processor exception.
2341	*/
2342	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2343	{
2344	if ((int32_t)(IRQn) >= 0)
2345	{
2346	NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2347	}
2348	else
2349	{
2350	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2351	}
2352	}
2353
2354
2355	/**
2356	\brief Get Interrupt Priority
2357	\details Reads the priority of a device specific interrupt or a processor exception.
2358	The interrupt number can be positive to specify a device specific interrupt,
2359	or negative to specify a processor exception.
2360	\param [in] IRQn Interrupt number.
2361	\return Interrupt Priority.
2362	Value is aligned automatically to the implemented priority bits of the microcontroller.
2363	*/
2364	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2365	{
2366
2367	if ((int32_t)(IRQn) >= 0)
2368	{
2369	return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2370	}
2371	else
2372	{
2373	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2374	}
2375	}
2376
2377
2378	/**
2379	\brief Encode Priority
2380	\details Encodes the priority for an interrupt with the given priority group,
2381	preemptive priority value, and subpriority value.
2382	In case of a conflict between priority grouping and available
2383	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2384	\param [in] PriorityGroup Used priority group.
2385	\param [in] PreemptPriority Preemptive priority value (starting from 0).
2386	\param [in] SubPriority Subpriority value (starting from 0).
2387	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2388	*/
2389	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2390	{
2391	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2392	uint32_t PreemptPriorityBits;
2393	uint32_t SubPriorityBits;
2394
2395	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2396	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2397
2398	return (
2399	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
2400	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2401	);
2402	}
2403
2404
2405	/**
2406	\brief Decode Priority
2407	\details Decodes an interrupt priority value with a given priority group to
2408	preemptive priority value and subpriority value.
2409	In case of a conflict between priority grouping and available
2410	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2411	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2412	\param [in] PriorityGroup Used priority group.
2413	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
2414	\param [out] pSubPriority Subpriority value (starting from 0).
2415	*/
2416	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2417	{
2418	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2419	uint32_t PreemptPriorityBits;
2420	uint32_t SubPriorityBits;
2421
2422	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2423	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2424
2425	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2426	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2427	}
2428
2429
2430	/**
2431	\brief Set Interrupt Vector
2432	\details Sets an interrupt vector in SRAM based interrupt vector table.
2433	The interrupt number can be positive to specify a device specific interrupt,
2434	or negative to specify a processor exception.
2435	VTOR must been relocated to SRAM before.
2436	\param [in] IRQn Interrupt number
2437	\param [in] vector Address of interrupt handler function
2438	*/
2439	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2440	{
2441	uint32_t vectors = (uint32_t )SCB->VTOR;
2442	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2443	}
2444
2445
2446	/**
2447	\brief Get Interrupt Vector
2448	\details Reads an interrupt vector from interrupt vector table.
2449	The interrupt number can be positive to specify a device specific interrupt,
2450	or negative to specify a processor exception.
2451	\param [in] IRQn Interrupt number.
2452	\return Address of interrupt handler function
2453	*/
2454	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2455	{
2456	uint32_t vectors = (uint32_t )SCB->VTOR;
2457	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2458	}
2459
2460
2461	/**
2462	\brief System Reset
2463	\details Initiates a system reset request to reset the MCU.
2464	*/
2465	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2466	{
2467	__DSB(); /* Ensure all outstanding memory accesses included
2468	buffered write are completed before reset */
2469	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
2470	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
2471	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2472	__DSB(); /* Ensure completion of memory access */
2473
2474	for(;;) /* wait until reset */
2475	{
2476	__NOP();
2477	}
2478	}
2479
2480	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2481	/**
2482	\brief Set Priority Grouping (non-secure)
2483	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2484	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2485	Only values from 0..7 are used.
2486	In case of a conflict between priority grouping and available
2487	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2488	\param [in] PriorityGroup Priority grouping field.
2489	*/
2490	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2491	{
2492	uint32_t reg_value;
2493	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2494
2495	reg_value = SCB_NS->AIRCR; /* read old register configuration */
2496	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2497	reg_value = (reg_value \|
2498	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
2499	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2500	SCB_NS->AIRCR = reg_value;
2501	}
2502
2503
2504	/**
2505	\brief Get Priority Grouping (non-secure)
2506	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
2507	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2508	*/
2509	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2510	{
2511	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2512	}
2513
2514
2515	/**
2516	\brief Enable Interrupt (non-secure)
2517	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2518	\param [in] IRQn Device specific interrupt number.
2519	\note IRQn must not be negative.
2520	*/
2521	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2522	{
2523	if ((int32_t)(IRQn) >= 0)
2524	{
2525	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2526	}
2527	}
2528
2529
2530	/**
2531	\brief Get Interrupt Enable status (non-secure)
2532	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2533	\param [in] IRQn Device specific interrupt number.
2534	\return 0 Interrupt is not enabled.
2535	\return 1 Interrupt is enabled.
2536	\note IRQn must not be negative.
2537	*/
2538	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2539	{
2540	if ((int32_t)(IRQn) >= 0)
2541	{
2542	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2543	}
2544	else
2545	{
2546	return(0U);
2547	}
2548	}
2549
2550
2551	/**
2552	\brief Disable Interrupt (non-secure)
2553	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2554	\param [in] IRQn Device specific interrupt number.
2555	\note IRQn must not be negative.
2556	*/
2557	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2558	{
2559	if ((int32_t)(IRQn) >= 0)
2560	{
2561	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2562	}
2563	}
2564
2565
2566	/**
2567	\brief Get Pending Interrupt (non-secure)
2568	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2569	\param [in] IRQn Device specific interrupt number.
2570	\return 0 Interrupt status is not pending.
2571	\return 1 Interrupt status is pending.
2572	\note IRQn must not be negative.
2573	*/
2574	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2575	{
2576	if ((int32_t)(IRQn) >= 0)
2577	{
2578	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2579	}
2580	else
2581	{
2582	return(0U);
2583	}
2584	}
2585
2586
2587	/**
2588	\brief Set Pending Interrupt (non-secure)
2589	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2590	\param [in] IRQn Device specific interrupt number.
2591	\note IRQn must not be negative.
2592	*/
2593	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2594	{
2595	if ((int32_t)(IRQn) >= 0)
2596	{
2597	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2598	}
2599	}
2600
2601
2602	/**
2603	\brief Clear Pending Interrupt (non-secure)
2604	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2605	\param [in] IRQn Device specific interrupt number.
2606	\note IRQn must not be negative.
2607	*/
2608	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2609	{
2610	if ((int32_t)(IRQn) >= 0)
2611	{
2612	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2613	}
2614	}
2615
2616
2617	/**
2618	\brief Get Active Interrupt (non-secure)
2619	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2620	\param [in] IRQn Device specific interrupt number.
2621	\return 0 Interrupt status is not active.
2622	\return 1 Interrupt status is active.
2623	\note IRQn must not be negative.
2624	*/
2625	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2626	{
2627	if ((int32_t)(IRQn) >= 0)
2628	{
2629	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2630	}
2631	else
2632	{
2633	return(0U);
2634	}
2635	}
2636
2637
2638	/**
2639	\brief Set Interrupt Priority (non-secure)
2640	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2641	The interrupt number can be positive to specify a device specific interrupt,
2642	or negative to specify a processor exception.
2643	\param [in] IRQn Interrupt number.
2644	\param [in] priority Priority to set.
2645	\note The priority cannot be set for every non-secure processor exception.
2646	*/
2647	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2648	{
2649	if ((int32_t)(IRQn) >= 0)
2650	{
2651	NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2652	}
2653	else
2654	{
2655	SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2656	}
2657	}
2658
2659
2660	/**
2661	\brief Get Interrupt Priority (non-secure)
2662	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2663	The interrupt number can be positive to specify a device specific interrupt,
2664	or negative to specify a processor exception.
2665	\param [in] IRQn Interrupt number.
2666	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2667	*/
2668	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2669	{
2670
2671	if ((int32_t)(IRQn) >= 0)
2672	{
2673	return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2674	}
2675	else
2676	{
2677	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2678	}
2679	}
2680	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2681
2682	/@} end of CMSIS_Core_NVICFunctions /
2683
2684	/* ########################## MPU functions #################################### */
2685
2686	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2687
2688	#include "mpu_armv8.h"
2689
2690	#endif
2691
2692	/* ########################## FPU functions #################################### */
2693	/**
2694	\ingroup CMSIS_Core_FunctionInterface
2695	\defgroup CMSIS_Core_FpuFunctions FPU Functions
2696	\brief Function that provides FPU type.
2697	@{
2698	*/
2699
2700	/**
2701	\brief get FPU type
2702	\details returns the FPU type
2703	\returns
2704	- \b 0: No FPU
2705	- \b 1: Single precision FPU
2706	- \b 2: Double + Single precision FPU
2707	*/
2708	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
2709	{
2710	uint32_t mvfr0;
2711
2712	mvfr0 = FPU->MVFR0;
2713	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2714	{
2715	return 2U; /* Double + Single precision FPU */
2716	}
2717	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2718	{
2719	return 1U; /* Single precision FPU */
2720	}
2721	else
2722	{
2723	return 0U; /* No FPU */
2724	}
2725	}
2726
2727
2728	/@} end of CMSIS_Core_FpuFunctions /
2729
2730
2731
2732	/* ########################## SAU functions #################################### */
2733	/**
2734	\ingroup CMSIS_Core_FunctionInterface
2735	\defgroup CMSIS_Core_SAUFunctions SAU Functions
2736	\brief Functions that configure the SAU.
2737	@{
2738	*/
2739
2740	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2741
2742	/**
2743	\brief Enable SAU
2744	\details Enables the Security Attribution Unit (SAU).
2745	*/
2746	__STATIC_INLINE void TZ_SAU_Enable(void)
2747	{
2748	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
2749	}
2750
2751
2752
2753	/**
2754	\brief Disable SAU
2755	\details Disables the Security Attribution Unit (SAU).
2756	*/
2757	__STATIC_INLINE void TZ_SAU_Disable(void)
2758	{
2759	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2760	}
2761
2762	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2763
2764	/@} end of CMSIS_Core_SAUFunctions /
2765
2766
2767
2768
2769	/* ################################## SysTick function ############################################ */
2770	/**
2771	\ingroup CMSIS_Core_FunctionInterface
2772	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2773	\brief Functions that configure the System.
2774	@{
2775	*/
2776
2777	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2778
2779	/**
2780	\brief System Tick Configuration
2781	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2782	Counter is in free running mode to generate periodic interrupts.
2783	\param [in] ticks Number of ticks between two interrupts.
2784	\return 0 Function succeeded.
2785	\return 1 Function failed.
2786	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2787	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2788	must contain a vendor-specific implementation of this function.
2789	*/
2790	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2791	{
2792	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2793	{
2794	return (1UL); /* Reload value impossible */
2795	}
2796
2797	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2798	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2799	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2800	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
2801	SysTick_CTRL_TICKINT_Msk \|
2802	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2803	return (0UL); /* Function successful */
2804	}
2805
2806	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2807	/**
2808	\brief System Tick Configuration (non-secure)
2809	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
2810	Counter is in free running mode to generate periodic interrupts.
2811	\param [in] ticks Number of ticks between two interrupts.
2812	\return 0 Function succeeded.
2813	\return 1 Function failed.
2814	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2815	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
2816	must contain a vendor-specific implementation of this function.
2817
2818	*/
2819	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2820	{
2821	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2822	{
2823	return (1UL); /* Reload value impossible */
2824	}
2825
2826	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2827	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2828	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2829	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
2830	SysTick_CTRL_TICKINT_Msk \|
2831	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2832	return (0UL); /* Function successful */
2833	}
2834	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2835
2836	#endif
2837
2838	/@} end of CMSIS_Core_SysTickFunctions /
2839
2840
2841
2842	/* ##################################### Debug In/Output function ########################################### */
2843	/**
2844	\ingroup CMSIS_Core_FunctionInterface
2845	\defgroup CMSIS_core_DebugFunctions ITM Functions
2846	\brief Functions that access the ITM debug interface.
2847	@{
2848	*/
2849
2850	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
2851	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
2852
2853
2854	/**
2855	\brief ITM Send Character
2856	\details Transmits a character via the ITM channel 0, and
2857	\li Just returns when no debugger is connected that has booked the output.
2858	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2859	\param [in] ch Character to transmit.
2860	\returns Character to transmit.
2861	*/
2862	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2863	{
2864	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2865	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2866	{
2867	while (ITM->PORT[0U].u32 == 0UL)
2868	{
2869	__NOP();
2870	}
2871	ITM->PORT[0U].u8 = (uint8_t)ch;
2872	}
2873	return (ch);
2874	}
2875
2876
2877	/**
2878	\brief ITM Receive Character
2879	\details Inputs a character via the external variable \ref ITM_RxBuffer.
2880	\return Received character.
2881	\return -1 No character pending.
2882	*/
2883	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
2884	{
2885	int32_t ch = -1; /* no character available */
2886
2887	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2888	{
2889	ch = ITM_RxBuffer;
2890	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2891	}
2892
2893	return (ch);
2894	}
2895
2896
2897	/**
2898	\brief ITM Check Character
2899	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2900	\return 0 No character available.
2901	\return 1 Character available.
2902	*/
2903	__STATIC_INLINE int32_t ITM_CheckChar (void)
2904	{
2905
2906	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2907	{
2908	return (0); /* no character available */
2909	}
2910	else
2911	{
2912	return (1); /* character available */
2913	}
2914	}
2915
2916	/@} end of CMSIS_core_DebugFunctions /
2917
2918
2919
2920
2921	#ifdef __cplusplus
2922	}
2923	#endif
2924
2925	#endif /* __CORE_ARMV8MML_H_DEPENDANT */
2926
2927	#endif /* __CMSIS_GENERIC */

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source: S-port/trunk/Drivers/CMSIS/Include/core_armv8mml.h

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