source: S-port/trunk/Drivers/CMSIS/Include/core_cm1.h

Last change on this file was 1, checked in by AlexLir, 4 years ago
File size: 42.4 KB
Line 
1/**************************************************************************//**
2 * @file core_cm1.h
3 * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
4 * @version V1.0.0
5 * @date 23. July 2018
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_CM1_H_GENERIC
32#define __CORE_CM1_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup Cortex_M1
60 @{
61 */
62
63#include "cmsis_version.h"
64
65/* CMSIS CM1 definitions */
66#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
69 __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71#define __CORTEX_M (1U) /*!< Cortex-M Core */
72
73/** __FPU_USED indicates whether an FPU is used or not.
74 This core does not support an FPU at all
75*/
76#define __FPU_USED 0U
77
78#if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_PCS_VFP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88#elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93#elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98#elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103#elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108#elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113#endif
114
115#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116
117
118#ifdef __cplusplus
119}
120#endif
121
122#endif /* __CORE_CM1_H_GENERIC */
123
124#ifndef __CMSIS_GENERIC
125
126#ifndef __CORE_CM1_H_DEPENDANT
127#define __CORE_CM1_H_DEPENDANT
128
129#ifdef __cplusplus
130 extern "C" {
131#endif
132
133/* check device defines and use defaults */
134#if defined __CHECK_DEVICE_DEFINES
135 #ifndef __CM1_REV
136 #define __CM1_REV 0x0100U
137 #warning "__CM1_REV not defined in device header file; using default!"
138 #endif
139
140 #ifndef __NVIC_PRIO_BITS
141 #define __NVIC_PRIO_BITS 2U
142 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
143 #endif
144
145 #ifndef __Vendor_SysTickConfig
146 #define __Vendor_SysTickConfig 0U
147 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
148 #endif
149#endif
150
151/* IO definitions (access restrictions to peripheral registers) */
152/**
153 \defgroup CMSIS_glob_defs CMSIS Global Defines
154
155 <strong>IO Type Qualifiers</strong> are used
156 \li to specify the access to peripheral variables.
157 \li for automatic generation of peripheral register debug information.
158*/
159#ifdef __cplusplus
160 #define __I volatile /*!< Defines 'read only' permissions */
161#else
162 #define __I volatile const /*!< Defines 'read only' permissions */
163#endif
164#define __O volatile /*!< Defines 'write only' permissions */
165#define __IO volatile /*!< Defines 'read / write' permissions */
166
167/* following defines should be used for structure members */
168#define __IM volatile const /*! Defines 'read only' structure member permissions */
169#define __OM volatile /*! Defines 'write only' structure member permissions */
170#define __IOM volatile /*! Defines 'read / write' structure member permissions */
171
172/*@} end of group Cortex_M1 */
173
174
175
176/*******************************************************************************
177 * Register Abstraction
178 Core Register contain:
179 - Core Register
180 - Core NVIC Register
181 - Core SCB Register
182 - Core SysTick Register
183 ******************************************************************************/
184/**
185 \defgroup CMSIS_core_register Defines and Type Definitions
186 \brief Type definitions and defines for Cortex-M processor based devices.
187*/
188
189/**
190 \ingroup CMSIS_core_register
191 \defgroup CMSIS_CORE Status and Control Registers
192 \brief Core Register type definitions.
193 @{
194 */
195
196/**
197 \brief Union type to access the Application Program Status Register (APSR).
198 */
199typedef union
200{
201 struct
202 {
203 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
204 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
205 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
206 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
207 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
208 } b; /*!< Structure used for bit access */
209 uint32_t w; /*!< Type used for word access */
210} APSR_Type;
211
212/* APSR Register Definitions */
213#define APSR_N_Pos 31U /*!< APSR: N Position */
214#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
215
216#define APSR_Z_Pos 30U /*!< APSR: Z Position */
217#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
218
219#define APSR_C_Pos 29U /*!< APSR: C Position */
220#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
221
222#define APSR_V_Pos 28U /*!< APSR: V Position */
223#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
224
225
226/**
227 \brief Union type to access the Interrupt Program Status Register (IPSR).
228 */
229typedef union
230{
231 struct
232 {
233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
235 } b; /*!< Structure used for bit access */
236 uint32_t w; /*!< Type used for word access */
237} IPSR_Type;
238
239/* IPSR Register Definitions */
240#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
241#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
242
243
244/**
245 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
246 */
247typedef union
248{
249 struct
250 {
251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
252 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
253 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
254 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
255 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
256 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
257 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
258 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
259 } b; /*!< Structure used for bit access */
260 uint32_t w; /*!< Type used for word access */
261} xPSR_Type;
262
263/* xPSR Register Definitions */
264#define xPSR_N_Pos 31U /*!< xPSR: N Position */
265#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
266
267#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
268#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
269
270#define xPSR_C_Pos 29U /*!< xPSR: C Position */
271#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
272
273#define xPSR_V_Pos 28U /*!< xPSR: V Position */
274#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
275
276#define xPSR_T_Pos 24U /*!< xPSR: T Position */
277#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
278
279#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
280#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
281
282
283/**
284 \brief Union type to access the Control Registers (CONTROL).
285 */
286typedef union
287{
288 struct
289 {
290 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
291 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
292 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
293 } b; /*!< Structure used for bit access */
294 uint32_t w; /*!< Type used for word access */
295} CONTROL_Type;
296
297/* CONTROL Register Definitions */
298#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
299#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
300
301/*@} end of group CMSIS_CORE */
302
303
304/**
305 \ingroup CMSIS_core_register
306 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
307 \brief Type definitions for the NVIC Registers
308 @{
309 */
310
311/**
312 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
313 */
314typedef struct
315{
316 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
317 uint32_t RESERVED0[31U];
318 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
319 uint32_t RSERVED1[31U];
320 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
321 uint32_t RESERVED2[31U];
322 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
323 uint32_t RESERVED3[31U];
324 uint32_t RESERVED4[64U];
325 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
326} NVIC_Type;
327
328/*@} end of group CMSIS_NVIC */
329
330
331/**
332 \ingroup CMSIS_core_register
333 \defgroup CMSIS_SCB System Control Block (SCB)
334 \brief Type definitions for the System Control Block Registers
335 @{
336 */
337
338/**
339 \brief Structure type to access the System Control Block (SCB).
340 */
341typedef struct
342{
343 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
344 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
345 uint32_t RESERVED0;
346 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
347 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
349 uint32_t RESERVED1;
350 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
351 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
352} SCB_Type;
353
354/* SCB CPUID Register Definitions */
355#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
356#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
357
358#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
359#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
360
361#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
362#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
363
364#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
365#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
366
367#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
368#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
369
370/* SCB Interrupt Control State Register Definitions */
371#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
372#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
373
374#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
375#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
376
377#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
378#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
379
380#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
381#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
382
383#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
384#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
385
386#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
387#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
388
389#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
390#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
391
392#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
393#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
394
395#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
396#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
397
398/* SCB Application Interrupt and Reset Control Register Definitions */
399#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
400#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
401
402#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
403#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
404
405#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
406#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
407
408#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
409#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
410
411#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
412#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
413
414/* SCB System Control Register Definitions */
415#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
416#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
417
418#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
419#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
420
421#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
422#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
423
424/* SCB Configuration Control Register Definitions */
425#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
426#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
427
428#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
429#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
430
431/* SCB System Handler Control and State Register Definitions */
432#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
433#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
434
435/*@} end of group CMSIS_SCB */
436
437
438/**
439 \ingroup CMSIS_core_register
440 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
441 \brief Type definitions for the System Control and ID Register not in the SCB
442 @{
443 */
444
445/**
446 \brief Structure type to access the System Control and ID Register not in the SCB.
447 */
448typedef struct
449{
450 uint32_t RESERVED0[2U];
451 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
452} SCnSCB_Type;
453
454/* Auxiliary Control Register Definitions */
455#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
456#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
457
458#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
459#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
460
461/*@} end of group CMSIS_SCnotSCB */
462
463
464/**
465 \ingroup CMSIS_core_register
466 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
467 \brief Type definitions for the System Timer Registers.
468 @{
469 */
470
471/**
472 \brief Structure type to access the System Timer (SysTick).
473 */
474typedef struct
475{
476 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
477 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
478 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
479 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
480} SysTick_Type;
481
482/* SysTick Control / Status Register Definitions */
483#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
484#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
485
486#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
487#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
488
489#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
490#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
491
492#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
493#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
494
495/* SysTick Reload Register Definitions */
496#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
497#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
498
499/* SysTick Current Register Definitions */
500#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
501#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
502
503/* SysTick Calibration Register Definitions */
504#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
505#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
506
507#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
508#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
509
510#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
511#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
512
513/*@} end of group CMSIS_SysTick */
514
515
516/**
517 \ingroup CMSIS_core_register
518 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
519 \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
520 Therefore they are not covered by the Cortex-M1 header file.
521 @{
522 */
523/*@} end of group CMSIS_CoreDebug */
524
525
526/**
527 \ingroup CMSIS_core_register
528 \defgroup CMSIS_core_bitfield Core register bit field macros
529 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
530 @{
531 */
532
533/**
534 \brief Mask and shift a bit field value for use in a register bit range.
535 \param[in] field Name of the register bit field.
536 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
537 \return Masked and shifted value.
538*/
539#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
540
541/**
542 \brief Mask and shift a register value to extract a bit filed value.
543 \param[in] field Name of the register bit field.
544 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
545 \return Masked and shifted bit field value.
546*/
547#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
548
549/*@} end of group CMSIS_core_bitfield */
550
551
552/**
553 \ingroup CMSIS_core_register
554 \defgroup CMSIS_core_base Core Definitions
555 \brief Definitions for base addresses, unions, and structures.
556 @{
557 */
558
559/* Memory mapping of Core Hardware */
560#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
561#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
562#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
563#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
564
565#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
566#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
567#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
568#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
569
570
571/*@} */
572
573
574
575/*******************************************************************************
576 * Hardware Abstraction Layer
577 Core Function Interface contains:
578 - Core NVIC Functions
579 - Core SysTick Functions
580 - Core Register Access Functions
581 ******************************************************************************/
582/**
583 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
584*/
585
586
587
588/* ########################## NVIC functions #################################### */
589/**
590 \ingroup CMSIS_Core_FunctionInterface
591 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
592 \brief Functions that manage interrupts and exceptions via the NVIC.
593 @{
594 */
595
596#ifdef CMSIS_NVIC_VIRTUAL
597 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
598 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
599 #endif
600 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
601#else
602 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
603 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
604 #define NVIC_EnableIRQ __NVIC_EnableIRQ
605 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
606 #define NVIC_DisableIRQ __NVIC_DisableIRQ
607 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
608 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
609 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
610/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
611 #define NVIC_SetPriority __NVIC_SetPriority
612 #define NVIC_GetPriority __NVIC_GetPriority
613 #define NVIC_SystemReset __NVIC_SystemReset
614#endif /* CMSIS_NVIC_VIRTUAL */
615
616#ifdef CMSIS_VECTAB_VIRTUAL
617 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
618 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
619 #endif
620 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
621#else
622 #define NVIC_SetVector __NVIC_SetVector
623 #define NVIC_GetVector __NVIC_GetVector
624#endif /* (CMSIS_VECTAB_VIRTUAL) */
625
626#define NVIC_USER_IRQ_OFFSET 16
627
628
629/* The following EXC_RETURN values are saved the LR on exception entry */
630#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
631#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
632#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
633
634
635/* Interrupt Priorities are WORD accessible only under Armv6-M */
636/* The following MACROS handle generation of the register offset and byte masks */
637#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
638#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
639#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
640
641#define __NVIC_SetPriorityGrouping(X) (void)(X)
642#define __NVIC_GetPriorityGrouping() (0U)
643
644/**
645 \brief Enable Interrupt
646 \details Enables a device specific interrupt in the NVIC interrupt controller.
647 \param [in] IRQn Device specific interrupt number.
648 \note IRQn must not be negative.
649 */
650__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
651{
652 if ((int32_t)(IRQn) >= 0)
653 {
654 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
655 }
656}
657
658
659/**
660 \brief Get Interrupt Enable status
661 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
662 \param [in] IRQn Device specific interrupt number.
663 \return 0 Interrupt is not enabled.
664 \return 1 Interrupt is enabled.
665 \note IRQn must not be negative.
666 */
667__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
668{
669 if ((int32_t)(IRQn) >= 0)
670 {
671 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
672 }
673 else
674 {
675 return(0U);
676 }
677}
678
679
680/**
681 \brief Disable Interrupt
682 \details Disables a device specific interrupt in the NVIC interrupt controller.
683 \param [in] IRQn Device specific interrupt number.
684 \note IRQn must not be negative.
685 */
686__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
687{
688 if ((int32_t)(IRQn) >= 0)
689 {
690 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
691 __DSB();
692 __ISB();
693 }
694}
695
696
697/**
698 \brief Get Pending Interrupt
699 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
700 \param [in] IRQn Device specific interrupt number.
701 \return 0 Interrupt status is not pending.
702 \return 1 Interrupt status is pending.
703 \note IRQn must not be negative.
704 */
705__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
706{
707 if ((int32_t)(IRQn) >= 0)
708 {
709 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
710 }
711 else
712 {
713 return(0U);
714 }
715}
716
717
718/**
719 \brief Set Pending Interrupt
720 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
721 \param [in] IRQn Device specific interrupt number.
722 \note IRQn must not be negative.
723 */
724__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
725{
726 if ((int32_t)(IRQn) >= 0)
727 {
728 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
729 }
730}
731
732
733/**
734 \brief Clear Pending Interrupt
735 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
736 \param [in] IRQn Device specific interrupt number.
737 \note IRQn must not be negative.
738 */
739__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
740{
741 if ((int32_t)(IRQn) >= 0)
742 {
743 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
744 }
745}
746
747
748/**
749 \brief Set Interrupt Priority
750 \details Sets the priority of a device specific interrupt or a processor exception.
751 The interrupt number can be positive to specify a device specific interrupt,
752 or negative to specify a processor exception.
753 \param [in] IRQn Interrupt number.
754 \param [in] priority Priority to set.
755 \note The priority cannot be set for every processor exception.
756 */
757__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
758{
759 if ((int32_t)(IRQn) >= 0)
760 {
761 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
762 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
763 }
764 else
765 {
766 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
767 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
768 }
769}
770
771
772/**
773 \brief Get Interrupt Priority
774 \details Reads the priority of a device specific interrupt or a processor exception.
775 The interrupt number can be positive to specify a device specific interrupt,
776 or negative to specify a processor exception.
777 \param [in] IRQn Interrupt number.
778 \return Interrupt Priority.
779 Value is aligned automatically to the implemented priority bits of the microcontroller.
780 */
781__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
782{
783
784 if ((int32_t)(IRQn) >= 0)
785 {
786 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
787 }
788 else
789 {
790 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
791 }
792}
793
794
795/**
796 \brief Encode Priority
797 \details Encodes the priority for an interrupt with the given priority group,
798 preemptive priority value, and subpriority value.
799 In case of a conflict between priority grouping and available
800 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
801 \param [in] PriorityGroup Used priority group.
802 \param [in] PreemptPriority Preemptive priority value (starting from 0).
803 \param [in] SubPriority Subpriority value (starting from 0).
804 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
805 */
806__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
807{
808 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
809 uint32_t PreemptPriorityBits;
810 uint32_t SubPriorityBits;
811
812 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
813 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
814
815 return (
816 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
817 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
818 );
819}
820
821
822/**
823 \brief Decode Priority
824 \details Decodes an interrupt priority value with a given priority group to
825 preemptive priority value and subpriority value.
826 In case of a conflict between priority grouping and available
827 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
828 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
829 \param [in] PriorityGroup Used priority group.
830 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
831 \param [out] pSubPriority Subpriority value (starting from 0).
832 */
833__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
834{
835 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
836 uint32_t PreemptPriorityBits;
837 uint32_t SubPriorityBits;
838
839 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
840 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
841
842 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
843 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
844}
845
846
847
848/**
849 \brief Set Interrupt Vector
850 \details Sets an interrupt vector in SRAM based interrupt vector table.
851 The interrupt number can be positive to specify a device specific interrupt,
852 or negative to specify a processor exception.
853 Address 0 must be mapped to SRAM.
854 \param [in] IRQn Interrupt number
855 \param [in] vector Address of interrupt handler function
856 */
857__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
858{
859 uint32_t *vectors = (uint32_t *)0x0U;
860 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
861}
862
863
864/**
865 \brief Get Interrupt Vector
866 \details Reads an interrupt vector from interrupt vector table.
867 The interrupt number can be positive to specify a device specific interrupt,
868 or negative to specify a processor exception.
869 \param [in] IRQn Interrupt number.
870 \return Address of interrupt handler function
871 */
872__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
873{
874 uint32_t *vectors = (uint32_t *)0x0U;
875 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
876}
877
878
879/**
880 \brief System Reset
881 \details Initiates a system reset request to reset the MCU.
882 */
883__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
884{
885 __DSB(); /* Ensure all outstanding memory accesses included
886 buffered write are completed before reset */
887 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
888 SCB_AIRCR_SYSRESETREQ_Msk);
889 __DSB(); /* Ensure completion of memory access */
890
891 for(;;) /* wait until reset */
892 {
893 __NOP();
894 }
895}
896
897/*@} end of CMSIS_Core_NVICFunctions */
898
899
900/* ########################## FPU functions #################################### */
901/**
902 \ingroup CMSIS_Core_FunctionInterface
903 \defgroup CMSIS_Core_FpuFunctions FPU Functions
904 \brief Function that provides FPU type.
905 @{
906 */
907
908/**
909 \brief get FPU type
910 \details returns the FPU type
911 \returns
912 - \b 0: No FPU
913 - \b 1: Single precision FPU
914 - \b 2: Double + Single precision FPU
915 */
916__STATIC_INLINE uint32_t SCB_GetFPUType(void)
917{
918 return 0U; /* No FPU */
919}
920
921
922/*@} end of CMSIS_Core_FpuFunctions */
923
924
925
926/* ################################## SysTick function ############################################ */
927/**
928 \ingroup CMSIS_Core_FunctionInterface
929 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
930 \brief Functions that configure the System.
931 @{
932 */
933
934#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
935
936/**
937 \brief System Tick Configuration
938 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
939 Counter is in free running mode to generate periodic interrupts.
940 \param [in] ticks Number of ticks between two interrupts.
941 \return 0 Function succeeded.
942 \return 1 Function failed.
943 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
944 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
945 must contain a vendor-specific implementation of this function.
946 */
947__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
948{
949 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
950 {
951 return (1UL); /* Reload value impossible */
952 }
953
954 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
955 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
956 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
957 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
958 SysTick_CTRL_TICKINT_Msk |
959 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
960 return (0UL); /* Function successful */
961}
962
963#endif
964
965/*@} end of CMSIS_Core_SysTickFunctions */
966
967
968
969
970#ifdef __cplusplus
971}
972#endif
973
974#endif /* __CORE_CM1_H_DEPENDANT */
975
976#endif /* __CMSIS_GENERIC */
Note: See TracBrowser for help on using the repository browser.