1 | /**************************************************************************//**
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2 | * @file core_cm7.h
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3 | * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
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4 | * @version V5.0.8
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5 | * @date 04. June 2018
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6 | ******************************************************************************/
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7 | /*
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8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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9 | *
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10 | * SPDX-License-Identifier: Apache-2.0
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11 | *
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12 | * Licensed under the Apache License, Version 2.0 (the License); you may
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13 | * not use this file except in compliance with the License.
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14 | * You may obtain a copy of the License at
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15 | *
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16 | * www.apache.org/licenses/LICENSE-2.0
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17 | *
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18 | * Unless required by applicable law or agreed to in writing, software
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19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 | * See the License for the specific language governing permissions and
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22 | * limitations under the License.
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23 | */
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24 |
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25 | #if defined ( __ICCARM__ )
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26 | #pragma system_include /* treat file as system include file for MISRA check */
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27 | #elif defined (__clang__)
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28 | #pragma clang system_header /* treat file as system include file */
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29 | #endif
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30 |
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31 | #ifndef __CORE_CM7_H_GENERIC
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32 | #define __CORE_CM7_H_GENERIC
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33 |
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34 | #include <stdint.h>
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35 |
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36 | #ifdef __cplusplus
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37 | extern "C" {
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38 | #endif
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39 |
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40 | /**
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41 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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42 | CMSIS violates the following MISRA-C:2004 rules:
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43 |
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44 | \li Required Rule 8.5, object/function definition in header file.<br>
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45 | Function definitions in header files are used to allow 'inlining'.
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46 |
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47 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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48 | Unions are used for effective representation of core registers.
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49 |
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50 | \li Advisory Rule 19.7, Function-like macro defined.<br>
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51 | Function-like macros are used to allow more efficient code.
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52 | */
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53 |
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54 |
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55 | /*******************************************************************************
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56 | * CMSIS definitions
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57 | ******************************************************************************/
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58 | /**
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59 | \ingroup Cortex_M7
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60 | @{
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61 | */
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62 |
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63 | #include "cmsis_version.h"
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64 |
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65 | /* CMSIS CM7 definitions */
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66 | #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
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67 | #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
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68 | #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
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69 | __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
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70 |
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71 | #define __CORTEX_M (7U) /*!< Cortex-M Core */
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72 |
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73 | /** __FPU_USED indicates whether an FPU is used or not.
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74 | For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
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75 | */
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76 | #if defined ( __CC_ARM )
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77 | #if defined __TARGET_FPU_VFP
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78 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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79 | #define __FPU_USED 1U
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80 | #else
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81 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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82 | #define __FPU_USED 0U
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83 | #endif
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84 | #else
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85 | #define __FPU_USED 0U
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86 | #endif
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87 |
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88 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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89 | #if defined __ARM_PCS_VFP
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90 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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91 | #define __FPU_USED 1U
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92 | #else
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93 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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94 | #define __FPU_USED 0U
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95 | #endif
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96 | #else
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97 | #define __FPU_USED 0U
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98 | #endif
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99 |
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100 | #elif defined ( __GNUC__ )
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101 | #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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102 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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103 | #define __FPU_USED 1U
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104 | #else
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105 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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106 | #define __FPU_USED 0U
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107 | #endif
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108 | #else
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109 | #define __FPU_USED 0U
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110 | #endif
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111 |
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112 | #elif defined ( __ICCARM__ )
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113 | #if defined __ARMVFP__
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114 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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115 | #define __FPU_USED 1U
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116 | #else
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117 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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118 | #define __FPU_USED 0U
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119 | #endif
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120 | #else
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121 | #define __FPU_USED 0U
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122 | #endif
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123 |
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124 | #elif defined ( __TI_ARM__ )
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125 | #if defined __TI_VFP_SUPPORT__
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126 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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127 | #define __FPU_USED 1U
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128 | #else
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129 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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130 | #define __FPU_USED 0U
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131 | #endif
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132 | #else
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133 | #define __FPU_USED 0U
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134 | #endif
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135 |
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136 | #elif defined ( __TASKING__ )
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137 | #if defined __FPU_VFP__
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138 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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139 | #define __FPU_USED 1U
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140 | #else
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141 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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142 | #define __FPU_USED 0U
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143 | #endif
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144 | #else
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145 | #define __FPU_USED 0U
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146 | #endif
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147 |
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148 | #elif defined ( __CSMC__ )
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149 | #if ( __CSMC__ & 0x400U)
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150 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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151 | #define __FPU_USED 1U
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152 | #else
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153 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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154 | #define __FPU_USED 0U
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155 | #endif
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156 | #else
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157 | #define __FPU_USED 0U
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158 | #endif
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159 |
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160 | #endif
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161 |
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162 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
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163 |
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164 |
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165 | #ifdef __cplusplus
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166 | }
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167 | #endif
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168 |
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169 | #endif /* __CORE_CM7_H_GENERIC */
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170 |
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171 | #ifndef __CMSIS_GENERIC
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172 |
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173 | #ifndef __CORE_CM7_H_DEPENDANT
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174 | #define __CORE_CM7_H_DEPENDANT
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175 |
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176 | #ifdef __cplusplus
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177 | extern "C" {
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178 | #endif
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179 |
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180 | /* check device defines and use defaults */
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181 | #if defined __CHECK_DEVICE_DEFINES
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182 | #ifndef __CM7_REV
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183 | #define __CM7_REV 0x0000U
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184 | #warning "__CM7_REV not defined in device header file; using default!"
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185 | #endif
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186 |
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187 | #ifndef __FPU_PRESENT
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188 | #define __FPU_PRESENT 0U
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189 | #warning "__FPU_PRESENT not defined in device header file; using default!"
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190 | #endif
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191 |
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192 | #ifndef __MPU_PRESENT
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193 | #define __MPU_PRESENT 0U
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194 | #warning "__MPU_PRESENT not defined in device header file; using default!"
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195 | #endif
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196 |
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197 | #ifndef __ICACHE_PRESENT
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198 | #define __ICACHE_PRESENT 0U
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199 | #warning "__ICACHE_PRESENT not defined in device header file; using default!"
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200 | #endif
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201 |
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202 | #ifndef __DCACHE_PRESENT
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203 | #define __DCACHE_PRESENT 0U
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204 | #warning "__DCACHE_PRESENT not defined in device header file; using default!"
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205 | #endif
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206 |
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207 | #ifndef __DTCM_PRESENT
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208 | #define __DTCM_PRESENT 0U
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209 | #warning "__DTCM_PRESENT not defined in device header file; using default!"
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210 | #endif
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211 |
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212 | #ifndef __NVIC_PRIO_BITS
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213 | #define __NVIC_PRIO_BITS 3U
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214 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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215 | #endif
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216 |
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217 | #ifndef __Vendor_SysTickConfig
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218 | #define __Vendor_SysTickConfig 0U
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219 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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220 | #endif
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221 | #endif
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222 |
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223 | /* IO definitions (access restrictions to peripheral registers) */
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224 | /**
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225 | \defgroup CMSIS_glob_defs CMSIS Global Defines
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226 |
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227 | <strong>IO Type Qualifiers</strong> are used
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228 | \li to specify the access to peripheral variables.
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229 | \li for automatic generation of peripheral register debug information.
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230 | */
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231 | #ifdef __cplusplus
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232 | #define __I volatile /*!< Defines 'read only' permissions */
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233 | #else
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234 | #define __I volatile const /*!< Defines 'read only' permissions */
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235 | #endif
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236 | #define __O volatile /*!< Defines 'write only' permissions */
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237 | #define __IO volatile /*!< Defines 'read / write' permissions */
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238 |
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239 | /* following defines should be used for structure members */
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240 | #define __IM volatile const /*! Defines 'read only' structure member permissions */
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241 | #define __OM volatile /*! Defines 'write only' structure member permissions */
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242 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */
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243 |
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244 | /*@} end of group Cortex_M7 */
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245 |
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246 |
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247 |
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248 | /*******************************************************************************
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249 | * Register Abstraction
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250 | Core Register contain:
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251 | - Core Register
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252 | - Core NVIC Register
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253 | - Core SCB Register
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254 | - Core SysTick Register
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255 | - Core Debug Register
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256 | - Core MPU Register
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257 | - Core FPU Register
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258 | ******************************************************************************/
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259 | /**
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260 | \defgroup CMSIS_core_register Defines and Type Definitions
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261 | \brief Type definitions and defines for Cortex-M processor based devices.
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262 | */
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263 |
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264 | /**
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265 | \ingroup CMSIS_core_register
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266 | \defgroup CMSIS_CORE Status and Control Registers
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267 | \brief Core Register type definitions.
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268 | @{
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269 | */
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270 |
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271 | /**
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272 | \brief Union type to access the Application Program Status Register (APSR).
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273 | */
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274 | typedef union
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275 | {
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276 | struct
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277 | {
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278 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
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279 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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280 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
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281 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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282 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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283 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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284 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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285 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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286 | } b; /*!< Structure used for bit access */
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287 | uint32_t w; /*!< Type used for word access */
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288 | } APSR_Type;
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289 |
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290 | /* APSR Register Definitions */
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291 | #define APSR_N_Pos 31U /*!< APSR: N Position */
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292 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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293 |
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294 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */
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295 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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296 |
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297 | #define APSR_C_Pos 29U /*!< APSR: C Position */
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298 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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299 |
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300 | #define APSR_V_Pos 28U /*!< APSR: V Position */
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301 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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302 |
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303 | #define APSR_Q_Pos 27U /*!< APSR: Q Position */
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304 | #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
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305 |
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306 | #define APSR_GE_Pos 16U /*!< APSR: GE Position */
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307 | #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
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308 |
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309 |
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310 | /**
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311 | \brief Union type to access the Interrupt Program Status Register (IPSR).
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312 | */
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313 | typedef union
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314 | {
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315 | struct
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316 | {
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317 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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318 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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319 | } b; /*!< Structure used for bit access */
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320 | uint32_t w; /*!< Type used for word access */
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321 | } IPSR_Type;
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322 |
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323 | /* IPSR Register Definitions */
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324 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
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325 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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326 |
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327 |
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328 | /**
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329 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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330 | */
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331 | typedef union
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332 | {
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333 | struct
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334 | {
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335 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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336 | uint32_t _reserved0:1; /*!< bit: 9 Reserved */
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337 | uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
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338 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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339 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
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340 | uint32_t T:1; /*!< bit: 24 Thumb bit */
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341 | uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
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342 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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343 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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344 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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345 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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346 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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347 | } b; /*!< Structure used for bit access */
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348 | uint32_t w; /*!< Type used for word access */
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349 | } xPSR_Type;
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350 |
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351 | /* xPSR Register Definitions */
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352 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */
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353 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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354 |
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355 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
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356 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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357 |
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358 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */
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359 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
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360 |
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361 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */
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362 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
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363 |
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364 | #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
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365 | #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
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366 |
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367 | #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
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368 | #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
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369 |
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370 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */
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371 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
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372 |
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373 | #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
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374 | #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
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375 |
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376 | #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
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377 | #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
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378 |
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379 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
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380 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
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381 |
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382 |
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383 | /**
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384 | \brief Union type to access the Control Registers (CONTROL).
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385 | */
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386 | typedef union
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387 | {
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388 | struct
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389 | {
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390 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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391 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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392 | uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
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393 | uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
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394 | } b; /*!< Structure used for bit access */
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395 | uint32_t w; /*!< Type used for word access */
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396 | } CONTROL_Type;
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397 |
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398 | /* CONTROL Register Definitions */
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399 | #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
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400 | #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
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401 |
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402 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
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403 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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404 |
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405 | #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
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406 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
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407 |
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408 | /*@} end of group CMSIS_CORE */
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409 |
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410 |
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411 | /**
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412 | \ingroup CMSIS_core_register
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413 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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414 | \brief Type definitions for the NVIC Registers
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415 | @{
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416 | */
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417 |
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418 | /**
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419 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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420 | */
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421 | typedef struct
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422 | {
|
---|
423 | __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
---|
424 | uint32_t RESERVED0[24U];
|
---|
425 | __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
---|
426 | uint32_t RSERVED1[24U];
|
---|
427 | __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
---|
428 | uint32_t RESERVED2[24U];
|
---|
429 | __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
---|
430 | uint32_t RESERVED3[24U];
|
---|
431 | __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
|
---|
432 | uint32_t RESERVED4[56U];
|
---|
433 | __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
|
---|
434 | uint32_t RESERVED5[644U];
|
---|
435 | __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
|
---|
436 | } NVIC_Type;
|
---|
437 |
|
---|
438 | /* Software Triggered Interrupt Register Definitions */
|
---|
439 | #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
|
---|
440 | #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
|
---|
441 |
|
---|
442 | /*@} end of group CMSIS_NVIC */
|
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443 |
|
---|
444 |
|
---|
445 | /**
|
---|
446 | \ingroup CMSIS_core_register
|
---|
447 | \defgroup CMSIS_SCB System Control Block (SCB)
|
---|
448 | \brief Type definitions for the System Control Block Registers
|
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449 | @{
|
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450 | */
|
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451 |
|
---|
452 | /**
|
---|
453 | \brief Structure type to access the System Control Block (SCB).
|
---|
454 | */
|
---|
455 | typedef struct
|
---|
456 | {
|
---|
457 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
---|
458 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
---|
459 | __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
---|
460 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
---|
461 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
---|
462 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
---|
463 | __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
|
---|
464 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
---|
465 | __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
|
---|
466 | __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
|
---|
467 | __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
|
---|
468 | __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
|
---|
469 | __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
|
---|
470 | __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
|
---|
471 | __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
|
---|
472 | __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
|
---|
473 | __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
|
---|
474 | __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
|
---|
475 | __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
|
---|
476 | uint32_t RESERVED0[1U];
|
---|
477 | __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
|
---|
478 | __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
|
---|
479 | __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
|
---|
480 | __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
|
---|
481 | __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
|
---|
482 | uint32_t RESERVED3[93U];
|
---|
483 | __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
|
---|
484 | uint32_t RESERVED4[15U];
|
---|
485 | __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
|
---|
486 | __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
|
---|
487 | __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
|
---|
488 | uint32_t RESERVED5[1U];
|
---|
489 | __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
|
---|
490 | uint32_t RESERVED6[1U];
|
---|
491 | __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
|
---|
492 | __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
|
---|
493 | __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
|
---|
494 | __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
|
---|
495 | __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
|
---|
496 | __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
|
---|
497 | __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
|
---|
498 | __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
|
---|
499 | uint32_t RESERVED7[6U];
|
---|
500 | __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
|
---|
501 | __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
|
---|
502 | __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
|
---|
503 | __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
|
---|
504 | __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
|
---|
505 | uint32_t RESERVED8[1U];
|
---|
506 | __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
|
---|
507 | } SCB_Type;
|
---|
508 |
|
---|
509 | /* SCB CPUID Register Definitions */
|
---|
510 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
---|
511 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
---|
512 |
|
---|
513 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
---|
514 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
---|
515 |
|
---|
516 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
---|
517 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
---|
518 |
|
---|
519 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
---|
520 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
---|
521 |
|
---|
522 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
---|
523 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
---|
524 |
|
---|
525 | /* SCB Interrupt Control State Register Definitions */
|
---|
526 | #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
---|
527 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
---|
528 |
|
---|
529 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
---|
530 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
---|
531 |
|
---|
532 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
---|
533 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
---|
534 |
|
---|
535 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
---|
536 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
---|
537 |
|
---|
538 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
---|
539 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
---|
540 |
|
---|
541 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
---|
542 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
---|
543 |
|
---|
544 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
---|
545 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
---|
546 |
|
---|
547 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
---|
548 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
---|
549 |
|
---|
550 | #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
|
---|
551 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
|
---|
552 |
|
---|
553 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
---|
554 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
---|
555 |
|
---|
556 | /* SCB Vector Table Offset Register Definitions */
|
---|
557 | #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
|
---|
558 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
---|
559 |
|
---|
560 | /* SCB Application Interrupt and Reset Control Register Definitions */
|
---|
561 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
---|
562 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
---|
563 |
|
---|
564 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
---|
565 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
---|
566 |
|
---|
567 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
---|
568 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
---|
569 |
|
---|
570 | #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
|
---|
571 | #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
|
---|
572 |
|
---|
573 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
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574 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
---|
575 |
|
---|
576 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
---|
577 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
---|
578 |
|
---|
579 | #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
|
---|
580 | #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
|
---|
581 |
|
---|
582 | /* SCB System Control Register Definitions */
|
---|
583 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
---|
584 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
---|
585 |
|
---|
586 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
---|
587 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
---|
588 |
|
---|
589 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
---|
590 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
---|
591 |
|
---|
592 | /* SCB Configuration Control Register Definitions */
|
---|
593 | #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
|
---|
594 | #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
|
---|
595 |
|
---|
596 | #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
|
---|
597 | #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
|
---|
598 |
|
---|
599 | #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
|
---|
600 | #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
|
---|
601 |
|
---|
602 | #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
---|
603 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
---|
604 |
|
---|
605 | #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
|
---|
606 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
|
---|
607 |
|
---|
608 | #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
|
---|
609 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
|
---|
610 |
|
---|
611 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
---|
612 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
---|
613 |
|
---|
614 | #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
|
---|
615 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
|
---|
616 |
|
---|
617 | #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
|
---|
618 | #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
|
---|
619 |
|
---|
620 | /* SCB System Handler Control and State Register Definitions */
|
---|
621 | #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
|
---|
622 | #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
|
---|
623 |
|
---|
624 | #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
|
---|
625 | #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
|
---|
626 |
|
---|
627 | #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
|
---|
628 | #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
|
---|
629 |
|
---|
630 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
---|
631 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
---|
632 |
|
---|
633 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
|
---|
634 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
|
---|
635 |
|
---|
636 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
|
---|
637 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
|
---|
638 |
|
---|
639 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
|
---|
640 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
|
---|
641 |
|
---|
642 | #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
|
---|
643 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
|
---|
644 |
|
---|
645 | #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
|
---|
646 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
|
---|
647 |
|
---|
648 | #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
|
---|
649 | #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
|
---|
650 |
|
---|
651 | #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
|
---|
652 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
|
---|
653 |
|
---|
654 | #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
|
---|
655 | #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
|
---|
656 |
|
---|
657 | #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
|
---|
658 | #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
|
---|
659 |
|
---|
660 | #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
|
---|
661 | #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
|
---|
662 |
|
---|
663 | /* SCB Configurable Fault Status Register Definitions */
|
---|
664 | #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
|
---|
665 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
|
---|
666 |
|
---|
667 | #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
|
---|
668 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
|
---|
669 |
|
---|
670 | #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
---|
671 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
---|
672 |
|
---|
673 | /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
|
---|
674 | #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
---|
675 | #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
---|
676 |
|
---|
677 | #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
|
---|
678 | #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
|
---|
679 |
|
---|
680 | #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
---|
681 | #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
---|
682 |
|
---|
683 | #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
---|
684 | #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
---|
685 |
|
---|
686 | #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
---|
687 | #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
---|
688 |
|
---|
689 | #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
---|
690 | #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
---|
691 |
|
---|
692 | /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
|
---|
693 | #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
---|
694 | #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
---|
695 |
|
---|
696 | #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
|
---|
697 | #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
|
---|
698 |
|
---|
699 | #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
---|
700 | #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
---|
701 |
|
---|
702 | #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
---|
703 | #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
---|
704 |
|
---|
705 | #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
---|
706 | #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
---|
707 |
|
---|
708 | #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
---|
709 | #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
---|
710 |
|
---|
711 | #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
---|
712 | #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
---|
713 |
|
---|
714 | /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
|
---|
715 | #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
---|
716 | #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
---|
717 |
|
---|
718 | #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
---|
719 | #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
---|
720 |
|
---|
721 | #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
---|
722 | #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
---|
723 |
|
---|
724 | #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
---|
725 | #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
---|
726 |
|
---|
727 | #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
---|
728 | #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
---|
729 |
|
---|
730 | #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
---|
731 | #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
---|
732 |
|
---|
733 | /* SCB Hard Fault Status Register Definitions */
|
---|
734 | #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
---|
735 | #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
---|
736 |
|
---|
737 | #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
|
---|
738 | #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
|
---|
739 |
|
---|
740 | #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
|
---|
741 | #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
|
---|
742 |
|
---|
743 | /* SCB Debug Fault Status Register Definitions */
|
---|
744 | #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
|
---|
745 | #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
|
---|
746 |
|
---|
747 | #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
|
---|
748 | #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
|
---|
749 |
|
---|
750 | #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
|
---|
751 | #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
|
---|
752 |
|
---|
753 | #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
|
---|
754 | #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
|
---|
755 |
|
---|
756 | #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
|
---|
757 | #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
|
---|
758 |
|
---|
759 | /* SCB Cache Level ID Register Definitions */
|
---|
760 | #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
|
---|
761 | #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
|
---|
762 |
|
---|
763 | #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
|
---|
764 | #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
|
---|
765 |
|
---|
766 | /* SCB Cache Type Register Definitions */
|
---|
767 | #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
|
---|
768 | #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
|
---|
769 |
|
---|
770 | #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
|
---|
771 | #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
|
---|
772 |
|
---|
773 | #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
|
---|
774 | #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
|
---|
775 |
|
---|
776 | #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
|
---|
777 | #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
|
---|
778 |
|
---|
779 | #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
|
---|
780 | #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
|
---|
781 |
|
---|
782 | /* SCB Cache Size ID Register Definitions */
|
---|
783 | #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
|
---|
784 | #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
|
---|
785 |
|
---|
786 | #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
|
---|
787 | #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
|
---|
788 |
|
---|
789 | #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
|
---|
790 | #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
|
---|
791 |
|
---|
792 | #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
|
---|
793 | #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
|
---|
794 |
|
---|
795 | #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
|
---|
796 | #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
|
---|
797 |
|
---|
798 | #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
|
---|
799 | #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
|
---|
800 |
|
---|
801 | #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
|
---|
802 | #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
|
---|
803 |
|
---|
804 | /* SCB Cache Size Selection Register Definitions */
|
---|
805 | #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
|
---|
806 | #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
|
---|
807 |
|
---|
808 | #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
|
---|
809 | #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
|
---|
810 |
|
---|
811 | /* SCB Software Triggered Interrupt Register Definitions */
|
---|
812 | #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
|
---|
813 | #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
|
---|
814 |
|
---|
815 | /* SCB D-Cache Invalidate by Set-way Register Definitions */
|
---|
816 | #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
|
---|
817 | #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
|
---|
818 |
|
---|
819 | #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
|
---|
820 | #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
|
---|
821 |
|
---|
822 | /* SCB D-Cache Clean by Set-way Register Definitions */
|
---|
823 | #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
|
---|
824 | #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
|
---|
825 |
|
---|
826 | #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
|
---|
827 | #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
|
---|
828 |
|
---|
829 | /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
|
---|
830 | #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
|
---|
831 | #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
|
---|
832 |
|
---|
833 | #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
|
---|
834 | #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
|
---|
835 |
|
---|
836 | /* Instruction Tightly-Coupled Memory Control Register Definitions */
|
---|
837 | #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
|
---|
838 | #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
|
---|
839 |
|
---|
840 | #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
|
---|
841 | #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
|
---|
842 |
|
---|
843 | #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
|
---|
844 | #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
|
---|
845 |
|
---|
846 | #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
|
---|
847 | #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
|
---|
848 |
|
---|
849 | /* Data Tightly-Coupled Memory Control Register Definitions */
|
---|
850 | #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
|
---|
851 | #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
|
---|
852 |
|
---|
853 | #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
|
---|
854 | #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
|
---|
855 |
|
---|
856 | #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
|
---|
857 | #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
|
---|
858 |
|
---|
859 | #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
|
---|
860 | #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
|
---|
861 |
|
---|
862 | /* AHBP Control Register Definitions */
|
---|
863 | #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
|
---|
864 | #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
|
---|
865 |
|
---|
866 | #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
|
---|
867 | #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
|
---|
868 |
|
---|
869 | /* L1 Cache Control Register Definitions */
|
---|
870 | #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
|
---|
871 | #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
|
---|
872 |
|
---|
873 | #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
|
---|
874 | #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
|
---|
875 |
|
---|
876 | #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
|
---|
877 | #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
|
---|
878 |
|
---|
879 | /* AHBS Control Register Definitions */
|
---|
880 | #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
|
---|
881 | #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
|
---|
882 |
|
---|
883 | #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
|
---|
884 | #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
|
---|
885 |
|
---|
886 | #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
|
---|
887 | #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
|
---|
888 |
|
---|
889 | /* Auxiliary Bus Fault Status Register Definitions */
|
---|
890 | #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
|
---|
891 | #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
|
---|
892 |
|
---|
893 | #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
|
---|
894 | #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
|
---|
895 |
|
---|
896 | #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
|
---|
897 | #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
|
---|
898 |
|
---|
899 | #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
|
---|
900 | #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
|
---|
901 |
|
---|
902 | #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
|
---|
903 | #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
|
---|
904 |
|
---|
905 | #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
|
---|
906 | #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
|
---|
907 |
|
---|
908 | /*@} end of group CMSIS_SCB */
|
---|
909 |
|
---|
910 |
|
---|
911 | /**
|
---|
912 | \ingroup CMSIS_core_register
|
---|
913 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
---|
914 | \brief Type definitions for the System Control and ID Register not in the SCB
|
---|
915 | @{
|
---|
916 | */
|
---|
917 |
|
---|
918 | /**
|
---|
919 | \brief Structure type to access the System Control and ID Register not in the SCB.
|
---|
920 | */
|
---|
921 | typedef struct
|
---|
922 | {
|
---|
923 | uint32_t RESERVED0[1U];
|
---|
924 | __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
|
---|
925 | __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
---|
926 | } SCnSCB_Type;
|
---|
927 |
|
---|
928 | /* Interrupt Controller Type Register Definitions */
|
---|
929 | #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
|
---|
930 | #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
|
---|
931 |
|
---|
932 | /* Auxiliary Control Register Definitions */
|
---|
933 | #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
|
---|
934 | #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
|
---|
935 |
|
---|
936 | #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
|
---|
937 | #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
|
---|
938 |
|
---|
939 | #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
|
---|
940 | #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
|
---|
941 |
|
---|
942 | #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
|
---|
943 | #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
|
---|
944 |
|
---|
945 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
|
---|
946 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
|
---|
947 |
|
---|
948 | /*@} end of group CMSIS_SCnotSCB */
|
---|
949 |
|
---|
950 |
|
---|
951 | /**
|
---|
952 | \ingroup CMSIS_core_register
|
---|
953 | \defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
---|
954 | \brief Type definitions for the System Timer Registers.
|
---|
955 | @{
|
---|
956 | */
|
---|
957 |
|
---|
958 | /**
|
---|
959 | \brief Structure type to access the System Timer (SysTick).
|
---|
960 | */
|
---|
961 | typedef struct
|
---|
962 | {
|
---|
963 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
---|
964 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
---|
965 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
---|
966 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
---|
967 | } SysTick_Type;
|
---|
968 |
|
---|
969 | /* SysTick Control / Status Register Definitions */
|
---|
970 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
---|
971 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
---|
972 |
|
---|
973 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
---|
974 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
---|
975 |
|
---|
976 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
---|
977 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
---|
978 |
|
---|
979 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
---|
980 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
---|
981 |
|
---|
982 | /* SysTick Reload Register Definitions */
|
---|
983 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
---|
984 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
---|
985 |
|
---|
986 | /* SysTick Current Register Definitions */
|
---|
987 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
---|
988 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
---|
989 |
|
---|
990 | /* SysTick Calibration Register Definitions */
|
---|
991 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
---|
992 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
---|
993 |
|
---|
994 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
---|
995 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
---|
996 |
|
---|
997 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
---|
998 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
---|
999 |
|
---|
1000 | /*@} end of group CMSIS_SysTick */
|
---|
1001 |
|
---|
1002 |
|
---|
1003 | /**
|
---|
1004 | \ingroup CMSIS_core_register
|
---|
1005 | \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
|
---|
1006 | \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
|
---|
1007 | @{
|
---|
1008 | */
|
---|
1009 |
|
---|
1010 | /**
|
---|
1011 | \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
|
---|
1012 | */
|
---|
1013 | typedef struct
|
---|
1014 | {
|
---|
1015 | __OM union
|
---|
1016 | {
|
---|
1017 | __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
|
---|
1018 | __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
|
---|
1019 | __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
|
---|
1020 | } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
|
---|
1021 | uint32_t RESERVED0[864U];
|
---|
1022 | __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
|
---|
1023 | uint32_t RESERVED1[15U];
|
---|
1024 | __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
|
---|
1025 | uint32_t RESERVED2[15U];
|
---|
1026 | __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
|
---|
1027 | uint32_t RESERVED3[29U];
|
---|
1028 | __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
|
---|
1029 | __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
|
---|
1030 | __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
|
---|
1031 | uint32_t RESERVED4[43U];
|
---|
1032 | __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
|
---|
1033 | __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
|
---|
1034 | uint32_t RESERVED5[6U];
|
---|
1035 | __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
|
---|
1036 | __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
|
---|
1037 | __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
|
---|
1038 | __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
|
---|
1039 | __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
|
---|
1040 | __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
|
---|
1041 | __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
|
---|
1042 | __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
|
---|
1043 | __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
|
---|
1044 | __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
|
---|
1045 | __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
|
---|
1046 | __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
|
---|
1047 | } ITM_Type;
|
---|
1048 |
|
---|
1049 | /* ITM Trace Privilege Register Definitions */
|
---|
1050 | #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
|
---|
1051 | #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
|
---|
1052 |
|
---|
1053 | /* ITM Trace Control Register Definitions */
|
---|
1054 | #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
|
---|
1055 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
|
---|
1056 |
|
---|
1057 | #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
|
---|
1058 | #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
|
---|
1059 |
|
---|
1060 | #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
|
---|
1061 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
|
---|
1062 |
|
---|
1063 | #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
|
---|
1064 | #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
|
---|
1065 |
|
---|
1066 | #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
|
---|
1067 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
|
---|
1068 |
|
---|
1069 | #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
|
---|
1070 | #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
|
---|
1071 |
|
---|
1072 | #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
|
---|
1073 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
|
---|
1074 |
|
---|
1075 | #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
|
---|
1076 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
|
---|
1077 |
|
---|
1078 | #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
|
---|
1079 | #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
|
---|
1080 |
|
---|
1081 | /* ITM Integration Write Register Definitions */
|
---|
1082 | #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
|
---|
1083 | #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
|
---|
1084 |
|
---|
1085 | /* ITM Integration Read Register Definitions */
|
---|
1086 | #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
|
---|
1087 | #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
|
---|
1088 |
|
---|
1089 | /* ITM Integration Mode Control Register Definitions */
|
---|
1090 | #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
|
---|
1091 | #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
|
---|
1092 |
|
---|
1093 | /* ITM Lock Status Register Definitions */
|
---|
1094 | #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
|
---|
1095 | #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
|
---|
1096 |
|
---|
1097 | #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
|
---|
1098 | #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
|
---|
1099 |
|
---|
1100 | #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
|
---|
1101 | #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
|
---|
1102 |
|
---|
1103 | /*@}*/ /* end of group CMSIS_ITM */
|
---|
1104 |
|
---|
1105 |
|
---|
1106 | /**
|
---|
1107 | \ingroup CMSIS_core_register
|
---|
1108 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
|
---|
1109 | \brief Type definitions for the Data Watchpoint and Trace (DWT)
|
---|
1110 | @{
|
---|
1111 | */
|
---|
1112 |
|
---|
1113 | /**
|
---|
1114 | \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
|
---|
1115 | */
|
---|
1116 | typedef struct
|
---|
1117 | {
|
---|
1118 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
|
---|
1119 | __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
|
---|
1120 | __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
|
---|
1121 | __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
|
---|
1122 | __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
|
---|
1123 | __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
|
---|
1124 | __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
|
---|
1125 | __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
|
---|
1126 | __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
|
---|
1127 | __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
|
---|
1128 | __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
|
---|
1129 | uint32_t RESERVED0[1U];
|
---|
1130 | __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
|
---|
1131 | __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
|
---|
1132 | __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
|
---|
1133 | uint32_t RESERVED1[1U];
|
---|
1134 | __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
|
---|
1135 | __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
|
---|
1136 | __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
|
---|
1137 | uint32_t RESERVED2[1U];
|
---|
1138 | __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
|
---|
1139 | __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
|
---|
1140 | __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
|
---|
1141 | uint32_t RESERVED3[981U];
|
---|
1142 | __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
|
---|
1143 | __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
|
---|
1144 | } DWT_Type;
|
---|
1145 |
|
---|
1146 | /* DWT Control Register Definitions */
|
---|
1147 | #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
|
---|
1148 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
|
---|
1149 |
|
---|
1150 | #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
|
---|
1151 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
|
---|
1152 |
|
---|
1153 | #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
|
---|
1154 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
|
---|
1155 |
|
---|
1156 | #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
|
---|
1157 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
|
---|
1158 |
|
---|
1159 | #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
|
---|
1160 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
|
---|
1161 |
|
---|
1162 | #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
|
---|
1163 | #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
|
---|
1164 |
|
---|
1165 | #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
|
---|
1166 | #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
|
---|
1167 |
|
---|
1168 | #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
|
---|
1169 | #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
|
---|
1170 |
|
---|
1171 | #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
|
---|
1172 | #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
|
---|
1173 |
|
---|
1174 | #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
|
---|
1175 | #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
|
---|
1176 |
|
---|
1177 | #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
|
---|
1178 | #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
|
---|
1179 |
|
---|
1180 | #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
|
---|
1181 | #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
|
---|
1182 |
|
---|
1183 | #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
|
---|
1184 | #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
|
---|
1185 |
|
---|
1186 | #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
|
---|
1187 | #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
|
---|
1188 |
|
---|
1189 | #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
|
---|
1190 | #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
|
---|
1191 |
|
---|
1192 | #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
|
---|
1193 | #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
|
---|
1194 |
|
---|
1195 | #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
|
---|
1196 | #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
|
---|
1197 |
|
---|
1198 | #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
|
---|
1199 | #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
|
---|
1200 |
|
---|
1201 | /* DWT CPI Count Register Definitions */
|
---|
1202 | #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
|
---|
1203 | #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
|
---|
1204 |
|
---|
1205 | /* DWT Exception Overhead Count Register Definitions */
|
---|
1206 | #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
|
---|
1207 | #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
|
---|
1208 |
|
---|
1209 | /* DWT Sleep Count Register Definitions */
|
---|
1210 | #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
|
---|
1211 | #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
|
---|
1212 |
|
---|
1213 | /* DWT LSU Count Register Definitions */
|
---|
1214 | #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
|
---|
1215 | #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
|
---|
1216 |
|
---|
1217 | /* DWT Folded-instruction Count Register Definitions */
|
---|
1218 | #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
|
---|
1219 | #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
|
---|
1220 |
|
---|
1221 | /* DWT Comparator Mask Register Definitions */
|
---|
1222 | #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
|
---|
1223 | #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
|
---|
1224 |
|
---|
1225 | /* DWT Comparator Function Register Definitions */
|
---|
1226 | #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
|
---|
1227 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
|
---|
1228 |
|
---|
1229 | #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
|
---|
1230 | #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
|
---|
1231 |
|
---|
1232 | #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
|
---|
1233 | #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
|
---|
1234 |
|
---|
1235 | #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
|
---|
1236 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
|
---|
1237 |
|
---|
1238 | #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
|
---|
1239 | #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
|
---|
1240 |
|
---|
1241 | #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
|
---|
1242 | #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
|
---|
1243 |
|
---|
1244 | #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
|
---|
1245 | #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
|
---|
1246 |
|
---|
1247 | #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
|
---|
1248 | #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
|
---|
1249 |
|
---|
1250 | #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
|
---|
1251 | #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
|
---|
1252 |
|
---|
1253 | /*@}*/ /* end of group CMSIS_DWT */
|
---|
1254 |
|
---|
1255 |
|
---|
1256 | /**
|
---|
1257 | \ingroup CMSIS_core_register
|
---|
1258 | \defgroup CMSIS_TPI Trace Port Interface (TPI)
|
---|
1259 | \brief Type definitions for the Trace Port Interface (TPI)
|
---|
1260 | @{
|
---|
1261 | */
|
---|
1262 |
|
---|
1263 | /**
|
---|
1264 | \brief Structure type to access the Trace Port Interface Register (TPI).
|
---|
1265 | */
|
---|
1266 | typedef struct
|
---|
1267 | {
|
---|
1268 | __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
---|
1269 | __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
---|
1270 | uint32_t RESERVED0[2U];
|
---|
1271 | __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
---|
1272 | uint32_t RESERVED1[55U];
|
---|
1273 | __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
|
---|
1274 | uint32_t RESERVED2[131U];
|
---|
1275 | __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
|
---|
1276 | __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
---|
1277 | __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
---|
1278 | uint32_t RESERVED3[759U];
|
---|
1279 | __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
|
---|
1280 | __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
---|
1281 | __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
---|
1282 | uint32_t RESERVED4[1U];
|
---|
1283 | __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
|
---|
1284 | __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
|
---|
1285 | __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
|
---|
1286 | uint32_t RESERVED5[39U];
|
---|
1287 | __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
|
---|
1288 | __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
|
---|
1289 | uint32_t RESERVED7[8U];
|
---|
1290 | __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
|
---|
1291 | __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
|
---|
1292 | } TPI_Type;
|
---|
1293 |
|
---|
1294 | /* TPI Asynchronous Clock Prescaler Register Definitions */
|
---|
1295 | #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
|
---|
1296 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
|
---|
1297 |
|
---|
1298 | /* TPI Selected Pin Protocol Register Definitions */
|
---|
1299 | #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
|
---|
1300 | #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
|
---|
1301 |
|
---|
1302 | /* TPI Formatter and Flush Status Register Definitions */
|
---|
1303 | #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
|
---|
1304 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
|
---|
1305 |
|
---|
1306 | #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
|
---|
1307 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
|
---|
1308 |
|
---|
1309 | #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
|
---|
1310 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
|
---|
1311 |
|
---|
1312 | #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
|
---|
1313 | #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
|
---|
1314 |
|
---|
1315 | /* TPI Formatter and Flush Control Register Definitions */
|
---|
1316 | #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
|
---|
1317 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
|
---|
1318 |
|
---|
1319 | #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
|
---|
1320 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
|
---|
1321 |
|
---|
1322 | /* TPI TRIGGER Register Definitions */
|
---|
1323 | #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
|
---|
1324 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
|
---|
1325 |
|
---|
1326 | /* TPI Integration ETM Data Register Definitions (FIFO0) */
|
---|
1327 | #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
|
---|
1328 | #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
|
---|
1329 |
|
---|
1330 | #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
|
---|
1331 | #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
|
---|
1332 |
|
---|
1333 | #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
|
---|
1334 | #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
|
---|
1335 |
|
---|
1336 | #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
|
---|
1337 | #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
|
---|
1338 |
|
---|
1339 | #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
|
---|
1340 | #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
|
---|
1341 |
|
---|
1342 | #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
|
---|
1343 | #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
|
---|
1344 |
|
---|
1345 | #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
|
---|
1346 | #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
---|
1347 |
|
---|
1348 | /* TPI ITATBCTR2 Register Definitions */
|
---|
1349 | #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
|
---|
1350 | #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
|
---|
1351 |
|
---|
1352 | #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
|
---|
1353 | #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
|
---|
1354 |
|
---|
1355 | /* TPI Integration ITM Data Register Definitions (FIFO1) */
|
---|
1356 | #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
---|
1357 | #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
|
---|
1358 |
|
---|
1359 | #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
|
---|
1360 | #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
|
---|
1361 |
|
---|
1362 | #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
|
---|
1363 | #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
|
---|
1364 |
|
---|
1365 | #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
|
---|
1366 | #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
|
---|
1367 |
|
---|
1368 | #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
|
---|
1369 | #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
|
---|
1370 |
|
---|
1371 | #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
|
---|
1372 | #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
|
---|
1373 |
|
---|
1374 | #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
|
---|
1375 | #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
---|
1376 |
|
---|
1377 | /* TPI ITATBCTR0 Register Definitions */
|
---|
1378 | #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
|
---|
1379 | #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
|
---|
1380 |
|
---|
1381 | #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
|
---|
1382 | #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
|
---|
1383 |
|
---|
1384 | /* TPI Integration Mode Control Register Definitions */
|
---|
1385 | #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
---|
1386 | #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
---|
1387 |
|
---|
1388 | /* TPI DEVID Register Definitions */
|
---|
1389 | #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
---|
1390 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
|
---|
1391 |
|
---|
1392 | #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
|
---|
1393 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
|
---|
1394 |
|
---|
1395 | #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
|
---|
1396 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
|
---|
1397 |
|
---|
1398 | #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
|
---|
1399 | #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
|
---|
1400 |
|
---|
1401 | #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
|
---|
1402 | #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
|
---|
1403 |
|
---|
1404 | #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
|
---|
1405 | #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
---|
1406 |
|
---|
1407 | /* TPI DEVTYPE Register Definitions */
|
---|
1408 | #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
|
---|
1409 | #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
---|
1410 |
|
---|
1411 | #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
|
---|
1412 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
---|
1413 |
|
---|
1414 | /*@}*/ /* end of group CMSIS_TPI */
|
---|
1415 |
|
---|
1416 |
|
---|
1417 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
---|
1418 | /**
|
---|
1419 | \ingroup CMSIS_core_register
|
---|
1420 | \defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
---|
1421 | \brief Type definitions for the Memory Protection Unit (MPU)
|
---|
1422 | @{
|
---|
1423 | */
|
---|
1424 |
|
---|
1425 | /**
|
---|
1426 | \brief Structure type to access the Memory Protection Unit (MPU).
|
---|
1427 | */
|
---|
1428 | typedef struct
|
---|
1429 | {
|
---|
1430 | __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
---|
1431 | __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
---|
1432 | __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
---|
1433 | __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
---|
1434 | __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
---|
1435 | __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
|
---|
1436 | __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
|
---|
1437 | __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
|
---|
1438 | __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
|
---|
1439 | __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
|
---|
1440 | __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
---|
1441 | } MPU_Type;
|
---|
1442 |
|
---|
1443 | #define MPU_TYPE_RALIASES 4U
|
---|
1444 |
|
---|
1445 | /* MPU Type Register Definitions */
|
---|
1446 | #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
---|
1447 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
---|
1448 |
|
---|
1449 | #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
|
---|
1450 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
---|
1451 |
|
---|
1452 | #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
---|
1453 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
---|
1454 |
|
---|
1455 | /* MPU Control Register Definitions */
|
---|
1456 | #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
---|
1457 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
---|
1458 |
|
---|
1459 | #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
|
---|
1460 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
---|
1461 |
|
---|
1462 | #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
---|
1463 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
---|
1464 |
|
---|
1465 | /* MPU Region Number Register Definitions */
|
---|
1466 | #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
---|
1467 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
---|
1468 |
|
---|
1469 | /* MPU Region Base Address Register Definitions */
|
---|
1470 | #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
|
---|
1471 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
---|
1472 |
|
---|
1473 | #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
|
---|
1474 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
---|
1475 |
|
---|
1476 | #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
---|
1477 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
---|
1478 |
|
---|
1479 | /* MPU Region Attribute and Size Register Definitions */
|
---|
1480 | #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
---|
1481 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
---|
1482 |
|
---|
1483 | #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
|
---|
1484 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
---|
1485 |
|
---|
1486 | #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
|
---|
1487 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
---|
1488 |
|
---|
1489 | #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
|
---|
1490 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
---|
1491 |
|
---|
1492 | #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
|
---|
1493 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
---|
1494 |
|
---|
1495 | #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
|
---|
1496 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
---|
1497 |
|
---|
1498 | #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
|
---|
1499 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
---|
1500 |
|
---|
1501 | #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
|
---|
1502 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
---|
1503 |
|
---|
1504 | #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
|
---|
1505 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
---|
1506 |
|
---|
1507 | #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
|
---|
1508 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
---|
1509 |
|
---|
1510 | /*@} end of group CMSIS_MPU */
|
---|
1511 | #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
|
---|
1512 |
|
---|
1513 |
|
---|
1514 | /**
|
---|
1515 | \ingroup CMSIS_core_register
|
---|
1516 | \defgroup CMSIS_FPU Floating Point Unit (FPU)
|
---|
1517 | \brief Type definitions for the Floating Point Unit (FPU)
|
---|
1518 | @{
|
---|
1519 | */
|
---|
1520 |
|
---|
1521 | /**
|
---|
1522 | \brief Structure type to access the Floating Point Unit (FPU).
|
---|
1523 | */
|
---|
1524 | typedef struct
|
---|
1525 | {
|
---|
1526 | uint32_t RESERVED0[1U];
|
---|
1527 | __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
|
---|
1528 | __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
|
---|
1529 | __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
|
---|
1530 | __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
|
---|
1531 | __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
|
---|
1532 | __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
|
---|
1533 | } FPU_Type;
|
---|
1534 |
|
---|
1535 | /* Floating-Point Context Control Register Definitions */
|
---|
1536 | #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
|
---|
1537 | #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
|
---|
1538 |
|
---|
1539 | #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
|
---|
1540 | #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
|
---|
1541 |
|
---|
1542 | #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
|
---|
1543 | #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
|
---|
1544 |
|
---|
1545 | #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
|
---|
1546 | #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
|
---|
1547 |
|
---|
1548 | #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
|
---|
1549 | #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
|
---|
1550 |
|
---|
1551 | #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
|
---|
1552 | #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
|
---|
1553 |
|
---|
1554 | #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
|
---|
1555 | #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
|
---|
1556 |
|
---|
1557 | #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
|
---|
1558 | #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
|
---|
1559 |
|
---|
1560 | #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
|
---|
1561 | #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
|
---|
1562 |
|
---|
1563 | /* Floating-Point Context Address Register Definitions */
|
---|
1564 | #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
|
---|
1565 | #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
|
---|
1566 |
|
---|
1567 | /* Floating-Point Default Status Control Register Definitions */
|
---|
1568 | #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
|
---|
1569 | #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
|
---|
1570 |
|
---|
1571 | #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
|
---|
1572 | #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
|
---|
1573 |
|
---|
1574 | #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
|
---|
1575 | #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
|
---|
1576 |
|
---|
1577 | #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
|
---|
1578 | #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
|
---|
1579 |
|
---|
1580 | /* Media and FP Feature Register 0 Definitions */
|
---|
1581 | #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
|
---|
1582 | #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
|
---|
1583 |
|
---|
1584 | #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
|
---|
1585 | #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
|
---|
1586 |
|
---|
1587 | #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
|
---|
1588 | #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
|
---|
1589 |
|
---|
1590 | #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
|
---|
1591 | #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
|
---|
1592 |
|
---|
1593 | #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
|
---|
1594 | #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
|
---|
1595 |
|
---|
1596 | #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
|
---|
1597 | #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
|
---|
1598 |
|
---|
1599 | #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
|
---|
1600 | #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
|
---|
1601 |
|
---|
1602 | #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
|
---|
1603 | #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
|
---|
1604 |
|
---|
1605 | /* Media and FP Feature Register 1 Definitions */
|
---|
1606 | #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
|
---|
1607 | #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
|
---|
1608 |
|
---|
1609 | #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
|
---|
1610 | #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
|
---|
1611 |
|
---|
1612 | #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
|
---|
1613 | #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
|
---|
1614 |
|
---|
1615 | #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
|
---|
1616 | #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
|
---|
1617 |
|
---|
1618 | /* Media and FP Feature Register 2 Definitions */
|
---|
1619 |
|
---|
1620 | /*@} end of group CMSIS_FPU */
|
---|
1621 |
|
---|
1622 |
|
---|
1623 | /**
|
---|
1624 | \ingroup CMSIS_core_register
|
---|
1625 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
---|
1626 | \brief Type definitions for the Core Debug Registers
|
---|
1627 | @{
|
---|
1628 | */
|
---|
1629 |
|
---|
1630 | /**
|
---|
1631 | \brief Structure type to access the Core Debug Register (CoreDebug).
|
---|
1632 | */
|
---|
1633 | typedef struct
|
---|
1634 | {
|
---|
1635 | __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
|
---|
1636 | __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
|
---|
1637 | __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
|
---|
1638 | __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
|
---|
1639 | } CoreDebug_Type;
|
---|
1640 |
|
---|
1641 | /* Debug Halting Control and Status Register Definitions */
|
---|
1642 | #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
|
---|
1643 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
|
---|
1644 |
|
---|
1645 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
|
---|
1646 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
|
---|
1647 |
|
---|
1648 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
|
---|
1649 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
|
---|
1650 |
|
---|
1651 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
|
---|
1652 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
|
---|
1653 |
|
---|
1654 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
|
---|
1655 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
|
---|
1656 |
|
---|
1657 | #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
|
---|
1658 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
|
---|
1659 |
|
---|
1660 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
|
---|
1661 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
|
---|
1662 |
|
---|
1663 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
|
---|
1664 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
|
---|
1665 |
|
---|
1666 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
|
---|
1667 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
|
---|
1668 |
|
---|
1669 | #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
|
---|
1670 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
|
---|
1671 |
|
---|
1672 | #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
|
---|
1673 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
|
---|
1674 |
|
---|
1675 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
|
---|
1676 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
|
---|
1677 |
|
---|
1678 | /* Debug Core Register Selector Register Definitions */
|
---|
1679 | #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
|
---|
1680 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
|
---|
1681 |
|
---|
1682 | #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
|
---|
1683 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
|
---|
1684 |
|
---|
1685 | /* Debug Exception and Monitor Control Register Definitions */
|
---|
1686 | #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
|
---|
1687 | #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
|
---|
1688 |
|
---|
1689 | #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
|
---|
1690 | #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
|
---|
1691 |
|
---|
1692 | #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
|
---|
1693 | #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
|
---|
1694 |
|
---|
1695 | #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
|
---|
1696 | #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
|
---|
1697 |
|
---|
1698 | #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
|
---|
1699 | #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
|
---|
1700 |
|
---|
1701 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
|
---|
1702 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
|
---|
1703 |
|
---|
1704 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
|
---|
1705 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
|
---|
1706 |
|
---|
1707 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
|
---|
1708 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
|
---|
1709 |
|
---|
1710 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
|
---|
1711 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
|
---|
1712 |
|
---|
1713 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
|
---|
1714 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
|
---|
1715 |
|
---|
1716 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
|
---|
1717 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
|
---|
1718 |
|
---|
1719 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
|
---|
1720 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
|
---|
1721 |
|
---|
1722 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
|
---|
1723 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
|
---|
1724 |
|
---|
1725 | /*@} end of group CMSIS_CoreDebug */
|
---|
1726 |
|
---|
1727 |
|
---|
1728 | /**
|
---|
1729 | \ingroup CMSIS_core_register
|
---|
1730 | \defgroup CMSIS_core_bitfield Core register bit field macros
|
---|
1731 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
---|
1732 | @{
|
---|
1733 | */
|
---|
1734 |
|
---|
1735 | /**
|
---|
1736 | \brief Mask and shift a bit field value for use in a register bit range.
|
---|
1737 | \param[in] field Name of the register bit field.
|
---|
1738 | \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
---|
1739 | \return Masked and shifted value.
|
---|
1740 | */
|
---|
1741 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
---|
1742 |
|
---|
1743 | /**
|
---|
1744 | \brief Mask and shift a register value to extract a bit filed value.
|
---|
1745 | \param[in] field Name of the register bit field.
|
---|
1746 | \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
---|
1747 | \return Masked and shifted bit field value.
|
---|
1748 | */
|
---|
1749 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
---|
1750 |
|
---|
1751 | /*@} end of group CMSIS_core_bitfield */
|
---|
1752 |
|
---|
1753 |
|
---|
1754 | /**
|
---|
1755 | \ingroup CMSIS_core_register
|
---|
1756 | \defgroup CMSIS_core_base Core Definitions
|
---|
1757 | \brief Definitions for base addresses, unions, and structures.
|
---|
1758 | @{
|
---|
1759 | */
|
---|
1760 |
|
---|
1761 | /* Memory mapping of Core Hardware */
|
---|
1762 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
---|
1763 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
---|
1764 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
---|
1765 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
|
---|
1766 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
|
---|
1767 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
---|
1768 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
---|
1769 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
---|
1770 |
|
---|
1771 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
---|
1772 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
---|
1773 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
---|
1774 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
---|
1775 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
|
---|
1776 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
|
---|
1777 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
---|
1778 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
---|
1779 |
|
---|
1780 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
---|
1781 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
---|
1782 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
---|
1783 | #endif
|
---|
1784 |
|
---|
1785 | #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
---|
1786 | #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
---|
1787 |
|
---|
1788 | /*@} */
|
---|
1789 |
|
---|
1790 |
|
---|
1791 |
|
---|
1792 | /*******************************************************************************
|
---|
1793 | * Hardware Abstraction Layer
|
---|
1794 | Core Function Interface contains:
|
---|
1795 | - Core NVIC Functions
|
---|
1796 | - Core SysTick Functions
|
---|
1797 | - Core Debug Functions
|
---|
1798 | - Core Register Access Functions
|
---|
1799 | ******************************************************************************/
|
---|
1800 | /**
|
---|
1801 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
---|
1802 | */
|
---|
1803 |
|
---|
1804 |
|
---|
1805 |
|
---|
1806 | /* ########################## NVIC functions #################################### */
|
---|
1807 | /**
|
---|
1808 | \ingroup CMSIS_Core_FunctionInterface
|
---|
1809 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
---|
1810 | \brief Functions that manage interrupts and exceptions via the NVIC.
|
---|
1811 | @{
|
---|
1812 | */
|
---|
1813 |
|
---|
1814 | #ifdef CMSIS_NVIC_VIRTUAL
|
---|
1815 | #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
---|
1816 | #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
---|
1817 | #endif
|
---|
1818 | #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
---|
1819 | #else
|
---|
1820 | #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
---|
1821 | #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
---|
1822 | #define NVIC_EnableIRQ __NVIC_EnableIRQ
|
---|
1823 | #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
---|
1824 | #define NVIC_DisableIRQ __NVIC_DisableIRQ
|
---|
1825 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
---|
1826 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
---|
1827 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
---|
1828 | #define NVIC_GetActive __NVIC_GetActive
|
---|
1829 | #define NVIC_SetPriority __NVIC_SetPriority
|
---|
1830 | #define NVIC_GetPriority __NVIC_GetPriority
|
---|
1831 | #define NVIC_SystemReset __NVIC_SystemReset
|
---|
1832 | #endif /* CMSIS_NVIC_VIRTUAL */
|
---|
1833 |
|
---|
1834 | #ifdef CMSIS_VECTAB_VIRTUAL
|
---|
1835 | #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
---|
1836 | #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
---|
1837 | #endif
|
---|
1838 | #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
---|
1839 | #else
|
---|
1840 | #define NVIC_SetVector __NVIC_SetVector
|
---|
1841 | #define NVIC_GetVector __NVIC_GetVector
|
---|
1842 | #endif /* (CMSIS_VECTAB_VIRTUAL) */
|
---|
1843 |
|
---|
1844 | #define NVIC_USER_IRQ_OFFSET 16
|
---|
1845 |
|
---|
1846 |
|
---|
1847 | /* The following EXC_RETURN values are saved the LR on exception entry */
|
---|
1848 | #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
---|
1849 | #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
---|
1850 | #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
---|
1851 | #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
|
---|
1852 | #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
|
---|
1853 | #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
|
---|
1854 |
|
---|
1855 |
|
---|
1856 | /**
|
---|
1857 | \brief Set Priority Grouping
|
---|
1858 | \details Sets the priority grouping field using the required unlock sequence.
|
---|
1859 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
|
---|
1860 | Only values from 0..7 are used.
|
---|
1861 | In case of a conflict between priority grouping and available
|
---|
1862 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
---|
1863 | \param [in] PriorityGroup Priority grouping field.
|
---|
1864 | */
|
---|
1865 | __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
---|
1866 | {
|
---|
1867 | uint32_t reg_value;
|
---|
1868 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
---|
1869 |
|
---|
1870 | reg_value = SCB->AIRCR; /* read old register configuration */
|
---|
1871 | reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
---|
1872 | reg_value = (reg_value |
|
---|
1873 | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
---|
1874 | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
---|
1875 | SCB->AIRCR = reg_value;
|
---|
1876 | }
|
---|
1877 |
|
---|
1878 |
|
---|
1879 | /**
|
---|
1880 | \brief Get Priority Grouping
|
---|
1881 | \details Reads the priority grouping field from the NVIC Interrupt Controller.
|
---|
1882 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
---|
1883 | */
|
---|
1884 | __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
---|
1885 | {
|
---|
1886 | return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
---|
1887 | }
|
---|
1888 |
|
---|
1889 |
|
---|
1890 | /**
|
---|
1891 | \brief Enable Interrupt
|
---|
1892 | \details Enables a device specific interrupt in the NVIC interrupt controller.
|
---|
1893 | \param [in] IRQn Device specific interrupt number.
|
---|
1894 | \note IRQn must not be negative.
|
---|
1895 | */
|
---|
1896 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
---|
1897 | {
|
---|
1898 | if ((int32_t)(IRQn) >= 0)
|
---|
1899 | {
|
---|
1900 | NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
---|
1901 | }
|
---|
1902 | }
|
---|
1903 |
|
---|
1904 |
|
---|
1905 | /**
|
---|
1906 | \brief Get Interrupt Enable status
|
---|
1907 | \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
---|
1908 | \param [in] IRQn Device specific interrupt number.
|
---|
1909 | \return 0 Interrupt is not enabled.
|
---|
1910 | \return 1 Interrupt is enabled.
|
---|
1911 | \note IRQn must not be negative.
|
---|
1912 | */
|
---|
1913 | __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
---|
1914 | {
|
---|
1915 | if ((int32_t)(IRQn) >= 0)
|
---|
1916 | {
|
---|
1917 | return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
---|
1918 | }
|
---|
1919 | else
|
---|
1920 | {
|
---|
1921 | return(0U);
|
---|
1922 | }
|
---|
1923 | }
|
---|
1924 |
|
---|
1925 |
|
---|
1926 | /**
|
---|
1927 | \brief Disable Interrupt
|
---|
1928 | \details Disables a device specific interrupt in the NVIC interrupt controller.
|
---|
1929 | \param [in] IRQn Device specific interrupt number.
|
---|
1930 | \note IRQn must not be negative.
|
---|
1931 | */
|
---|
1932 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
---|
1933 | {
|
---|
1934 | if ((int32_t)(IRQn) >= 0)
|
---|
1935 | {
|
---|
1936 | NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
---|
1937 | __DSB();
|
---|
1938 | __ISB();
|
---|
1939 | }
|
---|
1940 | }
|
---|
1941 |
|
---|
1942 |
|
---|
1943 | /**
|
---|
1944 | \brief Get Pending Interrupt
|
---|
1945 | \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
---|
1946 | \param [in] IRQn Device specific interrupt number.
|
---|
1947 | \return 0 Interrupt status is not pending.
|
---|
1948 | \return 1 Interrupt status is pending.
|
---|
1949 | \note IRQn must not be negative.
|
---|
1950 | */
|
---|
1951 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
---|
1952 | {
|
---|
1953 | if ((int32_t)(IRQn) >= 0)
|
---|
1954 | {
|
---|
1955 | return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
---|
1956 | }
|
---|
1957 | else
|
---|
1958 | {
|
---|
1959 | return(0U);
|
---|
1960 | }
|
---|
1961 | }
|
---|
1962 |
|
---|
1963 |
|
---|
1964 | /**
|
---|
1965 | \brief Set Pending Interrupt
|
---|
1966 | \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
---|
1967 | \param [in] IRQn Device specific interrupt number.
|
---|
1968 | \note IRQn must not be negative.
|
---|
1969 | */
|
---|
1970 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
---|
1971 | {
|
---|
1972 | if ((int32_t)(IRQn) >= 0)
|
---|
1973 | {
|
---|
1974 | NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
---|
1975 | }
|
---|
1976 | }
|
---|
1977 |
|
---|
1978 |
|
---|
1979 | /**
|
---|
1980 | \brief Clear Pending Interrupt
|
---|
1981 | \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
---|
1982 | \param [in] IRQn Device specific interrupt number.
|
---|
1983 | \note IRQn must not be negative.
|
---|
1984 | */
|
---|
1985 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
---|
1986 | {
|
---|
1987 | if ((int32_t)(IRQn) >= 0)
|
---|
1988 | {
|
---|
1989 | NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
---|
1990 | }
|
---|
1991 | }
|
---|
1992 |
|
---|
1993 |
|
---|
1994 | /**
|
---|
1995 | \brief Get Active Interrupt
|
---|
1996 | \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
|
---|
1997 | \param [in] IRQn Device specific interrupt number.
|
---|
1998 | \return 0 Interrupt status is not active.
|
---|
1999 | \return 1 Interrupt status is active.
|
---|
2000 | \note IRQn must not be negative.
|
---|
2001 | */
|
---|
2002 | __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
---|
2003 | {
|
---|
2004 | if ((int32_t)(IRQn) >= 0)
|
---|
2005 | {
|
---|
2006 | return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
---|
2007 | }
|
---|
2008 | else
|
---|
2009 | {
|
---|
2010 | return(0U);
|
---|
2011 | }
|
---|
2012 | }
|
---|
2013 |
|
---|
2014 |
|
---|
2015 | /**
|
---|
2016 | \brief Set Interrupt Priority
|
---|
2017 | \details Sets the priority of a device specific interrupt or a processor exception.
|
---|
2018 | The interrupt number can be positive to specify a device specific interrupt,
|
---|
2019 | or negative to specify a processor exception.
|
---|
2020 | \param [in] IRQn Interrupt number.
|
---|
2021 | \param [in] priority Priority to set.
|
---|
2022 | \note The priority cannot be set for every processor exception.
|
---|
2023 | */
|
---|
2024 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
---|
2025 | {
|
---|
2026 | if ((int32_t)(IRQn) >= 0)
|
---|
2027 | {
|
---|
2028 | NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
---|
2029 | }
|
---|
2030 | else
|
---|
2031 | {
|
---|
2032 | SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
---|
2033 | }
|
---|
2034 | }
|
---|
2035 |
|
---|
2036 |
|
---|
2037 | /**
|
---|
2038 | \brief Get Interrupt Priority
|
---|
2039 | \details Reads the priority of a device specific interrupt or a processor exception.
|
---|
2040 | The interrupt number can be positive to specify a device specific interrupt,
|
---|
2041 | or negative to specify a processor exception.
|
---|
2042 | \param [in] IRQn Interrupt number.
|
---|
2043 | \return Interrupt Priority.
|
---|
2044 | Value is aligned automatically to the implemented priority bits of the microcontroller.
|
---|
2045 | */
|
---|
2046 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
---|
2047 | {
|
---|
2048 |
|
---|
2049 | if ((int32_t)(IRQn) >= 0)
|
---|
2050 | {
|
---|
2051 | return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
---|
2052 | }
|
---|
2053 | else
|
---|
2054 | {
|
---|
2055 | return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
---|
2056 | }
|
---|
2057 | }
|
---|
2058 |
|
---|
2059 |
|
---|
2060 | /**
|
---|
2061 | \brief Encode Priority
|
---|
2062 | \details Encodes the priority for an interrupt with the given priority group,
|
---|
2063 | preemptive priority value, and subpriority value.
|
---|
2064 | In case of a conflict between priority grouping and available
|
---|
2065 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
---|
2066 | \param [in] PriorityGroup Used priority group.
|
---|
2067 | \param [in] PreemptPriority Preemptive priority value (starting from 0).
|
---|
2068 | \param [in] SubPriority Subpriority value (starting from 0).
|
---|
2069 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
---|
2070 | */
|
---|
2071 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
---|
2072 | {
|
---|
2073 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
---|
2074 | uint32_t PreemptPriorityBits;
|
---|
2075 | uint32_t SubPriorityBits;
|
---|
2076 |
|
---|
2077 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
---|
2078 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
---|
2079 |
|
---|
2080 | return (
|
---|
2081 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
---|
2082 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
---|
2083 | );
|
---|
2084 | }
|
---|
2085 |
|
---|
2086 |
|
---|
2087 | /**
|
---|
2088 | \brief Decode Priority
|
---|
2089 | \details Decodes an interrupt priority value with a given priority group to
|
---|
2090 | preemptive priority value and subpriority value.
|
---|
2091 | In case of a conflict between priority grouping and available
|
---|
2092 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
---|
2093 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
---|
2094 | \param [in] PriorityGroup Used priority group.
|
---|
2095 | \param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
---|
2096 | \param [out] pSubPriority Subpriority value (starting from 0).
|
---|
2097 | */
|
---|
2098 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
---|
2099 | {
|
---|
2100 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
---|
2101 | uint32_t PreemptPriorityBits;
|
---|
2102 | uint32_t SubPriorityBits;
|
---|
2103 |
|
---|
2104 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
---|
2105 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
---|
2106 |
|
---|
2107 | *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
---|
2108 | *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
---|
2109 | }
|
---|
2110 |
|
---|
2111 |
|
---|
2112 | /**
|
---|
2113 | \brief Set Interrupt Vector
|
---|
2114 | \details Sets an interrupt vector in SRAM based interrupt vector table.
|
---|
2115 | The interrupt number can be positive to specify a device specific interrupt,
|
---|
2116 | or negative to specify a processor exception.
|
---|
2117 | VTOR must been relocated to SRAM before.
|
---|
2118 | \param [in] IRQn Interrupt number
|
---|
2119 | \param [in] vector Address of interrupt handler function
|
---|
2120 | */
|
---|
2121 | __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
---|
2122 | {
|
---|
2123 | uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
---|
2124 | vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
---|
2125 | }
|
---|
2126 |
|
---|
2127 |
|
---|
2128 | /**
|
---|
2129 | \brief Get Interrupt Vector
|
---|
2130 | \details Reads an interrupt vector from interrupt vector table.
|
---|
2131 | The interrupt number can be positive to specify a device specific interrupt,
|
---|
2132 | or negative to specify a processor exception.
|
---|
2133 | \param [in] IRQn Interrupt number.
|
---|
2134 | \return Address of interrupt handler function
|
---|
2135 | */
|
---|
2136 | __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
---|
2137 | {
|
---|
2138 | uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
---|
2139 | return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
---|
2140 | }
|
---|
2141 |
|
---|
2142 |
|
---|
2143 | /**
|
---|
2144 | \brief System Reset
|
---|
2145 | \details Initiates a system reset request to reset the MCU.
|
---|
2146 | */
|
---|
2147 | __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
---|
2148 | {
|
---|
2149 | __DSB(); /* Ensure all outstanding memory accesses included
|
---|
2150 | buffered write are completed before reset */
|
---|
2151 | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
---|
2152 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
---|
2153 | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
|
---|
2154 | __DSB(); /* Ensure completion of memory access */
|
---|
2155 |
|
---|
2156 | for(;;) /* wait until reset */
|
---|
2157 | {
|
---|
2158 | __NOP();
|
---|
2159 | }
|
---|
2160 | }
|
---|
2161 |
|
---|
2162 | /*@} end of CMSIS_Core_NVICFunctions */
|
---|
2163 |
|
---|
2164 | /* ########################## MPU functions #################################### */
|
---|
2165 |
|
---|
2166 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
---|
2167 |
|
---|
2168 | #include "mpu_armv7.h"
|
---|
2169 |
|
---|
2170 | #endif
|
---|
2171 |
|
---|
2172 | /* ########################## FPU functions #################################### */
|
---|
2173 | /**
|
---|
2174 | \ingroup CMSIS_Core_FunctionInterface
|
---|
2175 | \defgroup CMSIS_Core_FpuFunctions FPU Functions
|
---|
2176 | \brief Function that provides FPU type.
|
---|
2177 | @{
|
---|
2178 | */
|
---|
2179 |
|
---|
2180 | /**
|
---|
2181 | \brief get FPU type
|
---|
2182 | \details returns the FPU type
|
---|
2183 | \returns
|
---|
2184 | - \b 0: No FPU
|
---|
2185 | - \b 1: Single precision FPU
|
---|
2186 | - \b 2: Double + Single precision FPU
|
---|
2187 | */
|
---|
2188 | __STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
---|
2189 | {
|
---|
2190 | uint32_t mvfr0;
|
---|
2191 |
|
---|
2192 | mvfr0 = SCB->MVFR0;
|
---|
2193 | if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
|
---|
2194 | {
|
---|
2195 | return 2U; /* Double + Single precision FPU */
|
---|
2196 | }
|
---|
2197 | else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
|
---|
2198 | {
|
---|
2199 | return 1U; /* Single precision FPU */
|
---|
2200 | }
|
---|
2201 | else
|
---|
2202 | {
|
---|
2203 | return 0U; /* No FPU */
|
---|
2204 | }
|
---|
2205 | }
|
---|
2206 |
|
---|
2207 |
|
---|
2208 | /*@} end of CMSIS_Core_FpuFunctions */
|
---|
2209 |
|
---|
2210 |
|
---|
2211 |
|
---|
2212 | /* ########################## Cache functions #################################### */
|
---|
2213 | /**
|
---|
2214 | \ingroup CMSIS_Core_FunctionInterface
|
---|
2215 | \defgroup CMSIS_Core_CacheFunctions Cache Functions
|
---|
2216 | \brief Functions that configure Instruction and Data cache.
|
---|
2217 | @{
|
---|
2218 | */
|
---|
2219 |
|
---|
2220 | /* Cache Size ID Register Macros */
|
---|
2221 | #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
|
---|
2222 | #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
|
---|
2223 |
|
---|
2224 |
|
---|
2225 | /**
|
---|
2226 | \brief Enable I-Cache
|
---|
2227 | \details Turns on I-Cache
|
---|
2228 | */
|
---|
2229 | __STATIC_INLINE void SCB_EnableICache (void)
|
---|
2230 | {
|
---|
2231 | #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
---|
2232 | __DSB();
|
---|
2233 | __ISB();
|
---|
2234 | SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
---|
2235 | __DSB();
|
---|
2236 | __ISB();
|
---|
2237 | SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
|
---|
2238 | __DSB();
|
---|
2239 | __ISB();
|
---|
2240 | #endif
|
---|
2241 | }
|
---|
2242 |
|
---|
2243 |
|
---|
2244 | /**
|
---|
2245 | \brief Disable I-Cache
|
---|
2246 | \details Turns off I-Cache
|
---|
2247 | */
|
---|
2248 | __STATIC_INLINE void SCB_DisableICache (void)
|
---|
2249 | {
|
---|
2250 | #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
---|
2251 | __DSB();
|
---|
2252 | __ISB();
|
---|
2253 | SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
|
---|
2254 | SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
---|
2255 | __DSB();
|
---|
2256 | __ISB();
|
---|
2257 | #endif
|
---|
2258 | }
|
---|
2259 |
|
---|
2260 |
|
---|
2261 | /**
|
---|
2262 | \brief Invalidate I-Cache
|
---|
2263 | \details Invalidates I-Cache
|
---|
2264 | */
|
---|
2265 | __STATIC_INLINE void SCB_InvalidateICache (void)
|
---|
2266 | {
|
---|
2267 | #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
---|
2268 | __DSB();
|
---|
2269 | __ISB();
|
---|
2270 | SCB->ICIALLU = 0UL;
|
---|
2271 | __DSB();
|
---|
2272 | __ISB();
|
---|
2273 | #endif
|
---|
2274 | }
|
---|
2275 |
|
---|
2276 |
|
---|
2277 | /**
|
---|
2278 | \brief Enable D-Cache
|
---|
2279 | \details Turns on D-Cache
|
---|
2280 | */
|
---|
2281 | __STATIC_INLINE void SCB_EnableDCache (void)
|
---|
2282 | {
|
---|
2283 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
---|
2284 | uint32_t ccsidr;
|
---|
2285 | uint32_t sets;
|
---|
2286 | uint32_t ways;
|
---|
2287 |
|
---|
2288 | SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
---|
2289 | __DSB();
|
---|
2290 |
|
---|
2291 | ccsidr = SCB->CCSIDR;
|
---|
2292 |
|
---|
2293 | /* invalidate D-Cache */
|
---|
2294 | sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
---|
2295 | do {
|
---|
2296 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
---|
2297 | do {
|
---|
2298 | SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
---|
2299 | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
---|
2300 | #if defined ( __CC_ARM )
|
---|
2301 | __schedule_barrier();
|
---|
2302 | #endif
|
---|
2303 | } while (ways-- != 0U);
|
---|
2304 | } while(sets-- != 0U);
|
---|
2305 | __DSB();
|
---|
2306 |
|
---|
2307 | SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
|
---|
2308 |
|
---|
2309 | __DSB();
|
---|
2310 | __ISB();
|
---|
2311 | #endif
|
---|
2312 | }
|
---|
2313 |
|
---|
2314 |
|
---|
2315 | /**
|
---|
2316 | \brief Disable D-Cache
|
---|
2317 | \details Turns off D-Cache
|
---|
2318 | */
|
---|
2319 | __STATIC_INLINE void SCB_DisableDCache (void)
|
---|
2320 | {
|
---|
2321 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
---|
2322 | uint32_t ccsidr;
|
---|
2323 | uint32_t sets;
|
---|
2324 | uint32_t ways;
|
---|
2325 |
|
---|
2326 | SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
---|
2327 | __DSB();
|
---|
2328 |
|
---|
2329 | SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
---|
2330 | __DSB();
|
---|
2331 |
|
---|
2332 | ccsidr = SCB->CCSIDR;
|
---|
2333 |
|
---|
2334 | /* clean & invalidate D-Cache */
|
---|
2335 | sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
---|
2336 | do {
|
---|
2337 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
---|
2338 | do {
|
---|
2339 | SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
---|
2340 | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
---|
2341 | #if defined ( __CC_ARM )
|
---|
2342 | __schedule_barrier();
|
---|
2343 | #endif
|
---|
2344 | } while (ways-- != 0U);
|
---|
2345 | } while(sets-- != 0U);
|
---|
2346 |
|
---|
2347 | __DSB();
|
---|
2348 | __ISB();
|
---|
2349 | #endif
|
---|
2350 | }
|
---|
2351 |
|
---|
2352 |
|
---|
2353 | /**
|
---|
2354 | \brief Invalidate D-Cache
|
---|
2355 | \details Invalidates D-Cache
|
---|
2356 | */
|
---|
2357 | __STATIC_INLINE void SCB_InvalidateDCache (void)
|
---|
2358 | {
|
---|
2359 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
---|
2360 | uint32_t ccsidr;
|
---|
2361 | uint32_t sets;
|
---|
2362 | uint32_t ways;
|
---|
2363 |
|
---|
2364 | SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
---|
2365 | __DSB();
|
---|
2366 |
|
---|
2367 | ccsidr = SCB->CCSIDR;
|
---|
2368 |
|
---|
2369 | /* invalidate D-Cache */
|
---|
2370 | sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
---|
2371 | do {
|
---|
2372 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
---|
2373 | do {
|
---|
2374 | SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
---|
2375 | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
---|
2376 | #if defined ( __CC_ARM )
|
---|
2377 | __schedule_barrier();
|
---|
2378 | #endif
|
---|
2379 | } while (ways-- != 0U);
|
---|
2380 | } while(sets-- != 0U);
|
---|
2381 |
|
---|
2382 | __DSB();
|
---|
2383 | __ISB();
|
---|
2384 | #endif
|
---|
2385 | }
|
---|
2386 |
|
---|
2387 |
|
---|
2388 | /**
|
---|
2389 | \brief Clean D-Cache
|
---|
2390 | \details Cleans D-Cache
|
---|
2391 | */
|
---|
2392 | __STATIC_INLINE void SCB_CleanDCache (void)
|
---|
2393 | {
|
---|
2394 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
---|
2395 | uint32_t ccsidr;
|
---|
2396 | uint32_t sets;
|
---|
2397 | uint32_t ways;
|
---|
2398 |
|
---|
2399 | SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
---|
2400 | __DSB();
|
---|
2401 |
|
---|
2402 | ccsidr = SCB->CCSIDR;
|
---|
2403 |
|
---|
2404 | /* clean D-Cache */
|
---|
2405 | sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
---|
2406 | do {
|
---|
2407 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
---|
2408 | do {
|
---|
2409 | SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
|
---|
2410 | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
|
---|
2411 | #if defined ( __CC_ARM )
|
---|
2412 | __schedule_barrier();
|
---|
2413 | #endif
|
---|
2414 | } while (ways-- != 0U);
|
---|
2415 | } while(sets-- != 0U);
|
---|
2416 |
|
---|
2417 | __DSB();
|
---|
2418 | __ISB();
|
---|
2419 | #endif
|
---|
2420 | }
|
---|
2421 |
|
---|
2422 |
|
---|
2423 | /**
|
---|
2424 | \brief Clean & Invalidate D-Cache
|
---|
2425 | \details Cleans and Invalidates D-Cache
|
---|
2426 | */
|
---|
2427 | __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
|
---|
2428 | {
|
---|
2429 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
---|
2430 | uint32_t ccsidr;
|
---|
2431 | uint32_t sets;
|
---|
2432 | uint32_t ways;
|
---|
2433 |
|
---|
2434 | SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
---|
2435 | __DSB();
|
---|
2436 |
|
---|
2437 | ccsidr = SCB->CCSIDR;
|
---|
2438 |
|
---|
2439 | /* clean & invalidate D-Cache */
|
---|
2440 | sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
---|
2441 | do {
|
---|
2442 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
---|
2443 | do {
|
---|
2444 | SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
---|
2445 | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
---|
2446 | #if defined ( __CC_ARM )
|
---|
2447 | __schedule_barrier();
|
---|
2448 | #endif
|
---|
2449 | } while (ways-- != 0U);
|
---|
2450 | } while(sets-- != 0U);
|
---|
2451 |
|
---|
2452 | __DSB();
|
---|
2453 | __ISB();
|
---|
2454 | #endif
|
---|
2455 | }
|
---|
2456 |
|
---|
2457 |
|
---|
2458 | /**
|
---|
2459 | \brief D-Cache Invalidate by address
|
---|
2460 | \details Invalidates D-Cache for the given address
|
---|
2461 | \param[in] addr address (aligned to 32-byte boundary)
|
---|
2462 | \param[in] dsize size of memory block (in number of bytes)
|
---|
2463 | */
|
---|
2464 | __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
---|
2465 | {
|
---|
2466 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
---|
2467 | int32_t op_size = dsize;
|
---|
2468 | uint32_t op_addr = (uint32_t)addr;
|
---|
2469 | int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
|
---|
2470 |
|
---|
2471 | __DSB();
|
---|
2472 |
|
---|
2473 | while (op_size > 0) {
|
---|
2474 | SCB->DCIMVAC = op_addr;
|
---|
2475 | op_addr += (uint32_t)linesize;
|
---|
2476 | op_size -= linesize;
|
---|
2477 | }
|
---|
2478 |
|
---|
2479 | __DSB();
|
---|
2480 | __ISB();
|
---|
2481 | #endif
|
---|
2482 | }
|
---|
2483 |
|
---|
2484 |
|
---|
2485 | /**
|
---|
2486 | \brief D-Cache Clean by address
|
---|
2487 | \details Cleans D-Cache for the given address
|
---|
2488 | \param[in] addr address (aligned to 32-byte boundary)
|
---|
2489 | \param[in] dsize size of memory block (in number of bytes)
|
---|
2490 | */
|
---|
2491 | __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
---|
2492 | {
|
---|
2493 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
---|
2494 | int32_t op_size = dsize;
|
---|
2495 | uint32_t op_addr = (uint32_t) addr;
|
---|
2496 | int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
|
---|
2497 |
|
---|
2498 | __DSB();
|
---|
2499 |
|
---|
2500 | while (op_size > 0) {
|
---|
2501 | SCB->DCCMVAC = op_addr;
|
---|
2502 | op_addr += (uint32_t)linesize;
|
---|
2503 | op_size -= linesize;
|
---|
2504 | }
|
---|
2505 |
|
---|
2506 | __DSB();
|
---|
2507 | __ISB();
|
---|
2508 | #endif
|
---|
2509 | }
|
---|
2510 |
|
---|
2511 |
|
---|
2512 | /**
|
---|
2513 | \brief D-Cache Clean and Invalidate by address
|
---|
2514 | \details Cleans and invalidates D_Cache for the given address
|
---|
2515 | \param[in] addr address (aligned to 32-byte boundary)
|
---|
2516 | \param[in] dsize size of memory block (in number of bytes)
|
---|
2517 | */
|
---|
2518 | __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
---|
2519 | {
|
---|
2520 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
---|
2521 | int32_t op_size = dsize;
|
---|
2522 | uint32_t op_addr = (uint32_t) addr;
|
---|
2523 | int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
|
---|
2524 |
|
---|
2525 | __DSB();
|
---|
2526 |
|
---|
2527 | while (op_size > 0) {
|
---|
2528 | SCB->DCCIMVAC = op_addr;
|
---|
2529 | op_addr += (uint32_t)linesize;
|
---|
2530 | op_size -= linesize;
|
---|
2531 | }
|
---|
2532 |
|
---|
2533 | __DSB();
|
---|
2534 | __ISB();
|
---|
2535 | #endif
|
---|
2536 | }
|
---|
2537 |
|
---|
2538 |
|
---|
2539 | /*@} end of CMSIS_Core_CacheFunctions */
|
---|
2540 |
|
---|
2541 |
|
---|
2542 |
|
---|
2543 | /* ################################## SysTick function ############################################ */
|
---|
2544 | /**
|
---|
2545 | \ingroup CMSIS_Core_FunctionInterface
|
---|
2546 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
---|
2547 | \brief Functions that configure the System.
|
---|
2548 | @{
|
---|
2549 | */
|
---|
2550 |
|
---|
2551 | #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
---|
2552 |
|
---|
2553 | /**
|
---|
2554 | \brief System Tick Configuration
|
---|
2555 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
---|
2556 | Counter is in free running mode to generate periodic interrupts.
|
---|
2557 | \param [in] ticks Number of ticks between two interrupts.
|
---|
2558 | \return 0 Function succeeded.
|
---|
2559 | \return 1 Function failed.
|
---|
2560 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
---|
2561 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
---|
2562 | must contain a vendor-specific implementation of this function.
|
---|
2563 | */
|
---|
2564 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
---|
2565 | {
|
---|
2566 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
---|
2567 | {
|
---|
2568 | return (1UL); /* Reload value impossible */
|
---|
2569 | }
|
---|
2570 |
|
---|
2571 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
---|
2572 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
---|
2573 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
---|
2574 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
---|
2575 | SysTick_CTRL_TICKINT_Msk |
|
---|
2576 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
---|
2577 | return (0UL); /* Function successful */
|
---|
2578 | }
|
---|
2579 |
|
---|
2580 | #endif
|
---|
2581 |
|
---|
2582 | /*@} end of CMSIS_Core_SysTickFunctions */
|
---|
2583 |
|
---|
2584 |
|
---|
2585 |
|
---|
2586 | /* ##################################### Debug In/Output function ########################################### */
|
---|
2587 | /**
|
---|
2588 | \ingroup CMSIS_Core_FunctionInterface
|
---|
2589 | \defgroup CMSIS_core_DebugFunctions ITM Functions
|
---|
2590 | \brief Functions that access the ITM debug interface.
|
---|
2591 | @{
|
---|
2592 | */
|
---|
2593 |
|
---|
2594 | extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
---|
2595 | #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
---|
2596 |
|
---|
2597 |
|
---|
2598 | /**
|
---|
2599 | \brief ITM Send Character
|
---|
2600 | \details Transmits a character via the ITM channel 0, and
|
---|
2601 | \li Just returns when no debugger is connected that has booked the output.
|
---|
2602 | \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
|
---|
2603 | \param [in] ch Character to transmit.
|
---|
2604 | \returns Character to transmit.
|
---|
2605 | */
|
---|
2606 | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
---|
2607 | {
|
---|
2608 | if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
|
---|
2609 | ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
|
---|
2610 | {
|
---|
2611 | while (ITM->PORT[0U].u32 == 0UL)
|
---|
2612 | {
|
---|
2613 | __NOP();
|
---|
2614 | }
|
---|
2615 | ITM->PORT[0U].u8 = (uint8_t)ch;
|
---|
2616 | }
|
---|
2617 | return (ch);
|
---|
2618 | }
|
---|
2619 |
|
---|
2620 |
|
---|
2621 | /**
|
---|
2622 | \brief ITM Receive Character
|
---|
2623 | \details Inputs a character via the external variable \ref ITM_RxBuffer.
|
---|
2624 | \return Received character.
|
---|
2625 | \return -1 No character pending.
|
---|
2626 | */
|
---|
2627 | __STATIC_INLINE int32_t ITM_ReceiveChar (void)
|
---|
2628 | {
|
---|
2629 | int32_t ch = -1; /* no character available */
|
---|
2630 |
|
---|
2631 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
|
---|
2632 | {
|
---|
2633 | ch = ITM_RxBuffer;
|
---|
2634 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
|
---|
2635 | }
|
---|
2636 |
|
---|
2637 | return (ch);
|
---|
2638 | }
|
---|
2639 |
|
---|
2640 |
|
---|
2641 | /**
|
---|
2642 | \brief ITM Check Character
|
---|
2643 | \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
|
---|
2644 | \return 0 No character available.
|
---|
2645 | \return 1 Character available.
|
---|
2646 | */
|
---|
2647 | __STATIC_INLINE int32_t ITM_CheckChar (void)
|
---|
2648 | {
|
---|
2649 |
|
---|
2650 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
|
---|
2651 | {
|
---|
2652 | return (0); /* no character available */
|
---|
2653 | }
|
---|
2654 | else
|
---|
2655 | {
|
---|
2656 | return (1); /* character available */
|
---|
2657 | }
|
---|
2658 | }
|
---|
2659 |
|
---|
2660 | /*@} end of CMSIS_core_DebugFunctions */
|
---|
2661 |
|
---|
2662 |
|
---|
2663 |
|
---|
2664 |
|
---|
2665 | #ifdef __cplusplus
|
---|
2666 | }
|
---|
2667 | #endif
|
---|
2668 |
|
---|
2669 | #endif /* __CORE_CM7_H_DEPENDANT */
|
---|
2670 |
|
---|
2671 | #endif /* __CMSIS_GENERIC */
|
---|