1 | /******************************************************************************
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2 | * @file mpu_armv7.h
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3 | * @brief CMSIS MPU API for Armv7-M MPU
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4 | * @version V5.0.4
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5 | * @date 10. January 2018
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6 | ******************************************************************************/
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7 | /*
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8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
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9 | *
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10 | * SPDX-License-Identifier: Apache-2.0
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11 | *
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12 | * Licensed under the Apache License, Version 2.0 (the License); you may
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13 | * not use this file except in compliance with the License.
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14 | * You may obtain a copy of the License at
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15 | *
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16 | * www.apache.org/licenses/LICENSE-2.0
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17 | *
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18 | * Unless required by applicable law or agreed to in writing, software
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19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 | * See the License for the specific language governing permissions and
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22 | * limitations under the License.
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23 | */
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24 |
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25 | #if defined ( __ICCARM__ )
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26 | #pragma system_include /* treat file as system include file for MISRA check */
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27 | #elif defined (__clang__)
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28 | #pragma clang system_header /* treat file as system include file */
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29 | #endif
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30 |
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31 | #ifndef ARM_MPU_ARMV7_H
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32 | #define ARM_MPU_ARMV7_H
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33 |
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34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
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35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
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36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
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37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
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38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
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39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
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40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
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41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
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42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
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43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
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44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
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45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
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46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
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47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
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48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
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49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
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50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
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51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
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52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
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53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
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54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
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55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
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56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
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57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
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58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
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59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
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60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
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61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
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62 |
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63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
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64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
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65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
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66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
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67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
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68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
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69 |
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70 | /** MPU Region Base Address Register Value
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71 | *
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72 | * \param Region The region to be configured, number 0 to 15.
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73 | * \param BaseAddress The base address for the region.
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74 | */
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75 | #define ARM_MPU_RBAR(Region, BaseAddress) \
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76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
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77 | ((Region) & MPU_RBAR_REGION_Msk) | \
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78 | (MPU_RBAR_VALID_Msk))
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79 |
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80 | /**
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81 | * MPU Memory Access Attributes
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82 | *
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83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
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84 | * \param IsShareable Region is shareable between multiple bus masters.
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85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
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86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
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87 | */
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88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
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89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
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90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
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91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
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92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
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93 |
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94 | /**
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95 | * MPU Region Attribute and Size Register Value
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96 | *
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97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
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98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
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99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
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100 | * \param SubRegionDisable Sub-region disable field.
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101 | * \param Size Region size of the region to be configured, for example 4K, 8K.
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102 | */
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103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
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104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
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105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
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106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
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107 |
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108 | /**
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109 | * MPU Region Attribute and Size Register Value
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110 | *
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111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
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112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
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113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
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114 | * \param IsShareable Region is shareable between multiple bus masters.
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115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
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116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
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117 | * \param SubRegionDisable Sub-region disable field.
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118 | * \param Size Region size of the region to be configured, for example 4K, 8K.
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119 | */
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120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
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121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
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122 |
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123 | /**
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124 | * MPU Memory Access Attribute for strongly ordered memory.
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125 | * - TEX: 000b
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126 | * - Shareable
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127 | * - Non-cacheable
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128 | * - Non-bufferable
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129 | */
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130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
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131 |
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132 | /**
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133 | * MPU Memory Access Attribute for device memory.
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134 | * - TEX: 000b (if non-shareable) or 010b (if shareable)
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135 | * - Shareable or non-shareable
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136 | * - Non-cacheable
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137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable)
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138 | *
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139 | * \param IsShareable Configures the device memory as shareable or non-shareable.
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140 | */
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141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
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142 |
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143 | /**
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144 | * MPU Memory Access Attribute for normal memory.
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145 | * - TEX: 1BBb (reflecting outer cacheability rules)
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146 | * - Shareable or non-shareable
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147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules)
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148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules)
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149 | *
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150 | * \param OuterCp Configures the outer cache policy.
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151 | * \param InnerCp Configures the inner cache policy.
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152 | * \param IsShareable Configures the memory as shareable or non-shareable.
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153 | */
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154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
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155 |
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156 | /**
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157 | * MPU Memory Access Attribute non-cacheable policy.
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158 | */
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159 | #define ARM_MPU_CACHEP_NOCACHE 0U
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160 |
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161 | /**
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162 | * MPU Memory Access Attribute write-back, write and read allocate policy.
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163 | */
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164 | #define ARM_MPU_CACHEP_WB_WRA 1U
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165 |
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166 | /**
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167 | * MPU Memory Access Attribute write-through, no write allocate policy.
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168 | */
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169 | #define ARM_MPU_CACHEP_WT_NWA 2U
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170 |
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171 | /**
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172 | * MPU Memory Access Attribute write-back, no write allocate policy.
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173 | */
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174 | #define ARM_MPU_CACHEP_WB_NWA 3U
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175 |
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176 |
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177 | /**
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178 | * Struct for a single MPU Region
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179 | */
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180 | typedef struct {
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181 | uint32_t RBAR; //!< The region base address register value (RBAR)
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182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
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183 | } ARM_MPU_Region_t;
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184 |
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185 | /** Enable the MPU.
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186 | * \param MPU_Control Default access permissions for unconfigured regions.
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187 | */
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188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
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189 | {
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190 | __DSB();
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191 | __ISB();
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192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
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193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
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194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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195 | #endif
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196 | }
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197 |
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198 | /** Disable the MPU.
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199 | */
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200 | __STATIC_INLINE void ARM_MPU_Disable(void)
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201 | {
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202 | __DSB();
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203 | __ISB();
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204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
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205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
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206 | #endif
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207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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208 | }
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209 |
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210 | /** Clear and disable the given MPU region.
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211 | * \param rnr Region number to be cleared.
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212 | */
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213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
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214 | {
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215 | MPU->RNR = rnr;
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216 | MPU->RASR = 0U;
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217 | }
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218 |
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219 | /** Configure an MPU region.
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220 | * \param rbar Value for RBAR register.
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221 | * \param rsar Value for RSAR register.
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222 | */
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223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
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224 | {
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225 | MPU->RBAR = rbar;
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226 | MPU->RASR = rasr;
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227 | }
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228 |
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229 | /** Configure the given MPU region.
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230 | * \param rnr Region number to be configured.
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231 | * \param rbar Value for RBAR register.
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232 | * \param rsar Value for RSAR register.
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233 | */
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234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
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235 | {
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236 | MPU->RNR = rnr;
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237 | MPU->RBAR = rbar;
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238 | MPU->RASR = rasr;
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239 | }
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240 |
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241 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
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242 | * \param dst Destination data is copied to.
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243 | * \param src Source data is copied from.
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244 | * \param len Amount of data words to be copied.
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245 | */
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246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
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247 | {
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248 | uint32_t i;
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249 | for (i = 0U; i < len; ++i)
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250 | {
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251 | dst[i] = src[i];
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252 | }
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253 | }
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254 |
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255 | /** Load the given number of MPU regions from a table.
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256 | * \param table Pointer to the MPU configuration table.
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257 | * \param cnt Amount of regions to be configured.
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258 | */
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259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
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260 | {
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261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
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262 | while (cnt > MPU_TYPE_RALIASES) {
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263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
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264 | table += MPU_TYPE_RALIASES;
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265 | cnt -= MPU_TYPE_RALIASES;
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266 | }
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267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
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268 | }
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269 |
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270 | #endif
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