1 | /*
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2 | * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
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3 | *
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4 | * SPDX-License-Identifier: Apache-2.0
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5 | *
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6 | * Licensed under the Apache License, Version 2.0 (the License); you may
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7 | * not use this file except in compliance with the License.
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8 | * You may obtain a copy of the License at
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9 | *
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10 | * www.apache.org/licenses/LICENSE-2.0
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11 | *
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12 | * Unless required by applicable law or agreed to in writing, software
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13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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15 | * See the License for the specific language governing permissions and
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16 | * limitations under the License.
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17 | */
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18 |
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19 | /* ----------------------------------------------------------------------
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20 | * Project: CMSIS NN Library
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21 | * Title: arm_nnsupportfunctions.h
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22 | * Description: Public header file of support functions for CMSIS NN Library
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23 | *
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24 | * $Date: 13. July 2018
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25 | * $Revision: V.1.0.0
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26 | *
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27 | * Target Processor: Cortex-M cores
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28 | * -------------------------------------------------------------------- */
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29 |
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30 | #ifndef _ARM_NNSUPPORTFUNCTIONS_H_
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31 | #define _ARM_NNSUPPORTFUNCTIONS_H_
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32 |
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33 | #include "arm_math.h"
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34 | #include "arm_common_tables.h"
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35 | //#include <cstring>
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36 |
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37 | #ifdef __cplusplus
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38 | extern "C"
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39 | {
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40 | #endif
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41 |
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42 | /**
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43 | * @brief Union for SIMD access of Q31/Q15/Q7 types
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44 | */
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45 | union arm_nnword
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46 | {
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47 | q31_t word;
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48 | /**< Q31 type */
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49 | q15_t half_words[2];
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50 | /**< Q15 type */
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51 | q7_t bytes[4];
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52 | /**< Q7 type */
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53 | };
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54 |
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55 | /**
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56 | * @brief Struct for specifying activation function types
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57 | *
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58 | */
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59 | typedef enum
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60 | {
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61 | ARM_SIGMOID = 0,
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62 | /**< Sigmoid activation function */
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63 | ARM_TANH = 1,
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64 | /**< Tanh activation function */
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65 | } arm_nn_activation_type;
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66 |
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67 | /**
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68 | * @defgroup nndata_convert Neural Network Data Conversion Functions
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69 | *
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70 | * Perform data type conversion in-between neural network operations
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71 | *
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72 | */
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73 |
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74 | /**
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75 | * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift
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76 | * @param[in] *pSrc points to the Q7 input vector
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77 | * @param[out] *pDst points to the Q15 output vector
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78 | * @param[in] blockSize length of the input vector
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79 | * @return none.
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80 | *
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81 | */
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82 |
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83 | void arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize);
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84 |
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85 | /**
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86 | * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift
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87 | * @param[in] *pSrc points to the Q7 input vector
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88 | * @param[out] *pDst points to the Q15 output vector
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89 | * @param[in] blockSize length of the input vector
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90 | * @return none.
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91 | *
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92 | */
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93 |
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94 | void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize);
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95 |
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96 | #if defined (ARM_MATH_DSP)
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97 |
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98 | /**
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99 | * @brief read and expand one Q7 word into two Q15 words
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100 | */
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101 |
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102 | __STATIC_FORCEINLINE void *read_and_pad(void *source, q31_t * out1, q31_t * out2)
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103 | {
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104 | q31_t inA = *__SIMD32(source)++;
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105 | q31_t inAbuf1 = __SXTB16(__ROR(inA, 8));
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106 | q31_t inAbuf2 = __SXTB16(inA);
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107 |
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108 | #ifndef ARM_MATH_BIG_ENDIAN
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109 | *out2 = __PKHTB(inAbuf1, inAbuf2, 16);
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110 | *out1 = __PKHBT(inAbuf2, inAbuf1, 16);
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111 | #else
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112 | *out1 = __PKHTB(inAbuf1, inAbuf2, 16);
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113 | *out2 = __PKHBT(inAbuf2, inAbuf1, 16);
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114 | #endif
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115 |
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116 | return source;
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117 | }
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118 |
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119 | /**
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120 | * @brief read and expand one Q7 word into two Q15 words with reordering
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121 | */
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122 |
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123 | __STATIC_FORCEINLINE void *read_and_pad_reordered(void *source, q31_t * out1, q31_t * out2)
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124 | {
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125 | q31_t inA = *__SIMD32(source)++;
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126 | #ifndef ARM_MATH_BIG_ENDIAN
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127 | *out2 = __SXTB16(__ROR(inA, 8));
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128 | *out1 = __SXTB16(inA);
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129 | #else
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130 | *out1 = __SXTB16(__ROR(inA, 8));
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131 | *out2 = __SXTB16(inA);
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132 | #endif
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133 |
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134 | return source;
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135 | }
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136 | #endif
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137 |
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138 | /**
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139 | * @defgroup NNBasicMath Basic Math Functions for Neural Network Computation
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140 | *
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141 | * Basic Math Functions for Neural Network Computation
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142 | *
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143 | */
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144 |
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145 | /**
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146 | * @brief Q7 vector multiplication with variable output shifts
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147 | * @param[in] *pSrcA pointer to the first input vector
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148 | * @param[in] *pSrcB pointer to the second input vector
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149 | * @param[out] *pDst pointer to the output vector
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150 | * @param[in] out_shift amount of right-shift for output
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151 | * @param[in] blockSize number of samples in each vector
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152 | * @return none.
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153 | *
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154 | * <b>Scaling and Overflow Behavior:</b>
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155 | * \par
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156 | * The function uses saturating arithmetic.
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157 | * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
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158 | */
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159 |
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160 | void arm_nn_mult_q15(
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161 | q15_t * pSrcA,
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162 | q15_t * pSrcB,
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163 | q15_t * pDst,
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164 | const uint16_t out_shift,
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165 | uint32_t blockSize);
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166 |
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167 | /**
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168 | * @brief Q7 vector multiplication with variable output shifts
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169 | * @param[in] *pSrcA pointer to the first input vector
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170 | * @param[in] *pSrcB pointer to the second input vector
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171 | * @param[out] *pDst pointer to the output vector
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172 | * @param[in] out_shift amount of right-shift for output
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173 | * @param[in] blockSize number of samples in each vector
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174 | * @return none.
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175 | *
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176 | * <b>Scaling and Overflow Behavior:</b>
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177 | * \par
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178 | * The function uses saturating arithmetic.
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179 | * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
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180 | */
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181 |
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182 | void arm_nn_mult_q7(
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183 | q7_t * pSrcA,
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184 | q7_t * pSrcB,
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185 | q7_t * pDst,
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186 | const uint16_t out_shift,
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187 | uint32_t blockSize);
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188 |
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189 | /**
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190 | * @brief defition to adding rouding offset
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191 | */
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192 | #ifndef ARM_NN_TRUNCATE
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193 | #define NN_ROUND(out_shift) ( 0x1 << (out_shift - 1) )
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194 | #else
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195 | #define NN_ROUND(out_shift) 0
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196 | #endif
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197 |
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198 | #ifdef __cplusplus
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199 | }
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200 | #endif
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201 |
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202 | #endif
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