| 1 | /*
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| 2 | * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
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| 3 | *
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| 4 | * SPDX-License-Identifier: Apache-2.0
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| 5 | *
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| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may
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| 7 | * not use this file except in compliance with the License.
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| 8 | * You may obtain a copy of the License at
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| 9 | *
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| 10 | * www.apache.org/licenses/LICENSE-2.0
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| 11 | *
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| 12 | * Unless required by applicable law or agreed to in writing, software
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| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 15 | * See the License for the specific language governing permissions and
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| 16 | * limitations under the License.
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| 17 | */
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| 18 |
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| 19 | /* ----------------------------------------------------------------------
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| 20 | * Project: CMSIS NN Library
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| 21 | * Title: arm_relu_q15.c
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| 22 | * Description: Q15 version of ReLU
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| 23 | *
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| 24 | * $Date: 17. January 2018
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| 25 | * $Revision: V.1.0.0
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| 26 | *
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| 27 | * Target Processor: Cortex-M cores
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| 28 | *
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| 29 | * -------------------------------------------------------------------- */
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| 30 |
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| 31 | #include "arm_math.h"
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| 32 | #include "arm_nnfunctions.h"
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| 33 |
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| 34 | /**
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| 35 | * @ingroup groupNN
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| 36 | */
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| 37 |
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| 38 | /**
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| 39 | * @addtogroup Acti
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| 40 | * @{
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| 41 | */
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| 42 |
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| 43 | /**
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| 44 | * @brief Q15 RELU function
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| 45 | * @param[in,out] data pointer to input
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| 46 | * @param[in] size number of elements
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| 47 | * @return none.
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| 48 | *
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| 49 | * @details
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| 50 | *
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| 51 | * Optimized relu with QSUB instructions.
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| 52 | *
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| 53 | */
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| 54 |
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| 55 | void arm_relu_q15(q15_t * data, uint16_t size)
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| 56 | {
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| 57 |
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| 58 | #if defined (ARM_MATH_DSP)
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| 59 | /* Run the following code for Cortex-M4 and Cortex-M7 */
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| 60 |
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| 61 | uint16_t i = size >> 1;
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| 62 | q15_t *pIn = data;
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| 63 | q15_t *pOut = data;
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| 64 | q31_t in;
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| 65 | q31_t buf;
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| 66 | q31_t mask;
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| 67 |
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| 68 | while (i)
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| 69 | {
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| 70 | in = *__SIMD32(pIn)++;
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| 71 |
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| 72 | /* extract the first bit */
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| 73 | buf = __ROR(in & 0x80008000, 15);
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| 74 |
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| 75 | /* if MSB=1, mask will be 0xFF, 0x0 otherwise */
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| 76 | mask = __QSUB16(0x00000000, buf);
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| 77 |
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| 78 | *__SIMD32(pOut)++ = in & (~mask);
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| 79 | i--;
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| 80 | }
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| 81 |
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| 82 | if (size & 0x1)
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| 83 | {
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| 84 | if (*pIn < 0)
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| 85 | {
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| 86 | *pIn = 0;
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| 87 | }
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| 88 | pIn++;
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| 89 | }
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| 90 | #else
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| 91 | /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
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| 92 | uint16_t i;
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| 93 |
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| 94 | for (i = 0; i < size; i++)
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| 95 | {
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| 96 | if (data[i] < 0)
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| 97 | data[i] = 0;
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| 98 | }
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| 99 |
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| 100 | #endif /* ARM_MATH_DSP */
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| 101 |
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| 102 | }
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| 103 |
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| 104 | /**
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| 105 | * @} end of Acti group
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| 106 | */
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