1 | /**************************************************************************//**
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2 | * @file os_systick.c
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3 | * @brief CMSIS OS Tick SysTick implementation
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4 | * @version V1.0.1
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5 | * @date 24. November 2017
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6 | ******************************************************************************/
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7 | /*
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8 | * Copyright (c) 2017-2017 ARM Limited. All rights reserved.
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9 | *
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10 | * SPDX-License-Identifier: Apache-2.0
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11 | *
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12 | * Licensed under the Apache License, Version 2.0 (the License); you may
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13 | * not use this file except in compliance with the License.
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14 | * You may obtain a copy of the License at
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15 | *
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16 | * www.apache.org/licenses/LICENSE-2.0
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17 | *
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18 | * Unless required by applicable law or agreed to in writing, software
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19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 | * See the License for the specific language governing permissions and
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22 | * limitations under the License.
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23 | */
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24 |
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25 | #include "os_tick.h"
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26 |
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27 | //lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer"
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28 | #include "RTE_Components.h"
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29 | #include CMSIS_device_header
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30 |
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31 | #ifdef SysTick
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32 |
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33 | #ifndef SYSTICK_IRQ_PRIORITY
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34 | #define SYSTICK_IRQ_PRIORITY 0xFFU
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35 | #endif
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36 |
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37 | static uint8_t PendST;
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38 |
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39 | // Setup OS Tick.
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40 | __WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {
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41 | uint32_t load;
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42 | (void)handler;
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43 |
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44 | if (freq == 0U) {
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45 | //lint -e{904} "Return statement before end of function"
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46 | return (-1);
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47 | }
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48 |
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49 | load = (SystemCoreClock / freq) - 1U;
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50 | if (load > 0x00FFFFFFU) {
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51 | //lint -e{904} "Return statement before end of function"
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52 | return (-1);
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53 | }
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54 |
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55 | // Set SysTick Interrupt Priority
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56 | #if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
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57 | (defined(__CORTEX_M) && (__CORTEX_M == 7U)))
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58 | SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY;
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59 | #elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
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60 | SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);
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61 | #elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \
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62 | (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)))
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63 | SCB->SHP[11] = SYSTICK_IRQ_PRIORITY;
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64 | #elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0))
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65 | SCB->SHP[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);
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66 | #else
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67 | #error "Unknown ARM Core!"
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68 | #endif
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69 |
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70 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk;
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71 | SysTick->LOAD = load;
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72 | SysTick->VAL = 0U;
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73 |
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74 | PendST = 0U;
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75 |
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76 | return (0);
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77 | }
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78 |
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79 | /// Enable OS Tick.
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80 | __WEAK void OS_Tick_Enable (void) {
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81 |
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82 | if (PendST != 0U) {
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83 | PendST = 0U;
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84 | SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
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85 | }
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86 |
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87 | SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
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88 | }
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89 |
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90 | /// Disable OS Tick.
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91 | __WEAK void OS_Tick_Disable (void) {
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92 |
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93 | SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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94 |
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95 | if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) {
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96 | SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
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97 | PendST = 1U;
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98 | }
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99 | }
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100 |
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101 | // Acknowledge OS Tick IRQ.
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102 | __WEAK void OS_Tick_AcknowledgeIRQ (void) {
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103 | (void)SysTick->CTRL;
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104 | }
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105 |
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106 | // Get OS Tick IRQ number.
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107 | __WEAK int32_t OS_Tick_GetIRQn (void) {
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108 | return ((int32_t)SysTick_IRQn);
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109 | }
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110 |
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111 | // Get OS Tick clock.
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112 | __WEAK uint32_t OS_Tick_GetClock (void) {
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113 | return (SystemCoreClock);
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114 | }
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115 |
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116 | // Get OS Tick interval.
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117 | __WEAK uint32_t OS_Tick_GetInterval (void) {
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118 | return (SysTick->LOAD + 1U);
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119 | }
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120 |
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121 | // Get OS Tick count value.
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122 | __WEAK uint32_t OS_Tick_GetCount (void) {
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123 | uint32_t load = SysTick->LOAD;
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124 | return (load - SysTick->VAL);
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125 | }
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126 |
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127 | // Get OS Tick overflow status.
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128 | __WEAK uint32_t OS_Tick_GetOverflow (void) {
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129 | return ((SysTick->CTRL >> 16) & 1U);
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130 | }
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131 |
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132 | #endif // SysTick
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