source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h

Last change on this file was 1, checked in by AlexLir, 4 years ago
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_dfsdm.h
4 * @author MCD Application Team
5 * @brief Header file of DFSDM HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef __STM32F4xx_HAL_DFSDM_H
22#define __STM32F4xx_HAL_DFSDM_H
23
24#ifdef __cplusplus
25 extern "C" {
26#endif
27
28#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
29/* Includes ------------------------------------------------------------------*/
30#include "stm32f4xx_hal_def.h"
31
32/** @addtogroup STM32F4xx_HAL_Driver
33 * @{
34 */
35
36/** @addtogroup DFSDM
37 * @{
38 */
39
40/* Exported types ------------------------------------------------------------*/
41/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
42 * @{
43 */
44
45/**
46 * @brief HAL DFSDM Channel states definition
47 */
48typedef enum
49{
50 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
51 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
52 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */
53}HAL_DFSDM_Channel_StateTypeDef;
54
55/**
56 * @brief DFSDM channel output clock structure definition
57 */
58typedef struct
59{
60 FunctionalState Activation; /*!< Output clock enable/disable */
61 uint32_t Selection; /*!< Output clock is system clock or audio clock.
62 This parameter can be a value of @ref DFSDM_Channel_OuputClock */
63 uint32_t Divider; /*!< Output clock divider.
64 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
65}DFSDM_Channel_OutputClockTypeDef;
66
67/**
68 * @brief DFSDM channel input structure definition
69 */
70typedef struct
71{
72 uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
73 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
74 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
75 This parameter can be a value of @ref DFSDM_Channel_DataPacking */
76 uint32_t Pins; /*!< Input pins are taken from same or following channel.
77 This parameter can be a value of @ref DFSDM_Channel_InputPins */
78}DFSDM_Channel_InputTypeDef;
79
80/**
81 * @brief DFSDM channel serial interface structure definition
82 */
83typedef struct
84{
85 uint32_t Type; /*!< SPI or Manchester modes.
86 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
87 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
88 This parameter can be a value of @ref DFSDM_Channel_SpiClock */
89}DFSDM_Channel_SerialInterfaceTypeDef;
90
91/**
92 * @brief DFSDM channel analog watchdog structure definition
93 */
94typedef struct
95{
96 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
97 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
98 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
99 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
100}DFSDM_Channel_AwdTypeDef;
101
102/**
103 * @brief DFSDM channel init structure definition
104 */
105typedef struct
106{
107 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
108 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */
109 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
110 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */
111 int32_t Offset; /*!< DFSDM channel offset.
112 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
113 uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
114 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
115}DFSDM_Channel_InitTypeDef;
116
117/**
118 * @brief DFSDM channel handle structure definition
119 */
120#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
121typedef struct __DFSDM_Channel_HandleTypeDef
122#else
123typedef struct
124#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
125{
126 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
127 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
128 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
129#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
130 void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */
131 void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */
132 void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */
133 void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */
134#endif
135}DFSDM_Channel_HandleTypeDef;
136
137#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
138/**
139 * @brief DFSDM channel callback ID enumeration definition
140 */
141typedef enum
142{
143 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */
144 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */
145 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */
146 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */
147}HAL_DFSDM_Channel_CallbackIDTypeDef;
148
149/**
150 * @brief DFSDM channel callback pointer definition
151 */
152typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
153#endif
154/**
155 * @brief HAL DFSDM Filter states definition
156 */
157typedef enum
158{
159 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */
160 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */
161 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */
162 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */
163 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
164 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */
165}HAL_DFSDM_Filter_StateTypeDef;
166
167/**
168 * @brief DFSDM filter regular conversion parameters structure definition
169 */
170typedef struct
171{
172 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
173 This parameter can be a value of @ref DFSDM_Filter_Trigger */
174 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
175 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
176}DFSDM_Filter_RegularParamTypeDef;
177
178/**
179 * @brief DFSDM filter injected conversion parameters structure definition
180 */
181typedef struct
182{
183 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
184 This parameter can be a value of @ref DFSDM_Filter_Trigger */
185 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */
186 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */
187 uint32_t ExtTrigger; /*!< External trigger.
188 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
189 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
190 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
191}DFSDM_Filter_InjectedParamTypeDef;
192
193/**
194 * @brief DFSDM filter parameters structure definition
195 */
196typedef struct
197{
198 uint32_t SincOrder; /*!< Sinc filter order.
199 This parameter can be a value of @ref DFSDM_Filter_SincOrder */
200 uint32_t Oversampling; /*!< Filter oversampling ratio.
201 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
202 uint32_t IntOversampling; /*!< Integrator oversampling ratio.
203 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
204}DFSDM_Filter_FilterParamTypeDef;
205
206/**
207 * @brief DFSDM filter init structure definition
208 */
209typedef struct
210{
211 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
212 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
213 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
214}DFSDM_Filter_InitTypeDef;
215
216/**
217 * @brief DFSDM filter handle structure definition
218 */
219#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
220typedef struct __DFSDM_Filter_HandleTypeDef
221#else
222typedef struct
223#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
224{
225 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
226 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
227 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */
228 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */
229 uint32_t RegularContMode; /*!< Regular conversion continuous mode */
230 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */
231 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */
232 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
233 FunctionalState InjectedScanMode; /*!< Injected scanning mode */
234 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
235 uint32_t InjConvRemaining; /*!< Injected conversions remaining */
236 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
237 uint32_t ErrorCode; /*!< DFSDM filter error code */
238#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
239 void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
240 uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */
241 void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */
242 void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */
243 void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */
244 void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */
245 void (*ErrorCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */
246 void (*MspInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */
247 void (*MspDeInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */
248#endif
249}DFSDM_Filter_HandleTypeDef;
250
251/**
252 * @brief DFSDM filter analog watchdog parameters structure definition
253 */
254typedef struct
255{
256 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
257 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
258 uint32_t Channel; /*!< Analog watchdog channel selection.
259 This parameter can be a values combination of @ref DFSDM_Channel_Selection */
260 int32_t HighThreshold; /*!< High threshold for the analog watchdog.
261 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
262 int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
263 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
264 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
265 This parameter can be a values combination of @ref DFSDM_BreakSignals */
266 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
267 This parameter can be a values combination of @ref DFSDM_BreakSignals */
268}DFSDM_Filter_AwdParamTypeDef;
269
270#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
271/**
272 * @brief DFSDM filter callback ID enumeration definition
273 */
274typedef enum
275{
276 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */
277 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */
278 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */
279 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */
280 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */
281 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */
282 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */
283}HAL_DFSDM_Filter_CallbackIDTypeDef;
284
285/**
286 * @brief DFSDM filter callback pointer definition
287 */
288typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
289typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
290#endif
291
292/**
293 * @}
294 */
295#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
296/**
297 * @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices
298 */
299typedef struct
300{
301 uint32_t DFSDM1ClockIn; /*!< Source selection for DFSDM1_Ckin.
302 This parameter can be a value of @ref DFSDM_1_CLOCKIN_SELECTION*/
303 uint32_t DFSDM2ClockIn; /*!< Source selection for DFSDM2_Ckin.
304 This parameter can be a value of @ref DFSDM_2_CLOCKIN_SELECTION*/
305 uint32_t DFSDM1ClockOut; /*!< Source selection for DFSDM1_Ckout.
306 This parameter can be a value of @ref DFSDM_1_CLOCKOUT_SELECTION*/
307 uint32_t DFSDM2ClockOut; /*!< Source selection for DFSDM2_Ckout.
308 This parameter can be a value of @ref DFSDM_2_CLOCKOUT_SELECTION*/
309 uint32_t DFSDM1BitClkDistribution; /*!< Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 or TIM4 OC2.
310 This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION
311 @note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2
312 @note The DFSDM2 audio gated by TIM4 OC1 can be injected on CKIN1 or CKIN3 */
313 uint32_t DFSDM2BitClkDistribution; /*!< Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 or TIM3 OC2 or TIM3 OC3 or TIM3 OC4.
314 This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION
315 @note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4
316 @note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5
317 @note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6
318 @note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */
319 uint32_t DFSDM1DataDistribution; /*!< Source selection for DatIn0 and DatIn2 of DFSDM1.
320 This parameter can be a value of @ref DFSDM_1_DATA_DISTRIBUTION */
321 uint32_t DFSDM2DataDistribution; /*!< Source selection for DatIn0, DatIn2, DatIn4 and DatIn6 of DFSDM2.
322 This parameter can be a value of @ref DFSDM_2_DATA_DISTRIBUTION */
323}DFSDM_MultiChannelConfigTypeDef;
324#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
325/**
326 * @}
327 */
328
329/* End of exported types -----------------------------------------------------*/
330
331/* Exported constants --------------------------------------------------------*/
332/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
333 * @{
334 */
335
336/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
337 * @{
338 */
339#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */
340#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
341/**
342 * @}
343 */
344
345/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
346 * @{
347 */
348#define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */
349#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
350/**
351 * @}
352 */
353
354/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
355 * @{
356 */
357#define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */
358#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
359#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
360/**
361 * @}
362 */
363
364/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
365 * @{
366 */
367#define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */
368#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
369/**
370 * @}
371 */
372
373/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
374 * @{
375 */
376#define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */
377#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
378#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
379#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
380/**
381 * @}
382 */
383
384/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
385 * @{
386 */
387#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */
388#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
389#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
390#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
391/**
392 * @}
393 */
394
395/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
396 * @{
397 */
398#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
399#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
400#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
401#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
402/**
403 * @}
404 */
405
406/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
407 * @{
408 */
409#define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */
410#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */
411#define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */
412/**
413 * @}
414 */
415
416/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
417 * @{
418 */
419#if defined(STM32F413xx) || defined(STM32F423xx)
420/* Trigger for stm32f413xx and STM32f423xx devices */
421#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For All DFSDM1/2 filters */
422#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For All DFSDM1/2 filters */
423#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For All DFSDM1/2 filters */
424#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */
425#define DFSDM_FILTER_EXT_TRIG_TIM2_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM2 filter 3 */
426#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */
427#define DFSDM_FILTER_EXT_TRIG_TIM11_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM2 filter 3 */
428#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0 and 1 */
429#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM2 filter 2 and 3*/
430#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For All DFSDM1/2 filters */
431#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For All DFSDM1/2 filters */
432#else
433/* Trigger for stm32f412xx devices */
434#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM1 filter 0 and 1*/
435#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM1 filter 0 and 1*/
436#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM1 filter 0 and 1*/
437#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1*/
438#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1*/
439#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/
440#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/
441#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM1 filter 0 and 1*/
442#endif
443/**
444 * @}
445 */
446
447/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
448 * @{
449 */
450#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
451#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
452#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */
453/**
454 * @}
455 */
456
457/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
458 * @{
459 */
460#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
461#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
462#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
463#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
464#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
465#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
466/**
467 * @}
468 */
469
470/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
471 * @{
472 */
473#define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */
474#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
475/**
476 * @}
477 */
478
479/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
480 * @{
481 */
482#define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */
483#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */
484#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */
485#define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */
486#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
487#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */
488#endif
489/**
490 * @}
491 */
492
493/** @defgroup DFSDM_BreakSignals DFSDM break signals
494 * @{
495 */
496#define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */
497#define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */
498#define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */
499#define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */
500#define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */
501/**
502 * @}
503 */
504
505/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
506 * @{
507 */
508/* DFSDM Channels ------------------------------------------------------------*/
509/* The DFSDM channels are defined as follows:
510 - in 16-bit LSB the channel mask is set
511 - in 16-bit MSB the channel number is set
512 e.g. for channel 3 definition:
513 - the channel mask is 0x00000008 (bit 3 is set)
514 - the channel number 3 is 0x00030000
515 --> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */
516#define DFSDM_CHANNEL_0 0x00000001U
517#define DFSDM_CHANNEL_1 0x00010002U
518#define DFSDM_CHANNEL_2 0x00020004U
519#define DFSDM_CHANNEL_3 0x00030008U
520#define DFSDM_CHANNEL_4 0x00040010U /* only for stmm32f413xx and stm32f423xx devices */
521#define DFSDM_CHANNEL_5 0x00050020U /* only for stmm32f413xx and stm32f423xx devices */
522#define DFSDM_CHANNEL_6 0x00060040U /* only for stmm32f413xx and stm32f423xx devices */
523#define DFSDM_CHANNEL_7 0x00070080U /* only for stmm32f413xx and stm32f423xx devices */
524/**
525 * @}
526 */
527
528/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
529 * @{
530 */
531#define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */
532#define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */
533/**
534 * @}
535 */
536
537/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
538 * @{
539 */
540#define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */
541#define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */
542/**
543 * @}
544 */
545
546#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
547/** @defgroup DFSDM_1_CLOCKOUT_SELECTION DFSDM1 ClockOut Selection
548 * @{
549 */
550#define DFSDM1_CKOUT_DFSDM2_CKOUT 0x00000080U
551#define DFSDM1_CKOUT_DFSDM1 0x00000000U
552/**
553 * @}
554 */
555
556/** @defgroup DFSDM_2_CLOCKOUT_SELECTION DFSDM2 ClockOut Selection
557 * @{
558 */
559#define DFSDM2_CKOUT_DFSDM2_CKOUT 0x00040000U
560#define DFSDM2_CKOUT_DFSDM2 0x00000000U
561/**
562 * @}
563 */
564
565/** @defgroup DFSDM_1_CLOCKIN_SELECTION DFSDM1 ClockIn Selection
566 * @{
567 */
568#define DFSDM1_CKIN_DFSDM2_CKOUT 0x00000040U
569#define DFSDM1_CKIN_PAD 0x00000000U
570/**
571 * @}
572 */
573
574/** @defgroup DFSDM_2_CLOCKIN_SELECTION DFSDM2 ClockIn Selection
575 * @{
576 */
577#define DFSDM2_CKIN_DFSDM2_CKOUT 0x00020000U
578#define DFSDM2_CKIN_PAD 0x00000000U
579/**
580 * @}
581 */
582
583/** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution
584 * @{
585 */
586#define DFSDM1_T4_OC2_BITSTREAM_CKIN0 0x00000000U /* TIM4_OC2 to CLKIN0 */
587#define DFSDM1_T4_OC2_BITSTREAM_CKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */
588#define DFSDM1_T4_OC1_BITSTREAM_CKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */
589#define DFSDM1_T4_OC1_BITSTREAM_CKIN1 0x00000000U /* TIM4_OC1 to CLKIN1 */
590/**
591 * @}
592 */
593
594/** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution
595 * @{
596 */
597#define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */
598#define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */
599#define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */
600#define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */
601#define DFSDM2_T3_OC2_BITSTREAM_CKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */
602#define DFSDM2_T3_OC2_BITSTREAM_CKIN2 0x00000000U /* TIM3_OC2 to CKIN2 */
603#define DFSDM2_T3_OC1_BITSTREAM_CKIN3 0x00000000U /* TIM3_OC1 to CKIN3 */
604#define DFSDM2_T3_OC1_BITSTREAM_CKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL /* TIM3_OC1 to CKIN7 */
605/**
606 * @}
607 */
608
609/** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution
610 * @{
611 */
612#define DFSDM1_DATIN0_TO_DATIN0_PAD 0x00000000U
613#define DFSDM1_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM1D0SEL
614#define DFSDM1_DATIN2_TO_DATIN2_PAD 0x00000000U
615#define DFSDM1_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM1D2SEL
616/**
617 * @}
618 */
619
620/** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution
621 * @{
622 */
623#define DFSDM2_DATIN0_TO_DATIN0_PAD 0x00000000U
624#define DFSDM2_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM2D0SEL
625#define DFSDM2_DATIN2_TO_DATIN2_PAD 0x00000000U
626#define DFSDM2_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM2D2SEL
627#define DFSDM2_DATIN4_TO_DATIN4_PAD 0x00000000U
628#define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL
629#define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U
630#define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL
631/**
632 * @}
633 */
634
635/** @defgroup HAL_MCHDLY_CLOCK HAL MCHDLY Clock enable
636 * @{
637 */
638#define HAL_MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN
639#define HAL_MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN
640/**
641 * @}
642 */
643
644/** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection
645 * @{
646 */
647#define HAL_DFSDM2_CKIN_PAD 0x00040000U
648#define HAL_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
649#define HAL_DFSDM1_CKIN_PAD 0x00000000U
650#define HAL_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
651/**
652 * @}
653 */
654
655/** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection
656 * @{
657 */
658#define HAL_DFSDM2_CKOUT_DFSDM2 0x10000000U
659#define HAL_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
660#define HAL_DFSDM1_CKOUT_DFSDM1 0x00000000U
661#define HAL_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
662/**
663 * @}
664 */
665
666/** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0
667 * @{
668 */
669#define HAL_DATAIN0_DFSDM2_PAD 0x10000000U
670#define HAL_DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL
671#define HAL_DATAIN0_DFSDM1_PAD 0x00000000U
672#define HAL_DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL
673/**
674 * @}
675 */
676
677/** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2
678 * @{
679 */
680#define HAL_DATAIN2_DFSDM2_PAD 0x10000000U
681#define HAL_DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL
682#define HAL_DATAIN2_DFSDM1_PAD 0x00000000U
683#define HAL_DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL
684/**
685 * @}
686 */
687
688/** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4
689 * @{
690 */
691#define HAL_DATAIN4_DFSDM2_PAD 0x00000000U
692#define HAL_DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL
693/**
694 * @}
695 */
696
697/** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6
698 * @{
699 */
700#define HAL_DATAIN6_DFSDM2_PAD 0x00000000U
701#define HAL_DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL
702/**
703 * @}
704 */
705
706/** @defgroup DFSDM1_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN
707 * @{
708 */
709#define HAL_DFSDM1_CLKIN0_TIM4OC2 0x01000000U
710#define HAL_DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
711#define HAL_DFSDM1_CLKIN1_TIM4OC1 0x02000000U
712#define HAL_DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
713/**
714 * @}
715 */
716
717/** @defgroup DFSDM2_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN
718 * @{
719 */
720#define HAL_DFSDM2_CLKIN0_TIM3OC4 0x04000000U
721#define HAL_DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
722#define HAL_DFSDM2_CLKIN1_TIM3OC3 0x08000000U
723#define HAL_DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
724#define HAL_DFSDM2_CLKIN2_TIM3OC2 0x10000000U
725#define HAL_DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
726#define HAL_DFSDM2_CLKIN3_TIM3OC1 0x00000000U
727#define HAL_DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
728/**
729 * @}
730 */
731
732#endif /* SYSCFG_MCHDLYCR_BSCKSEL*/
733/**
734 * @}
735 */
736/* End of exported constants -------------------------------------------------*/
737
738/* Exported macros -----------------------------------------------------------*/
739/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
740 * @{
741 */
742
743/** @brief Reset DFSDM channel handle state.
744 * @param __HANDLE__ DFSDM channel handle.
745 * @retval None
746 */
747#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
748#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \
749 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \
750 (__HANDLE__)->MspInitCallback = NULL; \
751 (__HANDLE__)->MspDeInitCallback = NULL; \
752 } while(0)
753#else
754#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
755#endif
756
757/** @brief Reset DFSDM filter handle state.
758 * @param __HANDLE__ DFSDM filter handle.
759 * @retval None
760 */
761#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
762#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \
763 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \
764 (__HANDLE__)->MspInitCallback = NULL; \
765 (__HANDLE__)->MspDeInitCallback = NULL; \
766 } while(0)
767#else
768#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
769#endif
770
771/**
772 * @}
773 */
774/* End of exported macros ----------------------------------------------------*/
775
776/* Exported functions --------------------------------------------------------*/
777/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
778 * @{
779 */
780
781/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
782 * @{
783 */
784/* Channel initialization and de-initialization functions *********************/
785HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
786HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
787void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
788void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
789#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
790/* Channel callbacks register/unregister functions ****************************/
791HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
792 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
793 pDFSDM_Channel_CallbackTypeDef pCallback);
794HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
795 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);
796#endif
797/**
798 * @}
799 */
800
801/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
802 * @{
803 */
804/* Channel operation functions ************************************************/
805HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
806HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
807HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
808HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
809
810HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
811HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
812HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
813HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
814
815int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
816HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
817
818HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
819HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
820
821void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
822void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
823/**
824 * @}
825 */
826
827/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
828 * @{
829 */
830/* Channel state function *****************************************************/
831HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
832/**
833 * @}
834 */
835
836/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
837 * @{
838 */
839/* Filter initialization and de-initialization functions *********************/
840HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
841HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
842void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
843void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
844#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
845/* Filter callbacks register/unregister functions ****************************/
846HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
847 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
848 pDFSDM_Filter_CallbackTypeDef pCallback);
849HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
850 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);
851HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
852 pDFSDM_Filter_AwdCallbackTypeDef pCallback);
853HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
854#endif
855/**
856 * @}
857 */
858
859/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
860 * @{
861 */
862/* Filter control functions *********************/
863HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
864 uint32_t Channel,
865 uint32_t ContinuousMode);
866HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
867 uint32_t Channel);
868/**
869 * @}
870 */
871
872/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
873 * @{
874 */
875/* Filter operation functions *********************/
876HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
877HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
878HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
879HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
880HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
881HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
882HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
883HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
884HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
885HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
886HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
887HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
888HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
889HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
890HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
891 DFSDM_Filter_AwdParamTypeDef* awdParam);
892HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
893HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
894HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
895
896int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
897int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
898int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
899int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
900uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
901
902void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
903
904HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
905HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
906
907void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
908void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
909void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
910void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
911void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
912void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
913/**
914 * @}
915 */
916
917/** @addtogroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
918 * @{
919 */
920/* Filter state functions *****************************************************/
921HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
922uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
923/**
924 * @}
925 */
926/** @addtogroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions
927 * @{
928 */
929#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
930void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct);
931void HAL_DFSDM_BitstreamClock_Start(void);
932void HAL_DFSDM_BitstreamClock_Stop(void);
933void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY);
934void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY);
935void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source);
936void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source);
937void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source);
938void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source);
939void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source);
940void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source);
941void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);
942#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
943/**
944 * @}
945 */
946/**
947 * @}
948 */
949/* End of exported functions -------------------------------------------------*/
950
951/* Private macros ------------------------------------------------------------*/
952/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
953* @{
954*/
955#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
956 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
957#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
958#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
959 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
960#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
961 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
962 ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
963#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
964 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
965#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
966 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
967 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
968 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
969#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
970 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
971 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
972 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
973#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
974 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
975 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
976 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
977#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U))
978#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
979#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU)
980#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU)
981#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
982 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
983#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
984 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
985 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
986#if defined (STM32F413xx) || defined (STM32F423xx)
987#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
988 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
989 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
990 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
991 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM2_TRGO) || \
992 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
993 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM11_OC1) || \
994 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
995 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
996 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
997#define IS_DFSDM_DELAY_CLOCK(CLOCK) (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \
998 ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1))
999#else
1000#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
1001 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
1002 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
1003 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
1004 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
1005 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
1006 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
1007 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
1008#endif
1009#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
1010 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
1011 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
1012#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
1013 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
1014 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
1015 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
1016 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
1017 ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
1018#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U))
1019#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U))
1020#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
1021 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
1022#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
1023#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0x0FU)
1024#if defined(DFSDM2_Channel0)
1025#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
1026 ((CHANNEL) == DFSDM_CHANNEL_1) || \
1027 ((CHANNEL) == DFSDM_CHANNEL_2) || \
1028 ((CHANNEL) == DFSDM_CHANNEL_3) || \
1029 ((CHANNEL) == DFSDM_CHANNEL_4) || \
1030 ((CHANNEL) == DFSDM_CHANNEL_5) || \
1031 ((CHANNEL) == DFSDM_CHANNEL_6) || \
1032 ((CHANNEL) == DFSDM_CHANNEL_7))
1033#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
1034#else
1035#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
1036 ((CHANNEL) == DFSDM_CHANNEL_1) || \
1037 ((CHANNEL) == DFSDM_CHANNEL_2) || \
1038 ((CHANNEL) == DFSDM_CHANNEL_3))
1039#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))
1040#endif
1041#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
1042 ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
1043#if defined(DFSDM2_Channel0)
1044#define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
1045 ((INSTANCE) == DFSDM1_Channel1) || \
1046 ((INSTANCE) == DFSDM1_Channel2) || \
1047 ((INSTANCE) == DFSDM1_Channel3))
1048#define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
1049 ((INSTANCE) == DFSDM1_Filter1))
1050#endif /* DFSDM2_Channel0 */
1051
1052#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
1053#define IS_DFSDM_CLOCKIN_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \
1054 ((SELECTION) == HAL_DFSDM2_CKIN_DM) || \
1055 ((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \
1056 ((SELECTION) == HAL_DFSDM1_CKIN_DM))
1057#define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \
1058 ((SELECTION) == HAL_DFSDM2_CKOUT_M27) || \
1059 ((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \
1060 ((SELECTION) == HAL_DFSDM1_CKOUT_M27))
1061#define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD) || \
1062 ((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \
1063 ((SELECTION) == HAL_DATAIN0_DFSDM1_PAD) || \
1064 ((SELECTION) == HAL_DATAIN0_DFSDM1_DATAIN1))
1065#define IS_DFSDM_DATAIN2_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN2_DFSDM2_PAD) || \
1066 ((SELECTION) == HAL_DATAIN2_DFSDM2_DATAIN3) || \
1067 ((SELECTION) == HAL_DATAIN2_DFSDM1_PAD) || \
1068 ((SELECTION) == HAL_DATAIN2_DFSDM1_DATAIN3))
1069#define IS_DFSDM_DATAIN4_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN4_DFSDM2_PAD) || \
1070 ((SELECTION) == HAL_DATAIN4_DFSDM2_DATAIN5))
1071#define IS_DFSDM_DATAIN6_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN6_DFSDM2_PAD) || \
1072 ((SELECTION) == HAL_DATAIN6_DFSDM2_DATAIN7))
1073#define IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(DISTRIBUTION) (((DISTRIBUTION) == HAL_DFSDM1_CLKIN0_TIM4OC2) || \
1074 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN2_TIM4OC2) || \
1075 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN1_TIM4OC1) || \
1076 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN3_TIM4OC1) || \
1077 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN0_TIM3OC4) || \
1078 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN4_TIM3OC4) || \
1079 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN1_TIM3OC3)|| \
1080 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN5_TIM3OC3) || \
1081 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN2_TIM3OC2) || \
1082 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN6_TIM3OC2) || \
1083 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN3_TIM3OC1)|| \
1084 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN7_TIM3OC1))
1085#define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT) || \
1086 ((CLKOUT) == DFSDM1_CKOUT_DFSDM1))
1087#define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT) || \
1088 ((CLKOUT) == DFSDM2_CKOUT_DFSDM2))
1089#define IS_DFSDM_DFSDM1_CLKIN(CLKIN) (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT) || \
1090 ((CLKIN) == DFSDM1_CKIN_PAD))
1091#define IS_DFSDM_DFSDM2_CLKIN(CLKIN) (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT) || \
1092 ((CLKIN) == DFSDM2_CKIN_PAD))
1093#define IS_DFSDM_DFSDM1_BIT_CLK(CLK) (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0) || \
1094 ((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2) || \
1095 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3) || \
1096 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1) || \
1097 ((CLK) <= 0x30U))
1098
1099#define IS_DFSDM_DFSDM2_BIT_CLK(CLK) (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0) || \
1100 ((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4) || \
1101 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN5) || \
1102 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN1) || \
1103 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN6) || \
1104 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2) || \
1105 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3) || \
1106 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \
1107 ((CLK) <= 0x1E000U))
1108
1109#define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \
1110 ((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \
1111 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \
1112 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \
1113 ((DISTRIBUTION) <= 0xCU))
1114
1115#define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \
1116 ((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \
1117 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \
1118 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN3_PAD)|| \
1119 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN4_PAD)|| \
1120 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \
1121 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \
1122 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \
1123 ((DISTRIBUTION) <= 0x1D00U))
1124#endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */
1125/**
1126 * @}
1127 */
1128/* End of private macros -----------------------------------------------------*/
1129
1130/**
1131 * @}
1132 */
1133
1134/**
1135 * @}
1136 */
1137#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
1138#ifdef __cplusplus
1139}
1140#endif
1141
1142#endif /* __STM32F4xx_HAL_DFSDM_H */
1143
1144/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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