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stm32f4xx_hal_dma.h

Last change on this file was 1, checked in by AlexLir, 3 years ago

File size: 37.9 KB

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_hal_dma.h
4	* @author MCD Application Team
5	* @brief Header file of DMA HAL module.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19
20	/* Define to prevent recursive inclusion -------------------------------------*/
21	#ifndef __STM32F4xx_HAL_DMA_H
22	#define __STM32F4xx_HAL_DMA_H
23
24	#ifdef __cplusplus
25	extern "C" {
26	#endif
27
28	/* Includes ------------------------------------------------------------------*/
29	#include "stm32f4xx_hal_def.h"
30
31	/** @addtogroup STM32F4xx_HAL_Driver
32	* @{
33	*/
34
35	/** @addtogroup DMA
36	* @{
37	*/
38
39	/* Exported types ------------------------------------------------------------*/
40
41	/** @defgroup DMA_Exported_Types DMA Exported Types
42	* @brief DMA Exported Types
43	* @{
44	*/
45
46	/**
47	* @brief DMA Configuration Structure definition
48	*/
49	typedef struct
50	{
51	uint32_t Channel; /*!< Specifies the channel used for the specified stream.
52	This parameter can be a value of @ref DMA_Channel_selection */
53
54	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
55	from memory to memory or from peripheral to memory.
56	This parameter can be a value of @ref DMA_Data_transfer_direction */
57
58	uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
59	This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
60
61	uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
62	This parameter can be a value of @ref DMA_Memory_incremented_mode */
63
64	uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
65	This parameter can be a value of @ref DMA_Peripheral_data_size */
66
67	uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
68	This parameter can be a value of @ref DMA_Memory_data_size */
69
70	uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
71	This parameter can be a value of @ref DMA_mode
72	@note The circular buffer mode cannot be used if the memory-to-memory
73	data transfer is configured on the selected Stream */
74
75	uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
76	This parameter can be a value of @ref DMA_Priority_level */
77
78	uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
79	This parameter can be a value of @ref DMA_FIFO_direct_mode
80	@note The Direct mode (FIFO mode disabled) cannot be used if the
81	memory-to-memory data transfer is configured on the selected stream */
82
83	uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
84	This parameter can be a value of @ref DMA_FIFO_threshold_level */
85
86	uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
87	It specifies the amount of data to be transferred in a single non interruptible
88	transaction.
89	This parameter can be a value of @ref DMA_Memory_burst
90	@note The burst mode is possible only if the address Increment mode is enabled. */
91
92	uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
93	It specifies the amount of data to be transferred in a single non interruptible
94	transaction.
95	This parameter can be a value of @ref DMA_Peripheral_burst
96	@note The burst mode is possible only if the address Increment mode is enabled. */
97	}DMA_InitTypeDef;
98
99
100	/**
101	* @brief HAL DMA State structures definition
102	*/
103	typedef enum
104	{
105	HAL_DMA_STATE_RESET = 0x00U, /!< DMA not yet initialized or disabled /
106	HAL_DMA_STATE_READY = 0x01U, /!< DMA initialized and ready for use /
107	HAL_DMA_STATE_BUSY = 0x02U, /!< DMA process is ongoing /
108	HAL_DMA_STATE_TIMEOUT = 0x03U, /!< DMA timeout state /
109	HAL_DMA_STATE_ERROR = 0x04U, /!< DMA error state /
110	HAL_DMA_STATE_ABORT = 0x05U, /!< DMA Abort state /
111	}HAL_DMA_StateTypeDef;
112
113	/**
114	* @brief HAL DMA Error Code structure definition
115	*/
116	typedef enum
117	{
118	HAL_DMA_FULL_TRANSFER = 0x00U, /!< Full transfer /
119	HAL_DMA_HALF_TRANSFER = 0x01U /!< Half Transfer /
120	}HAL_DMA_LevelCompleteTypeDef;
121
122	/**
123	* @brief HAL DMA Error Code structure definition
124	*/
125	typedef enum
126	{
127	HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /!< Full transfer /
128	HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /!< Half Transfer /
129	HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /!< M1 Full Transfer /
130	HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /!< M1 Half Transfer /
131	HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /!< Error /
132	HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /!< Abort /
133	HAL_DMA_XFER_ALL_CB_ID = 0x06U /!< All /
134	}HAL_DMA_CallbackIDTypeDef;
135
136	/**
137	* @brief DMA handle Structure definition
138	*/
139	typedef struct __DMA_HandleTypeDef
140	{
141	DMA_Stream_TypeDef Instance; /!< Register base address */
142
143	DMA_InitTypeDef Init; /!< DMA communication parameters /
144
145	HAL_LockTypeDef Lock; /!< DMA locking object /
146
147	__IO HAL_DMA_StateTypeDef State; /!< DMA transfer state /
148
149	void Parent; /!< Parent object state */
150
151	void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer complete callback /
152
153	void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA Half transfer complete callback /
154
155	void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer complete Memory1 callback /
156
157	void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer Half complete Memory1 callback /
158
159	void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer error callback /
160
161	void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer Abort callback /
162
163	__IO uint32_t ErrorCode; /!< DMA Error code /
164
165	uint32_t StreamBaseAddress; /!< DMA Stream Base Address /
166
167	uint32_t StreamIndex; /!< DMA Stream Index /
168
169	}DMA_HandleTypeDef;
170
171	/**
172	* @}
173	*/
174
175	/* Exported constants --------------------------------------------------------*/
176
177	/** @defgroup DMA_Exported_Constants DMA Exported Constants
178	* @brief DMA Exported constants
179	* @{
180	*/
181
182	/** @defgroup DMA_Error_Code DMA Error Code
183	* @brief DMA Error Code
184	* @{
185	*/
186	#define HAL_DMA_ERROR_NONE 0x00000000U /!< No error /
187	#define HAL_DMA_ERROR_TE 0x00000001U /!< Transfer error /
188	#define HAL_DMA_ERROR_FE 0x00000002U /!< FIFO error /
189	#define HAL_DMA_ERROR_DME 0x00000004U /!< Direct Mode error /
190	#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /!< Timeout error /
191	#define HAL_DMA_ERROR_PARAM 0x00000040U /!< Parameter error /
192	#define HAL_DMA_ERROR_NO_XFER 0x00000080U /!< Abort requested with no Xfer ongoing /
193	#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /!< Not supported mode /
194	/**
195	* @}
196	*/
197
198	/** @defgroup DMA_Channel_selection DMA Channel selection
199	* @brief DMA channel selection
200	* @{
201	*/
202	#define DMA_CHANNEL_0 0x00000000U /!< DMA Channel 0 /
203	#define DMA_CHANNEL_1 0x02000000U /!< DMA Channel 1 /
204	#define DMA_CHANNEL_2 0x04000000U /!< DMA Channel 2 /
205	#define DMA_CHANNEL_3 0x06000000U /!< DMA Channel 3 /
206	#define DMA_CHANNEL_4 0x08000000U /!< DMA Channel 4 /
207	#define DMA_CHANNEL_5 0x0A000000U /!< DMA Channel 5 /
208	#define DMA_CHANNEL_6 0x0C000000U /!< DMA Channel 6 /
209	#define DMA_CHANNEL_7 0x0E000000U /!< DMA Channel 7 /
210	#if defined (DMA_SxCR_CHSEL_3)
211	#define DMA_CHANNEL_8 0x10000000U /!< DMA Channel 8 /
212	#define DMA_CHANNEL_9 0x12000000U /!< DMA Channel 9 /
213	#define DMA_CHANNEL_10 0x14000000U /!< DMA Channel 10 /
214	#define DMA_CHANNEL_11 0x16000000U /!< DMA Channel 11 /
215	#define DMA_CHANNEL_12 0x18000000U /!< DMA Channel 12 /
216	#define DMA_CHANNEL_13 0x1A000000U /!< DMA Channel 13 /
217	#define DMA_CHANNEL_14 0x1C000000U /!< DMA Channel 14 /
218	#define DMA_CHANNEL_15 0x1E000000U /!< DMA Channel 15 /
219	#endif /* DMA_SxCR_CHSEL_3 */
220	/**
221	* @}
222	*/
223
224	/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
225	* @brief DMA data transfer direction
226	* @{
227	*/
228	#define DMA_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
229	#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /!< Memory to peripheral direction /
230	#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /!< Memory to memory direction /
231	/**
232	* @}
233	*/
234
235	/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
236	* @brief DMA peripheral incremented mode
237	* @{
238	*/
239	#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /!< Peripheral increment mode enable /
240	#define DMA_PINC_DISABLE 0x00000000U /!< Peripheral increment mode disable /
241	/**
242	* @}
243	*/
244
245	/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
246	* @brief DMA memory incremented mode
247	* @{
248	*/
249	#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /!< Memory increment mode enable /
250	#define DMA_MINC_DISABLE 0x00000000U /!< Memory increment mode disable /
251	/**
252	* @}
253	*/
254
255	/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
256	* @brief DMA peripheral data size
257	* @{
258	*/
259	#define DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment: Byte /
260	#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /!< Peripheral data alignment: HalfWord /
261	#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /!< Peripheral data alignment: Word /
262	/**
263	* @}
264	*/
265
266	/** @defgroup DMA_Memory_data_size DMA Memory data size
267	* @brief DMA memory data size
268	* @{
269	*/
270	#define DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment: Byte /
271	#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /!< Memory data alignment: HalfWord /
272	#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /!< Memory data alignment: Word /
273	/**
274	* @}
275	*/
276
277	/** @defgroup DMA_mode DMA mode
278	* @brief DMA mode
279	* @{
280	*/
281	#define DMA_NORMAL 0x00000000U /!< Normal mode /
282	#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /!< Circular mode /
283	#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /!< Peripheral flow control mode /
284	/**
285	* @}
286	*/
287
288	/** @defgroup DMA_Priority_level DMA Priority level
289	* @brief DMA priority levels
290	* @{
291	*/
292	#define DMA_PRIORITY_LOW 0x00000000U /!< Priority level: Low /
293	#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /!< Priority level: Medium /
294	#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /!< Priority level: High /
295	#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /!< Priority level: Very High /
296	/**
297	* @}
298	*/
299
300	/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
301	* @brief DMA FIFO direct mode
302	* @{
303	*/
304	#define DMA_FIFOMODE_DISABLE 0x00000000U /!< FIFO mode disable /
305	#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /!< FIFO mode enable /
306	/**
307	* @}
308	*/
309
310	/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
311	* @brief DMA FIFO level
312	* @{
313	*/
314	#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /!< FIFO threshold 1 quart full configuration /
315	#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /!< FIFO threshold half full configuration /
316	#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /!< FIFO threshold 3 quarts full configuration /
317	#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /!< FIFO threshold full configuration /
318	/**
319	* @}
320	*/
321
322	/** @defgroup DMA_Memory_burst DMA Memory burst
323	* @brief DMA memory burst
324	* @{
325	*/
326	#define DMA_MBURST_SINGLE 0x00000000U
327	#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
328	#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
329	#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
330	/**
331	* @}
332	*/
333
334	/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
335	* @brief DMA peripheral burst
336	* @{
337	*/
338	#define DMA_PBURST_SINGLE 0x00000000U
339	#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
340	#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
341	#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
342	/**
343	* @}
344	*/
345
346	/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
347	* @brief DMA interrupts definition
348	* @{
349	*/
350	#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
351	#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
352	#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
353	#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
354	#define DMA_IT_FE 0x00000080U
355	/**
356	* @}
357	*/
358
359	/** @defgroup DMA_flag_definitions DMA flag definitions
360	* @brief DMA flag definitions
361	* @{
362	*/
363	#define DMA_FLAG_FEIF0_4 0x00000001U
364	#define DMA_FLAG_DMEIF0_4 0x00000004U
365	#define DMA_FLAG_TEIF0_4 0x00000008U
366	#define DMA_FLAG_HTIF0_4 0x00000010U
367	#define DMA_FLAG_TCIF0_4 0x00000020U
368	#define DMA_FLAG_FEIF1_5 0x00000040U
369	#define DMA_FLAG_DMEIF1_5 0x00000100U
370	#define DMA_FLAG_TEIF1_5 0x00000200U
371	#define DMA_FLAG_HTIF1_5 0x00000400U
372	#define DMA_FLAG_TCIF1_5 0x00000800U
373	#define DMA_FLAG_FEIF2_6 0x00010000U
374	#define DMA_FLAG_DMEIF2_6 0x00040000U
375	#define DMA_FLAG_TEIF2_6 0x00080000U
376	#define DMA_FLAG_HTIF2_6 0x00100000U
377	#define DMA_FLAG_TCIF2_6 0x00200000U
378	#define DMA_FLAG_FEIF3_7 0x00400000U
379	#define DMA_FLAG_DMEIF3_7 0x01000000U
380	#define DMA_FLAG_TEIF3_7 0x02000000U
381	#define DMA_FLAG_HTIF3_7 0x04000000U
382	#define DMA_FLAG_TCIF3_7 0x08000000U
383	/**
384	* @}
385	*/
386
387	/**
388	* @}
389	*/
390
391	/* Exported macro ------------------------------------------------------------*/
392
393	/** @brief Reset DMA handle state
394	* @param __HANDLE__ specifies the DMA handle.
395	* @retval None
396	*/
397	#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
398
399	/**
400	* @brief Return the current DMA Stream FIFO filled level.
401	* @param __HANDLE__ DMA handle
402	* @retval The FIFO filling state.
403	* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
404	* and not empty.
405	* - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
406	* - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
407	* - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
408	* - DMA_FIFOStatus_Empty: when FIFO is empty
409	* - DMA_FIFOStatus_Full: when FIFO is full
410	*/
411	#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
412
413	/**
414	* @brief Enable the specified DMA Stream.
415	* @param __HANDLE__ DMA handle
416	* @retval None
417	*/
418	#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= DMA_SxCR_EN)
419
420	/**
421	* @brief Disable the specified DMA Stream.
422	* @param __HANDLE__ DMA handle
423	* @retval None
424	*/
425	#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
426
427	/* Interrupt & Flag management */
428
429	/**
430	* @brief Return the current DMA Stream transfer complete flag.
431	* @param __HANDLE__ DMA handle
432	* @retval The specified transfer complete flag index.
433	*/
434	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
435	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
436	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
437	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
438	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
439	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
440	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
441	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
442	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
443	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
444	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
445	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
446	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
447	DMA_FLAG_TCIF3_7)
448
449	/**
450	* @brief Return the current DMA Stream half transfer complete flag.
451	* @param __HANDLE__ DMA handle
452	* @retval The specified half transfer complete flag index.
453	*/
454	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
455	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
456	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
457	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
458	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
459	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
460	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
461	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
462	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
463	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
464	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
465	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
466	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
467	DMA_FLAG_HTIF3_7)
468
469	/**
470	* @brief Return the current DMA Stream transfer error flag.
471	* @param __HANDLE__ DMA handle
472	* @retval The specified transfer error flag index.
473	*/
474	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
475	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
476	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
477	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
478	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
479	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
480	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
481	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
482	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
483	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
484	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
485	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
486	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
487	DMA_FLAG_TEIF3_7)
488
489	/**
490	* @brief Return the current DMA Stream FIFO error flag.
491	* @param __HANDLE__ DMA handle
492	* @retval The specified FIFO error flag index.
493	*/
494	#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
495	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
496	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
497	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
498	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
499	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
500	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
501	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
502	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
503	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
504	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
505	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
506	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
507	DMA_FLAG_FEIF3_7)
508
509	/**
510	* @brief Return the current DMA Stream direct mode error flag.
511	* @param __HANDLE__ DMA handle
512	* @retval The specified direct mode error flag index.
513	*/
514	#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
515	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
516	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
517	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
518	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
519	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
520	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
521	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
522	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
523	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
524	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
525	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
526	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
527	DMA_FLAG_DMEIF3_7)
528
529	/**
530	* @brief Get the DMA Stream pending flags.
531	* @param __HANDLE__ DMA handle
532	* @param __FLAG__ Get the specified flag.
533	* This parameter can be any combination of the following values:
534	* @arg DMA_FLAG_TCIFx: Transfer complete flag.
535	* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
536	* @arg DMA_FLAG_TEIFx: Transfer error flag.
537	* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
538	* @arg DMA_FLAG_FEIFx: FIFO error flag.
539	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
540	* @retval The state of FLAG (SET or RESET).
541	*/
542	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
543	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
544	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
545	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
546
547	/**
548	* @brief Clear the DMA Stream pending flags.
549	* @param __HANDLE__ DMA handle
550	* @param __FLAG__ specifies the flag to clear.
551	* This parameter can be any combination of the following values:
552	* @arg DMA_FLAG_TCIFx: Transfer complete flag.
553	* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
554	* @arg DMA_FLAG_TEIFx: Transfer error flag.
555	* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
556	* @arg DMA_FLAG_FEIFx: FIFO error flag.
557	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
558	* @retval None
559	*/
560	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
561	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
562	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
563	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
564
565	/**
566	* @brief Enable the specified DMA Stream interrupts.
567	* @param __HANDLE__ DMA handle
568	* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
569	* This parameter can be any combination of the following values:
570	* @arg DMA_IT_TC: Transfer complete interrupt mask.
571	* @arg DMA_IT_HT: Half transfer complete interrupt mask.
572	* @arg DMA_IT_TE: Transfer error interrupt mask.
573	* @arg DMA_IT_FE: FIFO error interrupt mask.
574	* @arg DMA_IT_DME: Direct mode error interrupt.
575	* @retval None
576	*/
577	#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
578	((__HANDLE__)->Instance->CR \|= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR \|= (__INTERRUPT__)))
579
580	/**
581	* @brief Disable the specified DMA Stream interrupts.
582	* @param __HANDLE__ DMA handle
583	* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
584	* This parameter can be any combination of the following values:
585	* @arg DMA_IT_TC: Transfer complete interrupt mask.
586	* @arg DMA_IT_HT: Half transfer complete interrupt mask.
587	* @arg DMA_IT_TE: Transfer error interrupt mask.
588	* @arg DMA_IT_FE: FIFO error interrupt mask.
589	* @arg DMA_IT_DME: Direct mode error interrupt.
590	* @retval None
591	*/
592	#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
593	((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
594
595	/**
596	* @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
597	* @param __HANDLE__ DMA handle
598	* @param __INTERRUPT__ specifies the DMA interrupt source to check.
599	* This parameter can be one of the following values:
600	* @arg DMA_IT_TC: Transfer complete interrupt mask.
601	* @arg DMA_IT_HT: Half transfer complete interrupt mask.
602	* @arg DMA_IT_TE: Transfer error interrupt mask.
603	* @arg DMA_IT_FE: FIFO error interrupt mask.
604	* @arg DMA_IT_DME: Direct mode error interrupt.
605	* @retval The state of DMA_IT.
606	*/
607	#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
608	((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
609	((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
610
611	/**
612	* @brief Writes the number of data units to be transferred on the DMA Stream.
613	* @param __HANDLE__ DMA handle
614	* @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
615	* Number of data items depends only on the Peripheral data format.
616	*
617	* @note If Peripheral data format is Bytes: number of data units is equal
618	* to total number of bytes to be transferred.
619	*
620	* @note If Peripheral data format is Half-Word: number of data units is
621	* equal to total number of bytes to be transferred / 2.
622	*
623	* @note If Peripheral data format is Word: number of data units is equal
624	* to total number of bytes to be transferred / 4.
625	*
626	* @retval The number of remaining data units in the current DMAy Streamx transfer.
627	*/
628	#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
629
630	/**
631	* @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
632	* @param __HANDLE__ DMA handle
633	*
634	* @retval The number of remaining data units in the current DMA Stream transfer.
635	*/
636	#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
637
638
639	/* Include DMA HAL Extension module */
640	#include "stm32f4xx_hal_dma_ex.h"
641
642	/* Exported functions --------------------------------------------------------*/
643
644	/** @defgroup DMA_Exported_Functions DMA Exported Functions
645	* @brief DMA Exported functions
646	* @{
647	*/
648
649	/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
650	* @brief Initialization and de-initialization functions
651	* @{
652	*/
653	HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
654	HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
655	/**
656	* @}
657	*/
658
659	/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
660	* @brief I/O operation functions
661	* @{
662	*/
663	HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
664	HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
665	HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
666	HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
667	HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
668	void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
669	HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
670	HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void ( pCallback)(DMA_HandleTypeDef *_hdma));
671	HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
672
673	/**
674	* @}
675	*/
676
677	/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
678	* @brief Peripheral State functions
679	* @{
680	*/
681	HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
682	uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
683	/**
684	* @}
685	*/
686	/**
687	* @}
688	*/
689	/* Private Constants -------------------------------------------------------------*/
690	/** @defgroup DMA_Private_Constants DMA Private Constants
691	* @brief DMA private defines and constants
692	* @{
693	*/
694	/**
695	* @}
696	*/
697
698	/* Private macros ------------------------------------------------------------*/
699	/** @defgroup DMA_Private_Macros DMA Private Macros
700	* @brief DMA private macros
701	* @{
702	*/
703	#if defined (DMA_SxCR_CHSEL_3)
704	#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) \|\| \
705	((CHANNEL) == DMA_CHANNEL_1) \|\| \
706	((CHANNEL) == DMA_CHANNEL_2) \|\| \
707	((CHANNEL) == DMA_CHANNEL_3) \|\| \
708	((CHANNEL) == DMA_CHANNEL_4) \|\| \
709	((CHANNEL) == DMA_CHANNEL_5) \|\| \
710	((CHANNEL) == DMA_CHANNEL_6) \|\| \
711	((CHANNEL) == DMA_CHANNEL_7) \|\| \
712	((CHANNEL) == DMA_CHANNEL_8) \|\| \
713	((CHANNEL) == DMA_CHANNEL_9) \|\| \
714	((CHANNEL) == DMA_CHANNEL_10)\|\| \
715	((CHANNEL) == DMA_CHANNEL_11)\|\| \
716	((CHANNEL) == DMA_CHANNEL_12)\|\| \
717	((CHANNEL) == DMA_CHANNEL_13)\|\| \
718	((CHANNEL) == DMA_CHANNEL_14)\|\| \
719	((CHANNEL) == DMA_CHANNEL_15))
720	#else
721	#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) \|\| \
722	((CHANNEL) == DMA_CHANNEL_1) \|\| \
723	((CHANNEL) == DMA_CHANNEL_2) \|\| \
724	((CHANNEL) == DMA_CHANNEL_3) \|\| \
725	((CHANNEL) == DMA_CHANNEL_4) \|\| \
726	((CHANNEL) == DMA_CHANNEL_5) \|\| \
727	((CHANNEL) == DMA_CHANNEL_6) \|\| \
728	((CHANNEL) == DMA_CHANNEL_7))
729	#endif /* DMA_SxCR_CHSEL_3 */
730
731	#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) \|\| \
732	((DIRECTION) == DMA_MEMORY_TO_PERIPH) \|\| \
733	((DIRECTION) == DMA_MEMORY_TO_MEMORY))
734
735	#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
736
737	#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) \|\| \
738	((STATE) == DMA_PINC_DISABLE))
739
740	#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) \|\| \
741	((STATE) == DMA_MINC_DISABLE))
742
743	#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) \|\| \
744	((SIZE) == DMA_PDATAALIGN_HALFWORD) \|\| \
745	((SIZE) == DMA_PDATAALIGN_WORD))
746
747	#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) \|\| \
748	((SIZE) == DMA_MDATAALIGN_HALFWORD) \|\| \
749	((SIZE) == DMA_MDATAALIGN_WORD ))
750
751	#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) \|\| \
752	((MODE) == DMA_CIRCULAR) \|\| \
753	((MODE) == DMA_PFCTRL))
754
755	#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) \|\| \
756	((PRIORITY) == DMA_PRIORITY_MEDIUM) \|\| \
757	((PRIORITY) == DMA_PRIORITY_HIGH) \|\| \
758	((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
759
760	#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) \|\| \
761	((STATE) == DMA_FIFOMODE_ENABLE))
762
763	#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) \|\| \
764	((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) \|\| \
765	((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) \|\| \
766	((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
767
768	#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) \|\| \
769	((BURST) == DMA_MBURST_INC4) \|\| \
770	((BURST) == DMA_MBURST_INC8) \|\| \
771	((BURST) == DMA_MBURST_INC16))
772
773	#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) \|\| \
774	((BURST) == DMA_PBURST_INC4) \|\| \
775	((BURST) == DMA_PBURST_INC8) \|\| \
776	((BURST) == DMA_PBURST_INC16))
777	/**
778	* @}
779	*/
780
781	/* Private functions ---------------------------------------------------------*/
782	/** @defgroup DMA_Private_Functions DMA Private Functions
783	* @brief DMA private functions
784	* @{
785	*/
786	/**
787	* @}
788	*/
789
790	/**
791	* @}
792	*/
793
794	/**
795	* @}
796	*/
797
798	#ifdef __cplusplus
799	}
800	#endif
801
802	#endif /* __STM32F4xx_HAL_DMA_H */
803
804	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h

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