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stm32f4xx_hal_dma2d.h

Last change on this file was 1, checked in by AlexLir, 3 years ago

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_hal_dma2d.h
4	* @author MCD Application Team
5	* @brief Header file of DMA2D HAL module.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19
20	/* Define to prevent recursive inclusion -------------------------------------*/
21	#ifndef STM32F4xx_HAL_DMA2D_H
22	#define STM32F4xx_HAL_DMA2D_H
23
24	#ifdef __cplusplus
25	extern "C" {
26	#endif
27
28	/* Includes ------------------------------------------------------------------*/
29	#include "stm32f4xx_hal_def.h"
30
31	/** @addtogroup STM32F4xx_HAL_Driver
32	* @{
33	*/
34
35	#if defined (DMA2D)
36
37	/** @addtogroup DMA2D DMA2D
38	* @brief DMA2D HAL module driver
39	* @{
40	*/
41
42	/* Exported types ------------------------------------------------------------*/
43	/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
44	* @{
45	*/
46	#define MAX_DMA2D_LAYER 2U /!< DMA2D maximum number of layers /
47
48	/**
49	* @brief DMA2D CLUT Structure definition
50	*/
51	typedef struct
52	{
53	uint32_t pCLUT; /!< Configures the DMA2D CLUT memory address.*/
54
55	uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
56	This parameter can be one value of @ref DMA2D_CLUT_CM. */
57
58	uint32_t Size; /*!< Configures the DMA2D CLUT size.
59	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
60	} DMA2D_CLUTCfgTypeDef;
61
62	/**
63	* @brief DMA2D Init structure definition
64	*/
65	typedef struct
66	{
67	uint32_t Mode; /*!< Configures the DMA2D transfer mode.
68	This parameter can be one value of @ref DMA2D_Mode. */
69
70	uint32_t ColorMode; /*!< Configures the color format of the output image.
71	This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
72
73	uint32_t OutputOffset; /*!< Specifies the Offset value.
74	This parameter must be a number between
75	Min_Data = 0x0000 and Max_Data = 0x3FFF. */
76
77
78
79
80	} DMA2D_InitTypeDef;
81
82
83	/**
84	* @brief DMA2D Layer structure definition
85	*/
86	typedef struct
87	{
88	uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
89	This parameter must be a number between
90	Min_Data = 0x0000 and Max_Data = 0x3FFF. */
91
92	uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
93	This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
94
95	uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
96	This parameter can be one value of @ref DMA2D_Alpha_Mode. */
97
98	uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value
99	in case of A8 or A4 color mode.
100	This parameter must be a number between Min_Data = 0x00
101	and Max_Data = 0xFF except for the color modes detailed below.
102	@note In case of A8 or A4 color mode (ARGB),
103	this parameter must be a number between
104	Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
105	- InputAlpha[24:31] is the alpha value ALPHA[0:7]
106	- InputAlpha[16:23] is the red value RED[0:7]
107	- InputAlpha[8:15] is the green value GREEN[0:7]
108	- InputAlpha[0:7] is the blue value BLUE[0:7]. */
109
110
111	} DMA2D_LayerCfgTypeDef;
112
113	/**
114	* @brief HAL DMA2D State structures definition
115	*/
116	typedef enum
117	{
118	HAL_DMA2D_STATE_RESET = 0x00U, /!< DMA2D not yet initialized or disabled /
119	HAL_DMA2D_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
120	HAL_DMA2D_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
121	HAL_DMA2D_STATE_TIMEOUT = 0x03U, /!< Timeout state /
122	HAL_DMA2D_STATE_ERROR = 0x04U, /!< DMA2D state error /
123	HAL_DMA2D_STATE_SUSPEND = 0x05U /!< DMA2D process is suspended /
124	} HAL_DMA2D_StateTypeDef;
125
126	/**
127	* @brief DMA2D handle Structure definition
128	*/
129	typedef struct __DMA2D_HandleTypeDef
130	{
131	DMA2D_TypeDef Instance; /!< DMA2D register base address. */
132
133	DMA2D_InitTypeDef Init; /!< DMA2D communication parameters. /
134
135	void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef hdma2d); /!< DMA2D transfer complete callback. */
136
137	void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef hdma2d); /!< DMA2D transfer error callback. */
138
139	#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
140	void (* LineEventCallback)(struct __DMA2D_HandleTypeDef hdma2d); /!< DMA2D line event callback. */
141
142	void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef hdma2d); /!< DMA2D CLUT loading completion callback */
143
144	void (* MspInitCallback)(struct __DMA2D_HandleTypeDef hdma2d); /!< DMA2D Msp Init callback. */
145
146	void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef hdma2d); /!< DMA2D Msp DeInit callback. */
147
148	#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
149
150	DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /!< DMA2D Layers parameters /
151
152	HAL_LockTypeDef Lock; /!< DMA2D lock. /
153
154	__IO HAL_DMA2D_StateTypeDef State; /!< DMA2D transfer state. /
155
156	__IO uint32_t ErrorCode; /!< DMA2D error code. /
157	} DMA2D_HandleTypeDef;
158
159	#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
160	/**
161	* @brief HAL DMA2D Callback pointer definition
162	*/
163	typedef void (pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef hdma2d); /!< Pointer to a DMA2D common callback function /
164	#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
165	/**
166	* @}
167	*/
168
169	/* Exported constants --------------------------------------------------------*/
170	/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
171	* @{
172	*/
173
174	/** @defgroup DMA2D_Error_Code DMA2D Error Code
175	* @{
176	*/
177	#define HAL_DMA2D_ERROR_NONE 0x00000000U /!< No error /
178	#define HAL_DMA2D_ERROR_TE 0x00000001U /!< Transfer error /
179	#define HAL_DMA2D_ERROR_CE 0x00000002U /!< Configuration error /
180	#define HAL_DMA2D_ERROR_CAE 0x00000004U /!< CLUT access error /
181	#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /!< Timeout error /
182	#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
183	#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /!< Invalid callback error /
184	#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
185
186	/**
187	* @}
188	*/
189
190	/** @defgroup DMA2D_Mode DMA2D Mode
191	* @{
192	*/
193	#define DMA2D_M2M 0x00000000U /!< DMA2D memory to memory transfer mode /
194	#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /!< DMA2D memory to memory with pixel format conversion transfer mode /
195	#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /!< DMA2D memory to memory with blending transfer mode /
196	#define DMA2D_R2M DMA2D_CR_MODE /!< DMA2D register to memory transfer mode /
197	/**
198	* @}
199	*/
200
201	/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
202	* @{
203	*/
204	#define DMA2D_OUTPUT_ARGB8888 0x00000000U /!< ARGB8888 DMA2D color mode /
205	#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /!< RGB888 DMA2D color mode /
206	#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /!< RGB565 DMA2D color mode /
207	#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0\|DMA2D_OPFCCR_CM_1) /!< ARGB1555 DMA2D color mode /
208	#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /!< ARGB4444 DMA2D color mode /
209	/**
210	* @}
211	*/
212
213	/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
214	* @{
215	*/
216	#define DMA2D_INPUT_ARGB8888 0x00000000U /!< ARGB8888 color mode /
217	#define DMA2D_INPUT_RGB888 0x00000001U /!< RGB888 color mode /
218	#define DMA2D_INPUT_RGB565 0x00000002U /!< RGB565 color mode /
219	#define DMA2D_INPUT_ARGB1555 0x00000003U /!< ARGB1555 color mode /
220	#define DMA2D_INPUT_ARGB4444 0x00000004U /!< ARGB4444 color mode /
221	#define DMA2D_INPUT_L8 0x00000005U /!< L8 color mode /
222	#define DMA2D_INPUT_AL44 0x00000006U /!< AL44 color mode /
223	#define DMA2D_INPUT_AL88 0x00000007U /!< AL88 color mode /
224	#define DMA2D_INPUT_L4 0x00000008U /!< L4 color mode /
225	#define DMA2D_INPUT_A8 0x00000009U /!< A8 color mode /
226	#define DMA2D_INPUT_A4 0x0000000AU /!< A4 color mode /
227	/**
228	* @}
229	*/
230
231	/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
232	* @{
233	*/
234	#define DMA2D_NO_MODIF_ALPHA 0x00000000U /!< No modification of the alpha channel value /
235	#define DMA2D_REPLACE_ALPHA 0x00000001U /!< Replace original alpha channel value by programmed alpha value /
236	#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
237	with original alpha channel value */
238	/**
239	* @}
240	*/
241
242
243
244
245
246
247	/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
248	* @{
249	*/
250	#define DMA2D_CCM_ARGB8888 0x00000000U /!< ARGB8888 DMA2D CLUT color mode /
251	#define DMA2D_CCM_RGB888 0x00000001U /!< RGB888 DMA2D CLUT color mode /
252	/**
253	* @}
254	*/
255
256	/** @defgroup DMA2D_Interrupts DMA2D Interrupts
257	* @{
258	*/
259	#define DMA2D_IT_CE DMA2D_CR_CEIE /!< Configuration Error Interrupt /
260	#define DMA2D_IT_CTC DMA2D_CR_CTCIE /!< CLUT Transfer Complete Interrupt /
261	#define DMA2D_IT_CAE DMA2D_CR_CAEIE /!< CLUT Access Error Interrupt /
262	#define DMA2D_IT_TW DMA2D_CR_TWIE /!< Transfer Watermark Interrupt /
263	#define DMA2D_IT_TC DMA2D_CR_TCIE /!< Transfer Complete Interrupt /
264	#define DMA2D_IT_TE DMA2D_CR_TEIE /!< Transfer Error Interrupt /
265	/**
266	* @}
267	*/
268
269	/** @defgroup DMA2D_Flags DMA2D Flags
270	* @{
271	*/
272	#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /!< Configuration Error Interrupt Flag /
273	#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /!< CLUT Transfer Complete Interrupt Flag /
274	#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /!< CLUT Access Error Interrupt Flag /
275	#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /!< Transfer Watermark Interrupt Flag /
276	#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /!< Transfer Complete Interrupt Flag /
277	#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /!< Transfer Error Interrupt Flag /
278	/**
279	* @}
280	*/
281
282	/** @defgroup DMA2D_Aliases DMA2D API Aliases
283	* @{
284	*/
285	#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
286	for compatibility with legacy code */
287	/**
288	* @}
289	*/
290
291	#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
292	/**
293	* @brief HAL DMA2D common Callback ID enumeration definition
294	*/
295	typedef enum
296	{
297	HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /!< DMA2D MspInit callback ID /
298	HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /!< DMA2D MspDeInit callback ID /
299	HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /!< DMA2D transfer complete callback ID /
300	HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /!< DMA2D transfer error callback ID /
301	HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /!< DMA2D line event callback ID /
302	HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /!< DMA2D CLUT loading completion callback ID /
303	} HAL_DMA2D_CallbackIDTypeDef;
304	#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
305
306
307	/**
308	* @}
309	*/
310	/* Exported macros ------------------------------------------------------------*/
311	/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
312	* @{
313	*/
314
315	/** @brief Reset DMA2D handle state
316	* @param __HANDLE__ specifies the DMA2D handle.
317	* @retval None
318	*/
319	#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
320	#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
321	(__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
322	(__HANDLE__)->MspInitCallback = NULL; \
323	(__HANDLE__)->MspDeInitCallback = NULL; \
324	}while(0)
325	#else
326	#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
327	#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
328
329
330	/**
331	* @brief Enable the DMA2D.
332	* @param __HANDLE__ DMA2D handle
333	* @retval None.
334	*/
335	#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= DMA2D_CR_START)
336
337
338	/* Interrupt & Flag management */
339	/**
340	* @brief Get the DMA2D pending flags.
341	* @param __HANDLE__ DMA2D handle
342	* @param __FLAG__ flag to check.
343	* This parameter can be any combination of the following values:
344	* @arg DMA2D_FLAG_CE: Configuration error flag
345	* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
346	* @arg DMA2D_FLAG_CAE: CLUT access error flag
347	* @arg DMA2D_FLAG_TW: Transfer Watermark flag
348	* @arg DMA2D_FLAG_TC: Transfer complete flag
349	* @arg DMA2D_FLAG_TE: Transfer error flag
350	* @retval The state of FLAG.
351	*/
352	#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
353
354	/**
355	* @brief Clear the DMA2D pending flags.
356	* @param __HANDLE__ DMA2D handle
357	* @param __FLAG__ specifies the flag to clear.
358	* This parameter can be any combination of the following values:
359	* @arg DMA2D_FLAG_CE: Configuration error flag
360	* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
361	* @arg DMA2D_FLAG_CAE: CLUT access error flag
362	* @arg DMA2D_FLAG_TW: Transfer Watermark flag
363	* @arg DMA2D_FLAG_TC: Transfer complete flag
364	* @arg DMA2D_FLAG_TE: Transfer error flag
365	* @retval None
366	*/
367	#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
368
369	/**
370	* @brief Enable the specified DMA2D interrupts.
371	* @param __HANDLE__ DMA2D handle
372	* @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.
373	* This parameter can be any combination of the following values:
374	* @arg DMA2D_IT_CE: Configuration error interrupt mask
375	* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
376	* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
377	* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
378	* @arg DMA2D_IT_TC: Transfer complete interrupt mask
379	* @arg DMA2D_IT_TE: Transfer error interrupt mask
380	* @retval None
381	*/
382	#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR \|= (__INTERRUPT__))
383
384	/**
385	* @brief Disable the specified DMA2D interrupts.
386	* @param __HANDLE__ DMA2D handle
387	* @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.
388	* This parameter can be any combination of the following values:
389	* @arg DMA2D_IT_CE: Configuration error interrupt mask
390	* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
391	* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
392	* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
393	* @arg DMA2D_IT_TC: Transfer complete interrupt mask
394	* @arg DMA2D_IT_TE: Transfer error interrupt mask
395	* @retval None
396	*/
397	#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
398
399	/**
400	* @brief Check whether the specified DMA2D interrupt source is enabled or not.
401	* @param __HANDLE__ DMA2D handle
402	* @param __INTERRUPT__ specifies the DMA2D interrupt source to check.
403	* This parameter can be one of the following values:
404	* @arg DMA2D_IT_CE: Configuration error interrupt mask
405	* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
406	* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
407	* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
408	* @arg DMA2D_IT_TC: Transfer complete interrupt mask
409	* @arg DMA2D_IT_TE: Transfer error interrupt mask
410	* @retval The state of INTERRUPT source.
411	*/
412	#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
413
414	/**
415	* @}
416	*/
417
418	/* Exported functions --------------------------------------------------------*/
419	/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
420	* @{
421	*/
422
423	/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
424	* @{
425	*/
426
427	/* Initialization and de-initialization functions *******************************/
428	HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
429	HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
430	void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
431	void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
432	/* Callbacks Register/UnRegister functions ***********************************/
433	#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
434	HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
435	pDMA2D_CallbackTypeDef pCallback);
436	HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
437	#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
438
439	/**
440	* @}
441	*/
442
443
444	/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
445	* @{
446	*/
447
448	/* IO operation functions *******************************************************/
449	HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
450	uint32_t Height);
451	HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
452	uint32_t DstAddress, uint32_t Width, uint32_t Height);
453	HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
454	uint32_t Height);
455	HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
456	uint32_t DstAddress, uint32_t Width, uint32_t Height);
457	HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
458	HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
459	HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
460	HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
461	HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg,
462	uint32_t LayerIdx);
463	HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg,
464	uint32_t LayerIdx);
465	HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
466	HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
467	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
468	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
469	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
470	HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
471	void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
472	void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
473	void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
474
475	/**
476	* @}
477	*/
478
479	/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
480	* @{
481	*/
482
483	/* Peripheral Control functions *************************************************/
484	HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
485	HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
486	HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
487	HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
488	HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
489	HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
490
491	/**
492	* @}
493	*/
494
495	/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
496	* @{
497	*/
498
499	/* Peripheral State functions ***************************************************/
500	HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
501	uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
502
503	/**
504	* @}
505	*/
506
507	/**
508	* @}
509	*/
510
511	/* Private constants ---------------------------------------------------------*/
512
513	/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
514	* @{
515	*/
516
517	/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
518	* @{
519	*/
520	#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /!< DMA2D maximum line watermark /
521	/**
522	* @}
523	*/
524
525	/** @defgroup DMA2D_Color_Value DMA2D Color Value
526	* @{
527	*/
528	#define DMA2D_COLOR_VALUE 0x000000FFU /!< Color value mask /
529	/**
530	* @}
531	*/
532
533	/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
534	* @{
535	*/
536	#define DMA2D_MAX_LAYER 2U /!< DMA2D maximum number of layers /
537	/**
538	* @}
539	*/
540
541	/** @defgroup DMA2D_Layers DMA2D Layers
542	* @{
543	*/
544	#define DMA2D_BACKGROUND_LAYER 0x00000000U /!< DMA2D Background Layer (layer 0) /
545	#define DMA2D_FOREGROUND_LAYER 0x00000001U /!< DMA2D Foreground Layer (layer 1) /
546	/**
547	* @}
548	*/
549
550	/** @defgroup DMA2D_Offset DMA2D Offset
551	* @{
552	*/
553	#define DMA2D_OFFSET DMA2D_FGOR_LO /!< maximum Line Offset /
554	/**
555	* @}
556	*/
557
558	/** @defgroup DMA2D_Size DMA2D Size
559	* @{
560	*/
561	#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /!< DMA2D maximum number of pixels per line /
562	#define DMA2D_LINE DMA2D_NLR_NL /!< DMA2D maximum number of lines /
563	/**
564	* @}
565	*/
566
567	/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
568	* @{
569	*/
570	#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /!< DMA2D maximum CLUT size /
571	/**
572	* @}
573	*/
574
575	/**
576	* @}
577	*/
578
579
580	/* Private macros ------------------------------------------------------------*/
581	/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
582	* @{
583	*/
584	#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
585	\|\| ((LAYER) == DMA2D_FOREGROUND_LAYER))
586
587	#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) \|\| ((MODE) == DMA2D_M2M_PFC) \|\| \
588	((MODE) == DMA2D_M2M_BLEND) \|\| ((MODE) == DMA2D_R2M))
589
590	#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) \|\| \
591	((MODE_ARGB) == DMA2D_OUTPUT_RGB888) \|\| \
592	((MODE_ARGB) == DMA2D_OUTPUT_RGB565) \|\| \
593	((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) \|\| \
594	((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
595
596	#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
597	#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
598	#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
599	#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
600
601	#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) \|\| \
602	((INPUT_CM) == DMA2D_INPUT_RGB888) \|\| \
603	((INPUT_CM) == DMA2D_INPUT_RGB565) \|\| \
604	((INPUT_CM) == DMA2D_INPUT_ARGB1555) \|\| \
605	((INPUT_CM) == DMA2D_INPUT_ARGB4444) \|\| \
606	((INPUT_CM) == DMA2D_INPUT_L8) \|\| \
607	((INPUT_CM) == DMA2D_INPUT_AL44) \|\| \
608	((INPUT_CM) == DMA2D_INPUT_AL88) \|\| \
609	((INPUT_CM) == DMA2D_INPUT_L4) \|\| \
610	((INPUT_CM) == DMA2D_INPUT_A8) \|\| \
611	((INPUT_CM) == DMA2D_INPUT_A4))
612
613	#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) \|\| \
614	((AlphaMode) == DMA2D_REPLACE_ALPHA) \|\| \
615	((AlphaMode) == DMA2D_COMBINE_ALPHA))
616
617
618
619
620
621	#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) \|\| ((CLUT_CM) == DMA2D_CCM_RGB888))
622	#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
623	#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
624	#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) \|\| ((IT) == DMA2D_IT_CAE) \|\| \
625	((IT) == DMA2D_IT_TW) \|\| ((IT) == DMA2D_IT_TC) \|\| \
626	((IT) == DMA2D_IT_TE) \|\| ((IT) == DMA2D_IT_CE))
627	#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) \|\| ((FLAG) == DMA2D_FLAG_CAE) \|\| \
628	((FLAG) == DMA2D_FLAG_TW) \|\| ((FLAG) == DMA2D_FLAG_TC) \|\| \
629	((FLAG) == DMA2D_FLAG_TE) \|\| ((FLAG) == DMA2D_FLAG_CE))
630	/**
631	* @}
632	*/
633
634	/**
635	* @}
636	*/
637
638	#endif /* defined (DMA2D) */
639
640	/**
641	* @}
642	*/
643
644	#ifdef __cplusplus
645	}
646	#endif
647
648	#endif /* STM32F4xx_HAL_DMA2D_H */
649
650
651	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h

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