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stm32f4xx_hal_dsi.h

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_hal_dsi.h
4	* @author MCD Application Team
5	* @brief Header file of DSI HAL module.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19
20	/* Define to prevent recursive inclusion -------------------------------------*/
21	#ifndef STM32F4xx_HAL_DSI_H
22	#define STM32F4xx_HAL_DSI_H
23
24	#ifdef __cplusplus
25	extern "C" {
26	#endif
27
28	/* Includes ------------------------------------------------------------------*/
29	#include "stm32f4xx_hal_def.h"
30
31	#if defined(DSI)
32
33	/** @addtogroup STM32F4xx_HAL_Driver
34	* @{
35	*/
36
37	/** @defgroup DSI DSI
38	* @brief DSI HAL module driver
39	* @{
40	*/
41
42	/* Exported types ------------------------------------------------------------*/
43	/**
44	* @brief DSI Init Structure definition
45	*/
46	typedef struct
47	{
48	uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
49	This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
50
51	uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
52	The values 0 and 1 stop the TX_ESC clock generation */
53
54	uint32_t NumberOfLanes; /*!< Number of lanes
55	This parameter can be any value of @ref DSI_Number_Of_Lanes */
56
57	} DSI_InitTypeDef;
58
59	/**
60	* @brief DSI PLL Clock structure definition
61	*/
62	typedef struct
63	{
64	uint32_t PLLNDIV; /*!< PLL Loop Division Factor
65	This parameter must be a value between 10 and 125 */
66
67	uint32_t PLLIDF; /*!< PLL Input Division Factor
68	This parameter can be any value of @ref DSI_PLL_IDF */
69
70	uint32_t PLLODF; /*!< PLL Output Division Factor
71	This parameter can be any value of @ref DSI_PLL_ODF */
72
73	} DSI_PLLInitTypeDef;
74
75	/**
76	* @brief DSI Video mode configuration
77	*/
78	typedef struct
79	{
80	uint32_t VirtualChannelID; /!< Virtual channel ID /
81
82	uint32_t ColorCoding; /*!< Color coding for LTDC interface
83	This parameter can be any value of @ref DSI_Color_Coding */
84
85	uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
86	18-bit configuration).
87	This parameter can be any value of @ref DSI_LooselyPacked */
88
89	uint32_t Mode; /*!< Video mode type
90	This parameter can be any value of @ref DSI_Video_Mode_Type */
91
92	uint32_t PacketSize; /!< Video packet size /
93
94	uint32_t NumberOfChunks; /!< Number of chunks /
95
96	uint32_t NullPacketSize; /!< Null packet size /
97
98	uint32_t HSPolarity; /*!< HSYNC pin polarity
99	This parameter can be any value of @ref DSI_HSYNC_Polarity */
100
101	uint32_t VSPolarity; /*!< VSYNC pin polarity
102	This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
103
104	uint32_t DEPolarity; /*!< Data Enable pin polarity
105	This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
106
107	uint32_t HorizontalSyncActive; /!< Horizontal synchronism active duration (in lane byte clock cycles) /
108
109	uint32_t HorizontalBackPorch; /!< Horizontal back-porch duration (in lane byte clock cycles) /
110
111	uint32_t HorizontalLine; /!< Horizontal line duration (in lane byte clock cycles) /
112
113	uint32_t VerticalSyncActive; /!< Vertical synchronism active duration /
114
115	uint32_t VerticalBackPorch; /!< Vertical back-porch duration /
116
117	uint32_t VerticalFrontPorch; /!< Vertical front-porch duration /
118
119	uint32_t VerticalActive; /!< Vertical active duration /
120
121	uint32_t LPCommandEnable; /*!< Low-power command enable
122	This parameter can be any value of @ref DSI_LP_Command */
123
124	uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
125	can fit in a line during VSA, VBP and VFP regions */
126
127	uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
128	can fit in a line during VACT region */
129
130	uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
131	This parameter can be any value of @ref DSI_LP_HFP */
132
133	uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
134	This parameter can be any value of @ref DSI_LP_HBP */
135
136	uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
137	This parameter can be any value of @ref DSI_LP_VACT */
138
139	uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
140	This parameter can be any value of @ref DSI_LP_VFP */
141
142	uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
143	This parameter can be any value of @ref DSI_LP_VBP */
144
145	uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
146	This parameter can be any value of @ref DSI_LP_VSYNC */
147
148	uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
149	This parameter can be any value of @ref DSI_FBTA_acknowledge */
150
151	} DSI_VidCfgTypeDef;
152
153	/**
154	* @brief DSI Adapted command mode configuration
155	*/
156	typedef struct
157	{
158	uint32_t VirtualChannelID; /!< Virtual channel ID /
159
160	uint32_t ColorCoding; /*!< Color coding for LTDC interface
161	This parameter can be any value of @ref DSI_Color_Coding */
162
163	uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
164	pixels. This parameter can be any value between 0x00 and 0xFFFFU */
165
166	uint32_t TearingEffectSource; /*!< Tearing effect source
167	This parameter can be any value of @ref DSI_TearingEffectSource */
168
169	uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
170	This parameter can be any value of @ref DSI_TearingEffectPolarity */
171
172	uint32_t HSPolarity; /*!< HSYNC pin polarity
173	This parameter can be any value of @ref DSI_HSYNC_Polarity */
174
175	uint32_t VSPolarity; /*!< VSYNC pin polarity
176	This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
177
178	uint32_t DEPolarity; /*!< Data Enable pin polarity
179	This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
180
181	uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
182	This parameter can be any value of @ref DSI_Vsync_Polarity */
183
184	uint32_t AutomaticRefresh; /*!< Automatic refresh mode
185	This parameter can be any value of @ref DSI_AutomaticRefresh */
186
187	uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
188	This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
189
190	} DSI_CmdCfgTypeDef;
191
192	/**
193	* @brief DSI command transmission mode configuration
194	*/
195	typedef struct
196	{
197	uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
198	This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
199
200	uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
201	This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
202
203	uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
204	This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
205
206	uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
207	This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
208
209	uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
210	This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
211
212	uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
213	This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
214
215	uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
216	This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
217
218	uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
219	This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
220
221	uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
222	This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
223
224	uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
225	This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
226
227	uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
228	This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
229
230	uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
231	This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
232
233	uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
234	This parameter can be any value of @ref DSI_AcknowledgeRequest */
235
236	} DSI_LPCmdTypeDef;
237
238	/**
239	* @brief DSI PHY Timings definition
240	*/
241	typedef struct
242	{
243	uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
244	to low-power transmission */
245
246	uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
247	to high-speed transmission */
248
249	uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
250	to low-power transmission */
251
252	uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
253	to high-speed transmission */
254
255	uint32_t DataLaneMaxReadTime; /!< The maximum time required to perform a read command /
256
257	uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
258	Stop state */
259
260	} DSI_PHY_TimerTypeDef;
261
262	/**
263	* @brief DSI HOST Timeouts definition
264	*/
265	typedef struct
266	{
267	uint32_t TimeoutCkdiv; /!< Time-out clock division /
268
269	uint32_t HighSpeedTransmissionTimeout; /!< High-speed transmission time-out /
270
271	uint32_t LowPowerReceptionTimeout; /!< Low-power reception time-out /
272
273	uint32_t HighSpeedReadTimeout; /!< High-speed read time-out /
274
275	uint32_t LowPowerReadTimeout; /!< Low-power read time-out /
276
277	uint32_t HighSpeedWriteTimeout; /!< High-speed write time-out /
278
279	uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
280	This parameter can be any value of @ref DSI_HS_PrespMode */
281
282	uint32_t LowPowerWriteTimeout; /!< Low-speed write time-out /
283
284	uint32_t BTATimeout; /!< BTA time-out /
285
286	} DSI_HOST_TimeoutTypeDef;
287
288	/**
289	* @brief DSI States Structure definition
290	*/
291	typedef enum
292	{
293	HAL_DSI_STATE_RESET = 0x00U,
294	HAL_DSI_STATE_READY = 0x01U,
295	HAL_DSI_STATE_ERROR = 0x02U,
296	HAL_DSI_STATE_BUSY = 0x03U,
297	HAL_DSI_STATE_TIMEOUT = 0x04U
298	} HAL_DSI_StateTypeDef;
299
300	/**
301	* @brief DSI Handle Structure definition
302	*/
303	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
304	typedef struct __DSI_HandleTypeDef
305	#else
306	typedef struct
307	#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
308	{
309	DSI_TypeDef Instance; /!< Register base address */
310	DSI_InitTypeDef Init; /!< DSI required parameters /
311	HAL_LockTypeDef Lock; /!< DSI peripheral status /
312	__IO HAL_DSI_StateTypeDef State; /!< DSI communication state /
313	__IO uint32_t ErrorCode; /!< DSI Error code /
314	uint32_t ErrorMsk; /!< DSI Error monitoring mask /
315
316	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
317	void (* TearingEffectCallback)(struct __DSI_HandleTypeDef hdsi); /!< DSI Tearing Effect Callback */
318	void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef hdsi); /!< DSI End Of Refresh Callback */
319	void (* ErrorCallback)(struct __DSI_HandleTypeDef hdsi); /!< DSI Error Callback */
320
321	void (* MspInitCallback)(struct __DSI_HandleTypeDef hdsi); /!< DSI Msp Init callback */
322	void (* MspDeInitCallback)(struct __DSI_HandleTypeDef hdsi); /!< DSI Msp DeInit callback */
323
324	#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
325
326	} DSI_HandleTypeDef;
327
328	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
329	/**
330	* @brief HAL DSI Callback ID enumeration definition
331	*/
332	typedef enum
333	{
334	HAL_DSI_MSPINIT_CB_ID = 0x00U, /!< DSI MspInit callback ID /
335	HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /!< DSI MspDeInit callback ID /
336
337	HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /!< DSI Tearing Effect Callback ID /
338	HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /!< DSI End Of Refresh Callback ID /
339	HAL_DSI_ERROR_CB_ID = 0x04U /!< DSI Error Callback ID /
340
341	} HAL_DSI_CallbackIDTypeDef;
342
343	/**
344	* @brief HAL DSI Callback pointer definition
345	*/
346	typedef void (pDSI_CallbackTypeDef)(DSI_HandleTypeDef hdsi); /!< pointer to an DSI callback function /
347
348	#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
349
350	/* Exported constants --------------------------------------------------------*/
351	/** @defgroup DSI_Exported_Constants DSI Exported Constants
352	* @{
353	*/
354	/** @defgroup DSI_DCS_Command DSI DCS Command
355	* @{
356	*/
357	#define DSI_ENTER_IDLE_MODE 0x39U
358	#define DSI_ENTER_INVERT_MODE 0x21U
359	#define DSI_ENTER_NORMAL_MODE 0x13U
360	#define DSI_ENTER_PARTIAL_MODE 0x12U
361	#define DSI_ENTER_SLEEP_MODE 0x10U
362	#define DSI_EXIT_IDLE_MODE 0x38U
363	#define DSI_EXIT_INVERT_MODE 0x20U
364	#define DSI_EXIT_SLEEP_MODE 0x11U
365	#define DSI_GET_3D_CONTROL 0x3FU
366	#define DSI_GET_ADDRESS_MODE 0x0BU
367	#define DSI_GET_BLUE_CHANNEL 0x08U
368	#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
369	#define DSI_GET_DISPLAY_MODE 0x0DU
370	#define DSI_GET_GREEN_CHANNEL 0x07U
371	#define DSI_GET_PIXEL_FORMAT 0x0CU
372	#define DSI_GET_POWER_MODE 0x0AU
373	#define DSI_GET_RED_CHANNEL 0x06U
374	#define DSI_GET_SCANLINE 0x45U
375	#define DSI_GET_SIGNAL_MODE 0x0EU
376	#define DSI_NOP 0x00U
377	#define DSI_READ_DDB_CONTINUE 0xA8U
378	#define DSI_READ_DDB_START 0xA1U
379	#define DSI_READ_MEMORY_CONTINUE 0x3EU
380	#define DSI_READ_MEMORY_START 0x2EU
381	#define DSI_SET_3D_CONTROL 0x3DU
382	#define DSI_SET_ADDRESS_MODE 0x36U
383	#define DSI_SET_COLUMN_ADDRESS 0x2AU
384	#define DSI_SET_DISPLAY_OFF 0x28U
385	#define DSI_SET_DISPLAY_ON 0x29U
386	#define DSI_SET_GAMMA_CURVE 0x26U
387	#define DSI_SET_PAGE_ADDRESS 0x2BU
388	#define DSI_SET_PARTIAL_COLUMNS 0x31U
389	#define DSI_SET_PARTIAL_ROWS 0x30U
390	#define DSI_SET_PIXEL_FORMAT 0x3AU
391	#define DSI_SET_SCROLL_AREA 0x33U
392	#define DSI_SET_SCROLL_START 0x37U
393	#define DSI_SET_TEAR_OFF 0x34U
394	#define DSI_SET_TEAR_ON 0x35U
395	#define DSI_SET_TEAR_SCANLINE 0x44U
396	#define DSI_SET_VSYNC_TIMING 0x40U
397	#define DSI_SOFT_RESET 0x01U
398	#define DSI_WRITE_LUT 0x2DU
399	#define DSI_WRITE_MEMORY_CONTINUE 0x3CU
400	#define DSI_WRITE_MEMORY_START 0x2CU
401	/**
402	* @}
403	*/
404
405	/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
406	* @{
407	*/
408	#define DSI_VID_MODE_NB_PULSES 0U
409	#define DSI_VID_MODE_NB_EVENTS 1U
410	#define DSI_VID_MODE_BURST 2U
411	/**
412	* @}
413	*/
414
415	/** @defgroup DSI_Color_Mode DSI Color Mode
416	* @{
417	*/
418	#define DSI_COLOR_MODE_FULL 0x00000000U
419	#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
420	/**
421	* @}
422	*/
423
424	/** @defgroup DSI_ShutDown DSI ShutDown
425	* @{
426	*/
427	#define DSI_DISPLAY_ON 0x00000000U
428	#define DSI_DISPLAY_OFF DSI_WCR_SHTDN
429	/**
430	* @}
431	*/
432
433	/** @defgroup DSI_LP_Command DSI LP Command
434	* @{
435	*/
436	#define DSI_LP_COMMAND_DISABLE 0x00000000U
437	#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
438	/**
439	* @}
440	*/
441
442	/** @defgroup DSI_LP_HFP DSI LP HFP
443	* @{
444	*/
445	#define DSI_LP_HFP_DISABLE 0x00000000U
446	#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
447	/**
448	* @}
449	*/
450
451	/** @defgroup DSI_LP_HBP DSI LP HBP
452	* @{
453	*/
454	#define DSI_LP_HBP_DISABLE 0x00000000U
455	#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
456	/**
457	* @}
458	*/
459
460	/** @defgroup DSI_LP_VACT DSI LP VACT
461	* @{
462	*/
463	#define DSI_LP_VACT_DISABLE 0x00000000U
464	#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
465	/**
466	* @}
467	*/
468
469	/** @defgroup DSI_LP_VFP DSI LP VFP
470	* @{
471	*/
472	#define DSI_LP_VFP_DISABLE 0x00000000U
473	#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
474	/**
475	* @}
476	*/
477
478	/** @defgroup DSI_LP_VBP DSI LP VBP
479	* @{
480	*/
481	#define DSI_LP_VBP_DISABLE 0x00000000U
482	#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
483	/**
484	* @}
485	*/
486
487	/** @defgroup DSI_LP_VSYNC DSI LP VSYNC
488	* @{
489	*/
490	#define DSI_LP_VSYNC_DISABLE 0x00000000U
491	#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
492	/**
493	* @}
494	*/
495
496	/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
497	* @{
498	*/
499	#define DSI_FBTAA_DISABLE 0x00000000U
500	#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
501	/**
502	* @}
503	*/
504
505	/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
506	* @{
507	*/
508	#define DSI_TE_DSILINK 0x00000000U
509	#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
510	/**
511	* @}
512	*/
513
514	/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
515	* @{
516	*/
517	#define DSI_TE_RISING_EDGE 0x00000000U
518	#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
519	/**
520	* @}
521	*/
522
523	/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
524	* @{
525	*/
526	#define DSI_VSYNC_FALLING 0x00000000U
527	#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
528	/**
529	* @}
530	*/
531
532	/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
533	* @{
534	*/
535	#define DSI_AR_DISABLE 0x00000000U
536	#define DSI_AR_ENABLE DSI_WCFGR_AR
537	/**
538	* @}
539	*/
540
541	/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
542	* @{
543	*/
544	#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
545	#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
546	/**
547	* @}
548	*/
549
550	/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
551	* @{
552	*/
553	#define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
554	#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
555	/**
556	* @}
557	*/
558
559	/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
560	* @{
561	*/
562	#define DSI_LP_GSW0P_DISABLE 0x00000000U
563	#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
564	/**
565	* @}
566	*/
567
568	/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
569	* @{
570	*/
571	#define DSI_LP_GSW1P_DISABLE 0x00000000U
572	#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
573	/**
574	* @}
575	*/
576
577	/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
578	* @{
579	*/
580	#define DSI_LP_GSW2P_DISABLE 0x00000000U
581	#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
582	/**
583	* @}
584	*/
585
586	/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
587	* @{
588	*/
589	#define DSI_LP_GSR0P_DISABLE 0x00000000U
590	#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
591	/**
592	* @}
593	*/
594
595	/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
596	* @{
597	*/
598	#define DSI_LP_GSR1P_DISABLE 0x00000000U
599	#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
600	/**
601	* @}
602	*/
603
604	/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
605	* @{
606	*/
607	#define DSI_LP_GSR2P_DISABLE 0x00000000U
608	#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
609	/**
610	* @}
611	*/
612
613	/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
614	* @{
615	*/
616	#define DSI_LP_GLW_DISABLE 0x00000000U
617	#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
618	/**
619	* @}
620	*/
621
622	/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
623	* @{
624	*/
625	#define DSI_LP_DSW0P_DISABLE 0x00000000U
626	#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
627	/**
628	* @}
629	*/
630
631	/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
632	* @{
633	*/
634	#define DSI_LP_DSW1P_DISABLE 0x00000000U
635	#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
636	/**
637	* @}
638	*/
639
640	/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
641	* @{
642	*/
643	#define DSI_LP_DSR0P_DISABLE 0x00000000U
644	#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
645	/**
646	* @}
647	*/
648
649	/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
650	* @{
651	*/
652	#define DSI_LP_DLW_DISABLE 0x00000000U
653	#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
654	/**
655	* @}
656	*/
657
658	/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
659	* @{
660	*/
661	#define DSI_LP_MRDP_DISABLE 0x00000000U
662	#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
663	/**
664	* @}
665	*/
666
667	/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
668	* @{
669	*/
670	#define DSI_HS_PM_DISABLE 0x00000000U
671	#define DSI_HS_PM_ENABLE DSI_TCCR3_PM
672	/**
673	* @}
674	*/
675
676
677	/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
678	* @{
679	*/
680	#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
681	#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
682	/**
683	* @}
684	*/
685
686	/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
687	* @{
688	*/
689	#define DSI_ONE_DATA_LANE 0U
690	#define DSI_TWO_DATA_LANES 1U
691	/**
692	* @}
693	*/
694
695	/** @defgroup DSI_FlowControl DSI Flow Control
696	* @{
697	*/
698	#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
699	#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
700	#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
701	#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
702	#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
703	#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX \| DSI_FLOW_CONTROL_ECC_RX \| \
704	DSI_FLOW_CONTROL_BTA \| DSI_FLOW_CONTROL_EOTP_RX \| \
705	DSI_FLOW_CONTROL_EOTP_TX)
706	/**
707	* @}
708	*/
709
710	/** @defgroup DSI_Color_Coding DSI Color Coding
711	* @{
712	*/
713	#define DSI_RGB565 0x00000000U /!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration /
714	#define DSI_RGB666 0x00000003U /!< The value 0x00000004 can also be used for the RGB666 color mode configuration /
715	#define DSI_RGB888 0x00000005U
716	/**
717	* @}
718	*/
719
720	/** @defgroup DSI_LooselyPacked DSI Loosely Packed
721	* @{
722	*/
723	#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
724	#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
725	/**
726	* @}
727	*/
728
729	/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
730	* @{
731	*/
732	#define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
733	#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
734	/**
735	* @}
736	*/
737
738	/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
739	* @{
740	*/
741	#define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
742	#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
743	/**
744	* @}
745	*/
746
747	/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
748	* @{
749	*/
750	#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
751	#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
752	/**
753	* @}
754	*/
755
756	/** @defgroup DSI_PLL_IDF DSI PLL IDF
757	* @{
758	*/
759	#define DSI_PLL_IN_DIV1 0x00000001U
760	#define DSI_PLL_IN_DIV2 0x00000002U
761	#define DSI_PLL_IN_DIV3 0x00000003U
762	#define DSI_PLL_IN_DIV4 0x00000004U
763	#define DSI_PLL_IN_DIV5 0x00000005U
764	#define DSI_PLL_IN_DIV6 0x00000006U
765	#define DSI_PLL_IN_DIV7 0x00000007U
766	/**
767	* @}
768	*/
769
770	/** @defgroup DSI_PLL_ODF DSI PLL ODF
771	* @{
772	*/
773	#define DSI_PLL_OUT_DIV1 0x00000000U
774	#define DSI_PLL_OUT_DIV2 0x00000001U
775	#define DSI_PLL_OUT_DIV4 0x00000002U
776	#define DSI_PLL_OUT_DIV8 0x00000003U
777	/**
778	* @}
779	*/
780
781	/** @defgroup DSI_Flags DSI Flags
782	* @{
783	*/
784	#define DSI_FLAG_TE DSI_WISR_TEIF
785	#define DSI_FLAG_ER DSI_WISR_ERIF
786	#define DSI_FLAG_BUSY DSI_WISR_BUSY
787	#define DSI_FLAG_PLLLS DSI_WISR_PLLLS
788	#define DSI_FLAG_PLLL DSI_WISR_PLLLIF
789	#define DSI_FLAG_PLLU DSI_WISR_PLLUIF
790	#define DSI_FLAG_RRS DSI_WISR_RRS
791	#define DSI_FLAG_RR DSI_WISR_RRIF
792	/**
793	* @}
794	*/
795
796	/** @defgroup DSI_Interrupts DSI Interrupts
797	* @{
798	*/
799	#define DSI_IT_TE DSI_WIER_TEIE
800	#define DSI_IT_ER DSI_WIER_ERIE
801	#define DSI_IT_PLLL DSI_WIER_PLLLIE
802	#define DSI_IT_PLLU DSI_WIER_PLLUIE
803	#define DSI_IT_RR DSI_WIER_RRIE
804	/**
805	* @}
806	*/
807
808	/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
809	* @{
810	*/
811	#define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /!< DCS short write, no parameters /
812	#define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /!< DCS short write, one parameter /
813	#define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /!< Generic short write, no parameters /
814	#define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /!< Generic short write, one parameter /
815	#define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /!< Generic short write, two parameters /
816	/**
817	* @}
818	*/
819
820	/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
821	* @{
822	*/
823	#define DSI_DCS_LONG_PKT_WRITE 0x00000039U /!< DCS long write /
824	#define DSI_GEN_LONG_PKT_WRITE 0x00000029U /!< Generic long write /
825	/**
826	* @}
827	*/
828
829	/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
830	* @{
831	*/
832	#define DSI_DCS_SHORT_PKT_READ 0x00000006U /!< DCS short read /
833	#define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /!< Generic short read, no parameters /
834	#define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /!< Generic short read, one parameter /
835	#define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /!< Generic short read, two parameters /
836	/**
837	* @}
838	*/
839
840	/** @defgroup DSI_Error_Data_Type DSI Error Data Type
841	* @{
842	*/
843	#define HAL_DSI_ERROR_NONE 0U
844	#define HAL_DSI_ERROR_ACK 0x00000001U /!< acknowledge errors /
845	#define HAL_DSI_ERROR_PHY 0x00000002U /!< PHY related errors /
846	#define HAL_DSI_ERROR_TX 0x00000004U /!< transmission error /
847	#define HAL_DSI_ERROR_RX 0x00000008U /!< reception error /
848	#define HAL_DSI_ERROR_ECC 0x00000010U /!< ECC errors /
849	#define HAL_DSI_ERROR_CRC 0x00000020U /!< CRC error /
850	#define HAL_DSI_ERROR_PSE 0x00000040U /!< Packet Size error /
851	#define HAL_DSI_ERROR_EOT 0x00000080U /!< End Of Transmission error /
852	#define HAL_DSI_ERROR_OVF 0x00000100U /!< FIFO overflow error /
853	#define HAL_DSI_ERROR_GEN 0x00000200U /!< Generic FIFO related errors /
854	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
855	#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /!< DSI Invalid Callback error /
856	#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
857	/**
858	* @}
859	*/
860
861	/** @defgroup DSI_Lane_Group DSI Lane Group
862	* @{
863	*/
864	#define DSI_CLOCK_LANE 0x00000000U
865	#define DSI_DATA_LANES 0x00000001U
866	/**
867	* @}
868	*/
869
870	/** @defgroup DSI_Communication_Delay DSI Communication Delay
871	* @{
872	*/
873	#define DSI_SLEW_RATE_HSTX 0x00000000U
874	#define DSI_SLEW_RATE_LPTX 0x00000001U
875	#define DSI_HS_DELAY 0x00000002U
876	/**
877	* @}
878	*/
879
880	/** @defgroup DSI_CustomLane DSI CustomLane
881	* @{
882	*/
883	#define DSI_SWAP_LANE_PINS 0x00000000U
884	#define DSI_INVERT_HS_SIGNAL 0x00000001U
885	/**
886	* @}
887	*/
888
889	/** @defgroup DSI_Lane_Select DSI Lane Select
890	* @{
891	*/
892	#define DSI_CLK_LANE 0x00000000U
893	#define DSI_DATA_LANE0 0x00000001U
894	#define DSI_DATA_LANE1 0x00000002U
895	/**
896	* @}
897	*/
898
899	/** @defgroup DSI_PHY_Timing DSI PHY Timing
900	* @{
901	*/
902	#define DSI_TCLK_POST 0x00000000U
903	#define DSI_TLPX_CLK 0x00000001U
904	#define DSI_THS_EXIT 0x00000002U
905	#define DSI_TLPX_DATA 0x00000003U
906	#define DSI_THS_ZERO 0x00000004U
907	#define DSI_THS_TRAIL 0x00000005U
908	#define DSI_THS_PREPARE 0x00000006U
909	#define DSI_TCLK_ZERO 0x00000007U
910	#define DSI_TCLK_PREPARE 0x00000008U
911	/**
912	* @}
913	*/
914
915	/**
916	* @}
917	*/
918
919	/* Exported macros -----------------------------------------------------------*/
920	/** @defgroup DSI_Exported_Macros DSI Exported Macros
921	* @{
922	*/
923
924	/**
925	* @brief Reset DSI handle state.
926	* @param __HANDLE__ DSI handle
927	* @retval None
928	*/
929	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
930	#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
931	(__HANDLE__)->State = HAL_DSI_STATE_RESET; \
932	(__HANDLE__)->MspInitCallback = NULL; \
933	(__HANDLE__)->MspDeInitCallback = NULL; \
934	} while(0)
935	#else
936	#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
937	#endif /USE_HAL_DSI_REGISTER_CALLBACKS /
938
939	/**
940	* @brief Enables the DSI host.
941	* @param __HANDLE__ DSI handle
942	* @retval None.
943	*/
944	#define __HAL_DSI_ENABLE(__HANDLE__) do { \
945	__IO uint32_t tmpreg = 0x00U; \
946	SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
947	/* Delay after an DSI Host enabling */ \
948	tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
949	UNUSED(tmpreg); \
950	} while(0U)
951
952	/**
953	* @brief Disables the DSI host.
954	* @param __HANDLE__ DSI handle
955	* @retval None.
956	*/
957	#define __HAL_DSI_DISABLE(__HANDLE__) do { \
958	__IO uint32_t tmpreg = 0x00U; \
959	CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
960	/* Delay after an DSI Host disabling */ \
961	tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
962	UNUSED(tmpreg); \
963	} while(0U)
964
965	/**
966	* @brief Enables the DSI wrapper.
967	* @param __HANDLE__ DSI handle
968	* @retval None.
969	*/
970	#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
971	__IO uint32_t tmpreg = 0x00U; \
972	SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
973	/* Delay after an DSI warpper enabling */ \
974	tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
975	UNUSED(tmpreg); \
976	} while(0U)
977
978	/**
979	* @brief Disable the DSI wrapper.
980	* @param __HANDLE__ DSI handle
981	* @retval None.
982	*/
983	#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
984	__IO uint32_t tmpreg = 0x00U; \
985	CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
986	/* Delay after an DSI warpper disabling*/ \
987	tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
988	UNUSED(tmpreg); \
989	} while(0U)
990
991	/**
992	* @brief Enables the DSI PLL.
993	* @param __HANDLE__ DSI handle
994	* @retval None.
995	*/
996	#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
997	__IO uint32_t tmpreg = 0x00U; \
998	SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
999	/* Delay after an DSI PLL enabling */ \
1000	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1001	UNUSED(tmpreg); \
1002	} while(0U)
1003
1004	/**
1005	* @brief Disables the DSI PLL.
1006	* @param __HANDLE__ DSI handle
1007	* @retval None.
1008	*/
1009	#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
1010	__IO uint32_t tmpreg = 0x00U; \
1011	CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1012	/* Delay after an DSI PLL disabling */ \
1013	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1014	UNUSED(tmpreg); \
1015	} while(0U)
1016
1017	/**
1018	* @brief Enables the DSI regulator.
1019	* @param __HANDLE__ DSI handle
1020	* @retval None.
1021	*/
1022	#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
1023	__IO uint32_t tmpreg = 0x00U; \
1024	SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1025	/* Delay after an DSI regulator enabling */ \
1026	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1027	UNUSED(tmpreg); \
1028	} while(0U)
1029
1030	/**
1031	* @brief Disables the DSI regulator.
1032	* @param __HANDLE__ DSI handle
1033	* @retval None.
1034	*/
1035	#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
1036	__IO uint32_t tmpreg = 0x00U; \
1037	CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1038	/* Delay after an DSI regulator disabling */ \
1039	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1040	UNUSED(tmpreg); \
1041	} while(0U)
1042
1043	/**
1044	* @brief Get the DSI pending flags.
1045	* @param __HANDLE__ DSI handle.
1046	* @param __FLAG__ Get the specified flag.
1047	* This parameter can be any combination of the following values:
1048	* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
1049	* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
1050	* @arg DSI_FLAG_BUSY : Busy Flag
1051	* @arg DSI_FLAG_PLLLS: PLL Lock Status
1052	* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
1053	* @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
1054	* @arg DSI_FLAG_RRS : Regulator Ready Flag
1055	* @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
1056	* @retval The state of FLAG (SET or RESET).
1057	*/
1058	#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
1059
1060	/**
1061	* @brief Clears the DSI pending flags.
1062	* @param __HANDLE__ DSI handle.
1063	* @param __FLAG__ specifies the flag to clear.
1064	* This parameter can be any combination of the following values:
1065	* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
1066	* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
1067	* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
1068	* @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
1069	* @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
1070	* @retval None
1071	*/
1072	#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
1073
1074	/**
1075	* @brief Enables the specified DSI interrupts.
1076	* @param __HANDLE__ DSI handle.
1077	* @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled.
1078	* This parameter can be any combination of the following values:
1079	* @arg DSI_IT_TE : Tearing Effect Interrupt
1080	* @arg DSI_IT_ER : End of Refresh Interrupt
1081	* @arg DSI_IT_PLLL: PLL Lock Interrupt
1082	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
1083	* @arg DSI_IT_RR : Regulator Ready Interrupt
1084	* @retval None
1085	*/
1086	#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER \|= (__INTERRUPT__))
1087
1088	/**
1089	* @brief Disables the specified DSI interrupts.
1090	* @param __HANDLE__ DSI handle
1091	* @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled.
1092	* This parameter can be any combination of the following values:
1093	* @arg DSI_IT_TE : Tearing Effect Interrupt
1094	* @arg DSI_IT_ER : End of Refresh Interrupt
1095	* @arg DSI_IT_PLLL: PLL Lock Interrupt
1096	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
1097	* @arg DSI_IT_RR : Regulator Ready Interrupt
1098	* @retval None
1099	*/
1100	#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
1101
1102	/**
1103	* @brief Checks whether the specified DSI interrupt source is enabled or not.
1104	* @param __HANDLE__ DSI handle
1105	* @param __INTERRUPT__ specifies the DSI interrupt source to check.
1106	* This parameter can be one of the following values:
1107	* @arg DSI_IT_TE : Tearing Effect Interrupt
1108	* @arg DSI_IT_ER : End of Refresh Interrupt
1109	* @arg DSI_IT_PLLL: PLL Lock Interrupt
1110	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
1111	* @arg DSI_IT_RR : Regulator Ready Interrupt
1112	* @retval The state of INTERRUPT (SET or RESET).
1113	*/
1114	#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
1115
1116	/**
1117	* @}
1118	*/
1119
1120	/* Exported functions --------------------------------------------------------*/
1121	/** @defgroup DSI_Exported_Functions DSI Exported Functions
1122	* @{
1123	*/
1124	HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef hdsi, DSI_PLLInitTypeDef PLLInit);
1125	HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
1126	void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
1127	void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
1128
1129	void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
1130	void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
1131	void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
1132	void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
1133
1134	/* Callbacks Register/UnRegister functions ***********************************/
1135	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
1136	HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
1137	pDSI_CallbackTypeDef pCallback);
1138	HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
1139	#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
1140
1141	HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
1142	HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef hdsi, DSI_VidCfgTypeDef VidCfg);
1143	HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef hdsi, DSI_CmdCfgTypeDef CmdCfg);
1144	HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef hdsi, DSI_LPCmdTypeDef LPCmd);
1145	HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
1146	HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef hdsi, DSI_PHY_TimerTypeDef PhyTimers);
1147	HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef hdsi, DSI_HOST_TimeoutTypeDef HostTimeouts);
1148	HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
1149	HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
1150	HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
1151	HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
1152	HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
1153	HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1154	uint32_t ChannelID,
1155	uint32_t Mode,
1156	uint32_t Param1,
1157	uint32_t Param2);
1158	HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1159	uint32_t ChannelID,
1160	uint32_t Mode,
1161	uint32_t NbParams,
1162	uint32_t Param1,
1163	uint8_t *ParametersTable);
1164	HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1165	uint32_t ChannelNbr,
1166	uint8_t *Array,
1167	uint32_t Size,
1168	uint32_t Mode,
1169	uint32_t DCSCmd,
1170	uint8_t *ParametersTable);
1171	HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
1172	HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
1173	HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
1174	HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
1175
1176	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
1177	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
1178
1179	HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
1180	uint32_t Value);
1181	HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
1182	HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
1183	HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
1184	FunctionalState State);
1185	HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,
1186	uint32_t Value);
1187	HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
1188	HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
1189	HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
1190	HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
1191	HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
1192
1193	uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
1194	HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
1195	HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
1196	/**
1197	* @}
1198	*/
1199
1200	/* Private types -------------------------------------------------------------*/
1201	/** @defgroup DSI_Private_Types DSI Private Types
1202	* @{
1203	*/
1204
1205	/**
1206	* @}
1207	*/
1208
1209	/* Private defines -----------------------------------------------------------*/
1210	/** @defgroup DSI_Private_Defines DSI Private Defines
1211	* @{
1212	*/
1213
1214	/**
1215	* @}
1216	*/
1217
1218	/* Private variables ---------------------------------------------------------*/
1219	/** @defgroup DSI_Private_Variables DSI Private Variables
1220	* @{
1221	*/
1222
1223	/**
1224	* @}
1225	*/
1226
1227	/* Private constants ---------------------------------------------------------*/
1228	/** @defgroup DSI_Private_Constants DSI Private Constants
1229	* @{
1230	*/
1231	#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /!< Maximum return packet configuration /
1232	/**
1233	* @}
1234	*/
1235
1236	/* Private macros ------------------------------------------------------------*/
1237	/** @defgroup DSI_Private_Macros DSI Private Macros
1238	* @{
1239	*/
1240	#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
1241	#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) \|\| \
1242	((IDF) == DSI_PLL_IN_DIV2) \|\| \
1243	((IDF) == DSI_PLL_IN_DIV3) \|\| \
1244	((IDF) == DSI_PLL_IN_DIV4) \|\| \
1245	((IDF) == DSI_PLL_IN_DIV5) \|\| \
1246	((IDF) == DSI_PLL_IN_DIV6) \|\| \
1247	((IDF) == DSI_PLL_IN_DIV7))
1248	#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) \|\| \
1249	((ODF) == DSI_PLL_OUT_DIV2) \|\| \
1250	((ODF) == DSI_PLL_OUT_DIV4) \|\| \
1251	((ODF) == DSI_PLL_OUT_DIV8))
1252	#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) \|\| ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
1253	#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) \|\| ((NumberOfLanes) == DSI_TWO_DATA_LANES))
1254	#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) \| DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
1255	#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
1256	#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) \|\| ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
1257	#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) \|\| ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
1258	#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) \|\| ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
1259	#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) \|\| ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
1260	#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) \|\| \
1261	((VideoModeType) == DSI_VID_MODE_NB_EVENTS) \|\| \
1262	((VideoModeType) == DSI_VID_MODE_BURST))
1263	#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) \|\| ((ColorMode) == DSI_COLOR_MODE_EIGHT))
1264	#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) \|\| ((ShutDown) == DSI_DISPLAY_OFF))
1265	#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) \|\| ((LPCommand) == DSI_LP_COMMAND_ENABLE))
1266	#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) \|\| ((LPHFP) == DSI_LP_HFP_ENABLE))
1267	#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) \|\| ((LPHBP) == DSI_LP_HBP_ENABLE))
1268	#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) \|\| ((LPVActive) == DSI_LP_VACT_ENABLE))
1269	#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) \|\| ((LPVFP) == DSI_LP_VFP_ENABLE))
1270	#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) \|\| ((LPVBP) == DSI_LP_VBP_ENABLE))
1271	#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) \|\| ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
1272	#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) \|\| ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
1273	#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) \|\| ((TESource) == DSI_TE_EXTERNAL))
1274	#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) \|\| ((TEPolarity) == DSI_TE_FALLING_EDGE))
1275	#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) \|\| ((AutomaticRefresh) == DSI_AR_ENABLE))
1276	#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) \|\| ((VSPolarity) == DSI_VSYNC_RISING))
1277	#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) \|\| ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
1278	#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) \|\| ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
1279	#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) \|\| ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
1280	#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) \|\| ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
1281	#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) \|\| ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
1282	#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) \|\| ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
1283	#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) \|\| ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
1284	#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) \|\| ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
1285	#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) \|\| ((LP_GLW) == DSI_LP_GLW_ENABLE))
1286	#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) \|\| ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
1287	#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) \|\| ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
1288	#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) \|\| ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
1289	#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) \|\| ((LP_DLW) == DSI_LP_DLW_ENABLE))
1290	#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) \|\| ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
1291	#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) \|\| \
1292	((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) \|\| \
1293	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) \|\| \
1294	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) \|\| \
1295	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
1296	#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) \|\| \
1297	((MODE) == DSI_GEN_LONG_PKT_WRITE))
1298	#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) \|\| \
1299	((MODE) == DSI_GEN_SHORT_PKT_READ_P0) \|\| \
1300	((MODE) == DSI_GEN_SHORT_PKT_READ_P1) \|\| \
1301	((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
1302	#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) \|\| ((CommDelay) == DSI_SLEW_RATE_LPTX) \|\| ((CommDelay) == DSI_HS_DELAY))
1303	#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) \|\| ((Lane) == DSI_DATA_LANES))
1304	#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) \|\| ((CustomLane) == DSI_INVERT_HS_SIGNAL))
1305	#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) \|\| ((Lane) == DSI_DATA_LANE0) \|\| ((Lane) == DSI_DATA_LANE1))
1306	#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) \|\| \
1307	((Timing) == DSI_TLPX_CLK ) \|\| \
1308	((Timing) == DSI_THS_EXIT ) \|\| \
1309	((Timing) == DSI_TLPX_DATA ) \|\| \
1310	((Timing) == DSI_THS_ZERO ) \|\| \
1311	((Timing) == DSI_THS_TRAIL ) \|\| \
1312	((Timing) == DSI_THS_PREPARE ) \|\| \
1313	((Timing) == DSI_TCLK_ZERO ) \|\| \
1314	((Timing) == DSI_TCLK_PREPARE))
1315
1316	/**
1317	* @}
1318	*/
1319
1320	/* Private functions prototypes ----------------------------------------------*/
1321	/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
1322	* @{
1323	*/
1324
1325	/**
1326	* @}
1327	*/
1328
1329	/* Private functions ---------------------------------------------------------*/
1330	/** @defgroup DSI_Private_Functions DSI Private Functions
1331	* @{
1332	*/
1333
1334	/**
1335	* @}
1336	*/
1337
1338	/**
1339	* @}
1340	*/
1341
1342	/**
1343	* @}
1344	*/
1345	#endif /* DSI */
1346
1347	#ifdef __cplusplus
1348	}
1349	#endif
1350
1351	#endif /* STM32F4xx_HAL_DSI_H */
1352
1353	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h

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