source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h

Last change on this file was 1, checked in by AlexLir, 4 years ago
File size: 109.1 KB
Line 
1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_eth.h
4 * @author MCD Application Team
5 * @brief Header file of ETH HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef __STM32F4xx_HAL_ETH_H
22#define __STM32F4xx_HAL_ETH_H
23
24#ifdef __cplusplus
25 extern "C" {
26#endif
27
28#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
29 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
30/* Includes ------------------------------------------------------------------*/
31#include "stm32f4xx_hal_def.h"
32
33/** @addtogroup STM32F4xx_HAL_Driver
34 * @{
35 */
36
37/** @addtogroup ETH
38 * @{
39 */
40
41/** @addtogroup ETH_Private_Macros
42 * @{
43 */
44#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
45#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
46 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
47#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
48 ((SPEED) == ETH_SPEED_100M))
49#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
50 ((MODE) == ETH_MODE_HALFDUPLEX))
51#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
52 ((MODE) == ETH_RXINTERRUPT_MODE))
53#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
54 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
55#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
56 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
57#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
58 ((CMD) == ETH_WATCHDOG_DISABLE))
59#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
60 ((CMD) == ETH_JABBER_DISABLE))
61#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
62 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
63 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
64 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
65 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
66 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
67 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
68 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
69#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
70 ((CMD) == ETH_CARRIERSENCE_DISABLE))
71#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
72 ((CMD) == ETH_RECEIVEOWN_DISABLE))
73#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
74 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
75#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
76 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
77#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
78 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
79#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
80 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
81#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
82 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
83 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
84 ((LIMIT) == ETH_BACKOFFLIMIT_1))
85#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
86 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
87#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
88 ((CMD) == ETH_RECEIVEAll_DISABLE))
89#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
90 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
91 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
92#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
93 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
94 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
95#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
96 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
97#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
98 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
99#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
100 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
101#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
102 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
103 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
104 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
105#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
106 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
107 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
108#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
109#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
110 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
111#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
112 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
113 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
114 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
115#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
116 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
117#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
118 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
119#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
120 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
121#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
122 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
123#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
124#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
125 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
126 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
127 ((ADDRESS) == ETH_MAC_ADDRESS3))
128#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
129 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
130 ((ADDRESS) == ETH_MAC_ADDRESS3))
131#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
132 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
133#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
134 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
135 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
136 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
137 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
138 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
139#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
140 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
141#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
142 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
143#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
144 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
145#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
146 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
147#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
148 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
149 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
150 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
151 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
152 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
153 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
154 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
155#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
156 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
157#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
158 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
159#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
160 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
161 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
162 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
163#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
164 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
165#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
166 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
167#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
168 ((CMD) == ETH_FIXEDBURST_DISABLE))
169#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
170 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
171 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
172 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
173 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
174 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
175 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
176 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
177 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
178 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
179 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
180 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
181#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
182 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
183 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
184 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
185 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
186 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
187 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
188 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
189 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
190 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
191 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
192 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
193#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
194#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
195 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
196 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
197 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
198 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
199#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
200 ((FLAG) == ETH_DMATXDESC_IC) || \
201 ((FLAG) == ETH_DMATXDESC_LS) || \
202 ((FLAG) == ETH_DMATXDESC_FS) || \
203 ((FLAG) == ETH_DMATXDESC_DC) || \
204 ((FLAG) == ETH_DMATXDESC_DP) || \
205 ((FLAG) == ETH_DMATXDESC_TTSE) || \
206 ((FLAG) == ETH_DMATXDESC_TER) || \
207 ((FLAG) == ETH_DMATXDESC_TCH) || \
208 ((FLAG) == ETH_DMATXDESC_TTSS) || \
209 ((FLAG) == ETH_DMATXDESC_IHE) || \
210 ((FLAG) == ETH_DMATXDESC_ES) || \
211 ((FLAG) == ETH_DMATXDESC_JT) || \
212 ((FLAG) == ETH_DMATXDESC_FF) || \
213 ((FLAG) == ETH_DMATXDESC_PCE) || \
214 ((FLAG) == ETH_DMATXDESC_LCA) || \
215 ((FLAG) == ETH_DMATXDESC_NC) || \
216 ((FLAG) == ETH_DMATXDESC_LCO) || \
217 ((FLAG) == ETH_DMATXDESC_EC) || \
218 ((FLAG) == ETH_DMATXDESC_VF) || \
219 ((FLAG) == ETH_DMATXDESC_CC) || \
220 ((FLAG) == ETH_DMATXDESC_ED) || \
221 ((FLAG) == ETH_DMATXDESC_UF) || \
222 ((FLAG) == ETH_DMATXDESC_DB))
223#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
224 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
225#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
226 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
227 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
228 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
229#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
230#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
231 ((FLAG) == ETH_DMARXDESC_AFM) || \
232 ((FLAG) == ETH_DMARXDESC_ES) || \
233 ((FLAG) == ETH_DMARXDESC_DE) || \
234 ((FLAG) == ETH_DMARXDESC_SAF) || \
235 ((FLAG) == ETH_DMARXDESC_LE) || \
236 ((FLAG) == ETH_DMARXDESC_OE) || \
237 ((FLAG) == ETH_DMARXDESC_VLAN) || \
238 ((FLAG) == ETH_DMARXDESC_FS) || \
239 ((FLAG) == ETH_DMARXDESC_LS) || \
240 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
241 ((FLAG) == ETH_DMARXDESC_LC) || \
242 ((FLAG) == ETH_DMARXDESC_FT) || \
243 ((FLAG) == ETH_DMARXDESC_RWT) || \
244 ((FLAG) == ETH_DMARXDESC_RE) || \
245 ((FLAG) == ETH_DMARXDESC_DBE) || \
246 ((FLAG) == ETH_DMARXDESC_CE) || \
247 ((FLAG) == ETH_DMARXDESC_MAMPCE))
248#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
249 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
250#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
251 ((FLAG) == ETH_PMT_FLAG_MPR))
252#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
253#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
254 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
255 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
256 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
257 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
258 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
259 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
260 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
261 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
262 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
263 ((FLAG) == ETH_DMA_FLAG_T))
264#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
265#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
266 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
267 ((IT) == ETH_MAC_IT_PMT))
268#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
269 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
270 ((FLAG) == ETH_MAC_FLAG_PMT))
271#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
272#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
273 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
274 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
275 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
276 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
277 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
278 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
279 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
280 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
281#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
282 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
283#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
284 ((IT) != 0x00U))
285#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
286 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
287 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
288#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
289 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
290
291/**
292 * @}
293 */
294
295/** @addtogroup ETH_Private_Defines
296 * @{
297 */
298/* Delay to wait when writing to some Ethernet registers */
299#define ETH_REG_WRITE_DELAY 0x00000001U
300
301/* ETHERNET Errors */
302#define ETH_SUCCESS 0U
303#define ETH_ERROR 1U
304
305/* ETHERNET DMA Tx descriptors Collision Count Shift */
306#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
307
308/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
309#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
310
311/* ETHERNET DMA Rx descriptors Frame Length Shift */
312#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
313
314/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
315#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
316
317/* ETHERNET DMA Rx descriptors Frame length Shift */
318#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
319
320/* ETHERNET MAC address offsets */
321#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
322#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
323
324/* ETHERNET MACMIIAR register Mask */
325#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
326
327/* ETHERNET MACCR register Mask */
328#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
329
330/* ETHERNET MACFCR register Mask */
331#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
332
333/* ETHERNET DMAOMR register Mask */
334#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
335
336/* ETHERNET Remote Wake-up frame register length */
337#define ETH_WAKEUP_REGISTER_LENGTH 8U
338
339/* ETHERNET Missed frames counter Shift */
340#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
341 /**
342 * @}
343 */
344
345/* Exported types ------------------------------------------------------------*/
346/** @defgroup ETH_Exported_Types ETH Exported Types
347 * @{
348 */
349
350/**
351 * @brief HAL State structures definition
352 */
353typedef enum
354{
355 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
356 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
357 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
358 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
359 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
360 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
361 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
362 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
363 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
364 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
365}HAL_ETH_StateTypeDef;
366
367/**
368 * @brief ETH Init Structure definition
369 */
370
371typedef struct
372{
373 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
374 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
375 and the mode (half/full-duplex).
376 This parameter can be a value of @ref ETH_AutoNegotiation */
377
378 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
379 This parameter can be a value of @ref ETH_Speed */
380
381 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
382 This parameter can be a value of @ref ETH_Duplex_Mode */
383
384 uint16_t PhyAddress; /*!< Ethernet PHY address.
385 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
386
387 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
388
389 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
390 This parameter can be a value of @ref ETH_Rx_Mode */
391
392 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
393 This parameter can be a value of @ref ETH_Checksum_Mode */
394
395 uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
396 This parameter can be a value of @ref ETH_Media_Interface */
397
398} ETH_InitTypeDef;
399
400
401 /**
402 * @brief ETH MAC Configuration Structure definition
403 */
404
405typedef struct
406{
407 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
408 When enabled, the MAC allows no more then 2048 bytes to be received.
409 When disabled, the MAC can receive up to 16384 bytes.
410 This parameter can be a value of @ref ETH_Watchdog */
411
412 uint32_t Jabber; /*!< Selects or not Jabber timer
413 When enabled, the MAC allows no more then 2048 bytes to be sent.
414 When disabled, the MAC can send up to 16384 bytes.
415 This parameter can be a value of @ref ETH_Jabber */
416
417 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
418 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
419
420 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
421 This parameter can be a value of @ref ETH_Carrier_Sense */
422
423 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
424 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
425 in Half-Duplex mode.
426 This parameter can be a value of @ref ETH_Receive_Own */
427
428 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
429 This parameter can be a value of @ref ETH_Loop_Back_Mode */
430
431 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
432 This parameter can be a value of @ref ETH_Checksum_Offload */
433
434 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
435 when a collision occurs (Half-Duplex mode).
436 This parameter can be a value of @ref ETH_Retry_Transmission */
437
438 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
439 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
440
441 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
442 This parameter can be a value of @ref ETH_Back_Off_Limit */
443
444 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
445 This parameter can be a value of @ref ETH_Deferral_Check */
446
447 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
448 This parameter can be a value of @ref ETH_Receive_All */
449
450 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
451 This parameter can be a value of @ref ETH_Source_Addr_Filter */
452
453 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
454 This parameter can be a value of @ref ETH_Pass_Control_Frames */
455
456 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
457 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
458
459 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
460 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
461
462 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
463 This parameter can be a value of @ref ETH_Promiscuous_Mode */
464
465 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
466 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
467
468 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
469 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
470
471 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
472 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
473
474 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
475 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
476
477 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
478 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
479
480 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
481 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
482
483 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
484 automatic retransmission of PAUSE Frame.
485 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
486
487 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
488 unicast address and unique multicast address).
489 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
490
491 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
492 disable its transmitter for a specified time (Pause Time)
493 This parameter can be a value of @ref ETH_Receive_Flow_Control */
494
495 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
496 or the MAC back-pressure operation (Half-Duplex mode)
497 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
498
499 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
500 comparison and filtering.
501 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
502
503 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
504
505} ETH_MACInitTypeDef;
506
507/**
508 * @brief ETH DMA Configuration Structure definition
509 */
510
511typedef struct
512{
513 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
514 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
515
516 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
517 This parameter can be a value of @ref ETH_Receive_Store_Forward */
518
519 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
520 This parameter can be a value of @ref ETH_Flush_Received_Frame */
521
522 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
523 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
524
525 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
526 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
527
528 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
529 This parameter can be a value of @ref ETH_Forward_Error_Frames */
530
531 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
532 and length less than 64 bytes) including pad-bytes and CRC)
533 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
534
535 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
536 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
537
538 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
539 frame of Transmit data even before obtaining the status for the first frame.
540 This parameter can be a value of @ref ETH_Second_Frame_Operate */
541
542 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
543 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
544
545 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
546 This parameter can be a value of @ref ETH_Fixed_Burst */
547
548 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
549 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
550
551 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
552 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
553
554 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
555 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
556
557 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
558 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
559
560 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
561 This parameter can be a value of @ref ETH_DMA_Arbitration */
562} ETH_DMAInitTypeDef;
563
564
565/**
566 * @brief ETH DMA Descriptors data structure definition
567 */
568
569typedef struct
570{
571 __IO uint32_t Status; /*!< Status */
572
573 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
574
575 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
576
577 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
578
579 /*!< Enhanced ETHERNET DMA PTP Descriptors */
580 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
581
582 uint32_t Reserved1; /*!< Reserved */
583
584 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
585
586 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
587
588} ETH_DMADescTypeDef;
589
590/**
591 * @brief Received Frame Informations structure definition
592 */
593typedef struct
594{
595 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
596
597 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
598
599 uint32_t SegCount; /*!< Segment count */
600
601 uint32_t length; /*!< Frame length */
602
603 uint32_t buffer; /*!< Frame buffer */
604
605} ETH_DMARxFrameInfos;
606
607/**
608 * @brief ETH Handle Structure definition
609 */
610
611#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
612typedef struct __ETH_HandleTypeDef
613#else
614typedef struct
615#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
616{
617 ETH_TypeDef *Instance; /*!< Register base address */
618
619 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
620
621 uint32_t LinkStatus; /*!< Ethernet link status */
622
623 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
624
625 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
626
627 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
628
629 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
630
631 HAL_LockTypeDef Lock; /*!< ETH Lock */
632
633#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
634
635 void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */
636 void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */
637 void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */
638 void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */
639 void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */
640
641#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
642
643} ETH_HandleTypeDef;
644
645#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
646/**
647 * @brief HAL ETH Callback ID enumeration definition
648 */
649typedef enum
650{
651 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
652 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
653 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
654 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
655 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */
656
657}HAL_ETH_CallbackIDTypeDef;
658
659/**
660 * @brief HAL ETH Callback pointer definition
661 */
662typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
663
664#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
665
666 /**
667 * @}
668 */
669
670/* Exported constants --------------------------------------------------------*/
671/** @defgroup ETH_Exported_Constants ETH Exported Constants
672 * @{
673 */
674
675/** @defgroup ETH_Buffers_setting ETH Buffers setting
676 * @{
677 */
678#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
679#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
680#define ETH_CRC 4U /*!< Ethernet CRC */
681#define ETH_EXTRA 2U /*!< Extra bytes in some cases */
682#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
683#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
684#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
685#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
686
687 /* Ethernet driver receive buffers are organized in a chained linked-list, when
688 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
689 to the driver receive buffers memory.
690
691 Depending on the size of the received ethernet packet and the size of
692 each ethernet driver receive buffer, the received packet can take one or more
693 ethernet driver receive buffer.
694
695 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
696 and the total count of the driver receive buffers ETH_RXBUFNB.
697
698 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
699 example, they can be reconfigured in the application layer to fit the application
700 needs */
701
702/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
703 packet */
704#ifndef ETH_RX_BUF_SIZE
705 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
706#endif
707
708/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
709#ifndef ETH_RXBUFNB
710 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
711#endif
712
713
714 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
715 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
716 driver transmit buffers memory to the TxFIFO.
717
718 Depending on the size of the Ethernet packet to be transmitted and the size of
719 each ethernet driver transmit buffer, the packet to be transmitted can take
720 one or more ethernet driver transmit buffer.
721
722 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
723 and the total count of the driver transmit buffers ETH_TXBUFNB.
724
725 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
726 example, they can be reconfigured in the application layer to fit the application
727 needs */
728
729/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
730 packet */
731#ifndef ETH_TX_BUF_SIZE
732 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
733#endif
734
735/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
736#ifndef ETH_TXBUFNB
737 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
738#endif
739
740 /**
741 * @}
742 */
743
744/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
745 * @{
746 */
747
748/*
749 DMA Tx Descriptor
750 -----------------------------------------------------------------------------------------------
751 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
752 -----------------------------------------------------------------------------------------------
753 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
754 -----------------------------------------------------------------------------------------------
755 TDES2 | Buffer1 Address [31:0] |
756 -----------------------------------------------------------------------------------------------
757 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
758 -----------------------------------------------------------------------------------------------
759*/
760
761/**
762 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
763 */
764#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
765#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
766#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
767#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
768#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
769#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
770#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
771#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
772#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
773#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
774#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
775#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
776#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
777#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
778#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
779#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
780#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
781#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
782#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
783#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
784#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
785#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
786#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
787#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
788#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
789#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
790#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
791#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
792#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
793
794/**
795 * @brief Bit definition of TDES1 register
796 */
797#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
798#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
799
800/**
801 * @brief Bit definition of TDES2 register
802 */
803#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
804
805/**
806 * @brief Bit definition of TDES3 register
807 */
808#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
809
810 /*---------------------------------------------------------------------------------------------
811 TDES6 | Transmit Time Stamp Low [31:0] |
812 -----------------------------------------------------------------------------------------------
813 TDES7 | Transmit Time Stamp High [31:0] |
814 ----------------------------------------------------------------------------------------------*/
815
816/* Bit definition of TDES6 register */
817 #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
818
819/* Bit definition of TDES7 register */
820 #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
821
822/**
823 * @}
824 */
825/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
826 * @{
827 */
828
829/*
830 DMA Rx Descriptor
831 --------------------------------------------------------------------------------------------------------------------
832 RDES0 | OWN(31) | Status [30:0] |
833 ---------------------------------------------------------------------------------------------------------------------
834 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
835 ---------------------------------------------------------------------------------------------------------------------
836 RDES2 | Buffer1 Address [31:0] |
837 ---------------------------------------------------------------------------------------------------------------------
838 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
839 ---------------------------------------------------------------------------------------------------------------------
840*/
841
842/**
843 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
844 */
845#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
846#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
847#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
848#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
849#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
850#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
851#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
852#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
853#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
854#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
855#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
856#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
857#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
858#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
859#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
860#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
861#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
862#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
863#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
864
865/**
866 * @brief Bit definition of RDES1 register
867 */
868#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
869#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
870#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
871#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
872#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
873
874/**
875 * @brief Bit definition of RDES2 register
876 */
877#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
878
879/**
880 * @brief Bit definition of RDES3 register
881 */
882#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
883
884/*---------------------------------------------------------------------------------------------------------------------
885 RDES4 | Reserved[31:15] | Extended Status [14:0] |
886 ---------------------------------------------------------------------------------------------------------------------
887 RDES5 | Reserved[31:0] |
888 ---------------------------------------------------------------------------------------------------------------------
889 RDES6 | Receive Time Stamp Low [31:0] |
890 ---------------------------------------------------------------------------------------------------------------------
891 RDES7 | Receive Time Stamp High [31:0] |
892 --------------------------------------------------------------------------------------------------------------------*/
893
894/* Bit definition of RDES4 register */
895#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
896#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
897#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
898 #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
899 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
900 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
901 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
902 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
903 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
904 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
905#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
906#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
907#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
908#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
909#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
910#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
911 #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
912 #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
913 #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
914
915/* Bit definition of RDES6 register */
916#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
917
918/* Bit definition of RDES7 register */
919#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
920/**
921 * @}
922 */
923 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
924 * @{
925 */
926#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
927#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
928
929/**
930 * @}
931 */
932/** @defgroup ETH_Speed ETH Speed
933 * @{
934 */
935#define ETH_SPEED_10M 0x00000000U
936#define ETH_SPEED_100M 0x00004000U
937
938/**
939 * @}
940 */
941/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
942 * @{
943 */
944#define ETH_MODE_FULLDUPLEX 0x00000800U
945#define ETH_MODE_HALFDUPLEX 0x00000000U
946/**
947 * @}
948 */
949/** @defgroup ETH_Rx_Mode ETH Rx Mode
950 * @{
951 */
952#define ETH_RXPOLLING_MODE 0x00000000U
953#define ETH_RXINTERRUPT_MODE 0x00000001U
954/**
955 * @}
956 */
957
958/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
959 * @{
960 */
961#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
962#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
963/**
964 * @}
965 */
966
967/** @defgroup ETH_Media_Interface ETH Media Interface
968 * @{
969 */
970#define ETH_MEDIA_INTERFACE_MII 0x00000000U
971#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
972/**
973 * @}
974 */
975
976/** @defgroup ETH_Watchdog ETH Watchdog
977 * @{
978 */
979#define ETH_WATCHDOG_ENABLE 0x00000000U
980#define ETH_WATCHDOG_DISABLE 0x00800000U
981/**
982 * @}
983 */
984
985/** @defgroup ETH_Jabber ETH Jabber
986 * @{
987 */
988#define ETH_JABBER_ENABLE 0x00000000U
989#define ETH_JABBER_DISABLE 0x00400000U
990/**
991 * @}
992 */
993
994/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
995 * @{
996 */
997#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
998#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
999#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
1000#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
1001#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
1002#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
1003#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
1004#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
1005/**
1006 * @}
1007 */
1008
1009/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
1010 * @{
1011 */
1012#define ETH_CARRIERSENCE_ENABLE 0x00000000U
1013#define ETH_CARRIERSENCE_DISABLE 0x00010000U
1014/**
1015 * @}
1016 */
1017
1018/** @defgroup ETH_Receive_Own ETH Receive Own
1019 * @{
1020 */
1021#define ETH_RECEIVEOWN_ENABLE 0x00000000U
1022#define ETH_RECEIVEOWN_DISABLE 0x00002000U
1023/**
1024 * @}
1025 */
1026
1027/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
1028 * @{
1029 */
1030#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
1031#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
1032/**
1033 * @}
1034 */
1035
1036/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
1037 * @{
1038 */
1039#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
1040#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
1041/**
1042 * @}
1043 */
1044
1045/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
1046 * @{
1047 */
1048#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
1049#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
1050/**
1051 * @}
1052 */
1053
1054/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
1055 * @{
1056 */
1057#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
1058#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
1059/**
1060 * @}
1061 */
1062
1063/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
1064 * @{
1065 */
1066#define ETH_BACKOFFLIMIT_10 0x00000000U
1067#define ETH_BACKOFFLIMIT_8 0x00000020U
1068#define ETH_BACKOFFLIMIT_4 0x00000040U
1069#define ETH_BACKOFFLIMIT_1 0x00000060U
1070/**
1071 * @}
1072 */
1073
1074/** @defgroup ETH_Deferral_Check ETH Deferral Check
1075 * @{
1076 */
1077#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
1078#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
1079/**
1080 * @}
1081 */
1082
1083/** @defgroup ETH_Receive_All ETH Receive All
1084 * @{
1085 */
1086#define ETH_RECEIVEALL_ENABLE 0x80000000U
1087#define ETH_RECEIVEAll_DISABLE 0x00000000U
1088/**
1089 * @}
1090 */
1091
1092/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
1093 * @{
1094 */
1095#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
1096#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
1097#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
1098/**
1099 * @}
1100 */
1101
1102/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
1103 * @{
1104 */
1105#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
1106#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
1107#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
1108/**
1109 * @}
1110 */
1111
1112/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
1113 * @{
1114 */
1115#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
1116#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
1117/**
1118 * @}
1119 */
1120
1121/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
1122 * @{
1123 */
1124#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
1125#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
1126/**
1127 * @}
1128 */
1129
1130/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
1131 * @{
1132 */
1133#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
1134#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
1135/**
1136 * @}
1137 */
1138
1139/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
1140 * @{
1141 */
1142#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
1143#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
1144#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
1145#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
1146/**
1147 * @}
1148 */
1149
1150/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
1151 * @{
1152 */
1153#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
1154#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
1155#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
1156/**
1157 * @}
1158 */
1159
1160/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
1161 * @{
1162 */
1163#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
1164#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
1165/**
1166 * @}
1167 */
1168
1169/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
1170 * @{
1171 */
1172#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
1173#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
1174#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
1175#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
1176/**
1177 * @}
1178 */
1179
1180/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
1181 * @{
1182 */
1183#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
1184#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
1185/**
1186 * @}
1187 */
1188
1189/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
1190 * @{
1191 */
1192#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
1193#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
1194/**
1195 * @}
1196 */
1197
1198/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
1199 * @{
1200 */
1201#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
1202#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
1203/**
1204 * @}
1205 */
1206
1207/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1208 * @{
1209 */
1210#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
1211#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
1212/**
1213 * @}
1214 */
1215
1216/** @defgroup ETH_MAC_addresses ETH MAC addresses
1217 * @{
1218 */
1219#define ETH_MAC_ADDRESS0 0x00000000U
1220#define ETH_MAC_ADDRESS1 0x00000008U
1221#define ETH_MAC_ADDRESS2 0x00000010U
1222#define ETH_MAC_ADDRESS3 0x00000018U
1223/**
1224 * @}
1225 */
1226
1227/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
1228 * @{
1229 */
1230#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
1231#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
1232/**
1233 * @}
1234 */
1235
1236/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
1237 * @{
1238 */
1239#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
1240#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
1241#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
1242#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
1243#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
1244#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
1245/**
1246 * @}
1247 */
1248
1249/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
1250 * @{
1251 */
1252#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
1253#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
1254/**
1255 * @}
1256 */
1257
1258/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
1259 * @{
1260 */
1261#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
1262#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
1263/**
1264 * @}
1265 */
1266
1267/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
1268 * @{
1269 */
1270#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
1271#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
1272/**
1273 * @}
1274 */
1275
1276/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
1277 * @{
1278 */
1279#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
1280#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
1281/**
1282 * @}
1283 */
1284
1285/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
1286 * @{
1287 */
1288#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
1289#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
1290#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
1291#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
1292#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
1293#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
1294#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
1295#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
1296/**
1297 * @}
1298 */
1299
1300/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
1301 * @{
1302 */
1303#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
1304#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
1305/**
1306 * @}
1307 */
1308
1309/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
1310 * @{
1311 */
1312#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
1313#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
1314/**
1315 * @}
1316 */
1317
1318/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
1319 * @{
1320 */
1321#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
1322#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
1323#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
1324#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
1325/**
1326 * @}
1327 */
1328
1329/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
1330 * @{
1331 */
1332#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
1333#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
1334/**
1335 * @}
1336 */
1337
1338/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
1339 * @{
1340 */
1341#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
1342#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
1343/**
1344 * @}
1345 */
1346
1347/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
1348 * @{
1349 */
1350#define ETH_FIXEDBURST_ENABLE 0x00010000U
1351#define ETH_FIXEDBURST_DISABLE 0x00000000U
1352/**
1353 * @}
1354 */
1355
1356/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
1357 * @{
1358 */
1359#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
1360#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
1361#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1362#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1363#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1364#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1365#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1366#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1367#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1368#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1369#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
1370#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
1371/**
1372 * @}
1373 */
1374
1375/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1376 * @{
1377 */
1378#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
1379#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
1380#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1381#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1382#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1383#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1384#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1385#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1386#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1387#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1388#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
1389#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
1390/**
1391 * @}
1392 */
1393
1394/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
1395 * @{
1396 */
1397#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
1398#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
1399/**
1400 * @}
1401 */
1402
1403/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1404 * @{
1405 */
1406#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
1407#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
1408#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
1409#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
1410#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
1411/**
1412 * @}
1413 */
1414
1415/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
1416 * @{
1417 */
1418#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
1419#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
1420/**
1421 * @}
1422 */
1423
1424/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
1425 * @{
1426 */
1427#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
1428#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
1429#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
1430#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
1431/**
1432 * @}
1433 */
1434
1435/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
1436 * @{
1437 */
1438#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
1439#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
1440/**
1441 * @}
1442 */
1443
1444/** @defgroup ETH_PMT_Flags ETH PMT Flags
1445 * @{
1446 */
1447#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
1448#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
1449#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
1450/**
1451 * @}
1452 */
1453
1454/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
1455 * @{
1456 */
1457#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
1458#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
1459#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
1460/**
1461 * @}
1462 */
1463
1464/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
1465 * @{
1466 */
1467#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */
1468#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */
1469#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */
1470/**
1471 * @}
1472 */
1473
1474/** @defgroup ETH_MAC_Flags ETH MAC Flags
1475 * @{
1476 */
1477#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
1478#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
1479#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
1480#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */
1481#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */
1482/**
1483 * @}
1484 */
1485
1486/** @defgroup ETH_DMA_Flags ETH DMA Flags
1487 * @{
1488 */
1489#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
1490#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
1491#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
1492#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */
1493#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */
1494#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */
1495#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */
1496#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */
1497#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */
1498#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */
1499#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */
1500#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */
1501#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */
1502#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */
1503#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */
1504#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */
1505#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */
1506#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */
1507#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */
1508#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */
1509#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */
1510/**
1511 * @}
1512 */
1513
1514/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1515 * @{
1516 */
1517#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
1518#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
1519#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
1520#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */
1521#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */
1522/**
1523 * @}
1524 */
1525
1526/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1527 * @{
1528 */
1529#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
1530#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
1531#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
1532#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */
1533#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */
1534#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */
1535#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */
1536#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */
1537#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */
1538#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */
1539#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */
1540#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */
1541#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */
1542#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */
1543#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */
1544#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */
1545#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */
1546#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */
1547/**
1548 * @}
1549 */
1550
1551/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
1552 * @{
1553 */
1554#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
1555#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
1556#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
1557#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */
1558#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */
1559#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */
1560
1561/**
1562 * @}
1563 */
1564
1565
1566/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
1567 * @{
1568 */
1569#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
1570#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
1571#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
1572#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */
1573#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */
1574#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */
1575
1576/**
1577 * @}
1578 */
1579
1580/** @defgroup ETH_DMA_overflow ETH DMA overflow
1581 * @{
1582 */
1583#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
1584#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
1585/**
1586 * @}
1587 */
1588
1589/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
1590 * @{
1591 */
1592#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
1593
1594/**
1595 * @}
1596 */
1597
1598/**
1599 * @}
1600 */
1601
1602/* Exported macro ------------------------------------------------------------*/
1603/** @defgroup ETH_Exported_Macros ETH Exported Macros
1604 * @brief macros to handle interrupts and specific clock configurations
1605 * @{
1606 */
1607
1608/** @brief Reset ETH handle state
1609 * @param __HANDLE__ specifies the ETH handle.
1610 * @retval None
1611 */
1612#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1613#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
1614 (__HANDLE__)->State = HAL_ETH_STATE_RESET; \
1615 (__HANDLE__)->MspInitCallback = NULL; \
1616 (__HANDLE__)->MspDeInitCallback = NULL; \
1617 } while(0)
1618#else
1619#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
1620#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
1621
1622/**
1623 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
1624 * @param __HANDLE__ ETH Handle
1625 * @param __FLAG__ specifies the flag of TDES0 to check.
1626 * @retval the ETH_DMATxDescFlag (SET or RESET).
1627 */
1628#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
1629
1630/**
1631 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
1632 * @param __HANDLE__ ETH Handle
1633 * @param __FLAG__ specifies the flag of RDES0 to check.
1634 * @retval the ETH_DMATxDescFlag (SET or RESET).
1635 */
1636#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
1637
1638/**
1639 * @brief Enables the specified DMA Rx Desc receive interrupt.
1640 * @param __HANDLE__ ETH Handle
1641 * @retval None
1642 */
1643#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
1644
1645/**
1646 * @brief Disables the specified DMA Rx Desc receive interrupt.
1647 * @param __HANDLE__ ETH Handle
1648 * @retval None
1649 */
1650#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
1651
1652/**
1653 * @brief Set the specified DMA Rx Desc Own bit.
1654 * @param __HANDLE__ ETH Handle
1655 * @retval None
1656 */
1657#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
1658
1659/**
1660 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
1661 * @param __HANDLE__ ETH Handle
1662 * @retval The Transmit descriptor collision counter value.
1663 */
1664#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
1665
1666/**
1667 * @brief Set the specified DMA Tx Desc Own bit.
1668 * @param __HANDLE__ ETH Handle
1669 * @retval None
1670 */
1671#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
1672
1673/**
1674 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
1675 * @param __HANDLE__ ETH Handle
1676 * @retval None
1677 */
1678#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
1679
1680/**
1681 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
1682 * @param __HANDLE__ ETH Handle
1683 * @retval None
1684 */
1685#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
1686
1687/**
1688 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
1689 * @param __HANDLE__ ETH Handle
1690 * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion.
1691 * This parameter can be one of the following values:
1692 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
1693 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
1694 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
1695 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
1696 * @retval None
1697 */
1698#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
1699
1700/**
1701 * @brief Enables the DMA Tx Desc CRC.
1702 * @param __HANDLE__ ETH Handle
1703 * @retval None
1704 */
1705#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
1706
1707/**
1708 * @brief Disables the DMA Tx Desc CRC.
1709 * @param __HANDLE__ ETH Handle
1710 * @retval None
1711 */
1712#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
1713
1714/**
1715 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
1716 * @param __HANDLE__ ETH Handle
1717 * @retval None
1718 */
1719#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
1720
1721/**
1722 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
1723 * @param __HANDLE__ ETH Handle
1724 * @retval None
1725 */
1726#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
1727
1728/**
1729 * @brief Enables the specified ETHERNET MAC interrupts.
1730 * @param __HANDLE__ ETH Handle
1731 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
1732 * enabled or disabled.
1733 * This parameter can be any combination of the following values:
1734 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1735 * @arg ETH_MAC_IT_PMT : PMT interrupt
1736 * @retval None
1737 */
1738#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
1739
1740/**
1741 * @brief Disables the specified ETHERNET MAC interrupts.
1742 * @param __HANDLE__ ETH Handle
1743 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
1744 * enabled or disabled.
1745 * This parameter can be any combination of the following values:
1746 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1747 * @arg ETH_MAC_IT_PMT : PMT interrupt
1748 * @retval None
1749 */
1750#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
1751
1752/**
1753 * @brief Initiate a Pause Control Frame (Full-duplex only).
1754 * @param __HANDLE__ ETH Handle
1755 * @retval None
1756 */
1757#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1758
1759/**
1760 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
1761 * @param __HANDLE__ ETH Handle
1762 * @retval The new state of flow control busy status bit (SET or RESET).
1763 */
1764#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
1765
1766/**
1767 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
1768 * @param __HANDLE__ ETH Handle
1769 * @retval None
1770 */
1771#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1772
1773/**
1774 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
1775 * @param __HANDLE__ ETH Handle
1776 * @retval None
1777 */
1778#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
1779
1780/**
1781 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
1782 * @param __HANDLE__ ETH Handle
1783 * @param __FLAG__ specifies the flag to check.
1784 * This parameter can be one of the following values:
1785 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
1786 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
1787 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
1788 * @arg ETH_MAC_FLAG_MMC : MMC flag
1789 * @arg ETH_MAC_FLAG_PMT : PMT flag
1790 * @retval The state of ETHERNET MAC flag.
1791 */
1792#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
1793
1794/**
1795 * @brief Enables the specified ETHERNET DMA interrupts.
1796 * @param __HANDLE__ ETH Handle
1797 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
1798 * enabled @ref ETH_DMA_Interrupts
1799 * @retval None
1800 */
1801#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
1802
1803/**
1804 * @brief Disables the specified ETHERNET DMA interrupts.
1805 * @param __HANDLE__ ETH Handle
1806 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
1807 * disabled. @ref ETH_DMA_Interrupts
1808 * @retval None
1809 */
1810#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
1811
1812/**
1813 * @brief Clears the ETHERNET DMA IT pending bit.
1814 * @param __HANDLE__ ETH Handle
1815 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
1816 * @retval None
1817 */
1818#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
1819
1820/**
1821 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1822* @param __HANDLE__ ETH Handle
1823 * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags
1824 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1825 */
1826#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
1827
1828/**
1829 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1830 * @param __HANDLE__ ETH Handle
1831 * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags
1832 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1833 */
1834#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
1835
1836/**
1837 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
1838 * @param __HANDLE__ ETH Handle
1839 * @param __OVERFLOW__ specifies the DMA overflow flag to check.
1840 * This parameter can be one of the following values:
1841 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
1842 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
1843 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
1844 */
1845#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
1846
1847/**
1848 * @brief Set the DMA Receive status watchdog timer register value
1849 * @param __HANDLE__ ETH Handle
1850 * @param __VALUE__ DMA Receive status watchdog timer register value
1851 * @retval None
1852 */
1853#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
1854
1855/**
1856 * @brief Enables any unicast packet filtered by the MAC address
1857 * recognition to be a wake-up frame.
1858 * @param __HANDLE__ ETH Handle.
1859 * @retval None
1860 */
1861#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
1862
1863/**
1864 * @brief Disables any unicast packet filtered by the MAC address
1865 * recognition to be a wake-up frame.
1866 * @param __HANDLE__ ETH Handle.
1867 * @retval None
1868 */
1869#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
1870
1871/**
1872 * @brief Enables the MAC Wake-Up Frame Detection.
1873 * @param __HANDLE__ ETH Handle.
1874 * @retval None
1875 */
1876#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
1877
1878/**
1879 * @brief Disables the MAC Wake-Up Frame Detection.
1880 * @param __HANDLE__ ETH Handle.
1881 * @retval None
1882 */
1883#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1884
1885/**
1886 * @brief Enables the MAC Magic Packet Detection.
1887 * @param __HANDLE__ ETH Handle.
1888 * @retval None
1889 */
1890#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
1891
1892/**
1893 * @brief Disables the MAC Magic Packet Detection.
1894 * @param __HANDLE__ ETH Handle.
1895 * @retval None
1896 */
1897#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1898
1899/**
1900 * @brief Enables the MAC Power Down.
1901 * @param __HANDLE__ ETH Handle
1902 * @retval None
1903 */
1904#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
1905
1906/**
1907 * @brief Disables the MAC Power Down.
1908 * @param __HANDLE__ ETH Handle
1909 * @retval None
1910 */
1911#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
1912
1913/**
1914 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
1915 * @param __HANDLE__ ETH Handle.
1916 * @param __FLAG__ specifies the flag to check.
1917 * This parameter can be one of the following values:
1918 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
1919 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
1920 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
1921 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
1922 */
1923#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
1924
1925/**
1926 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
1927 * @param __HANDLE__ ETH Handle.
1928 * @retval None
1929 */
1930#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
1931
1932/**
1933 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
1934 * @param __HANDLE__ ETH Handle.
1935 * @retval None
1936 */
1937#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
1938 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
1939
1940/**
1941 * @brief Enables the MMC Counter Freeze.
1942 * @param __HANDLE__ ETH Handle.
1943 * @retval None
1944 */
1945#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
1946
1947/**
1948 * @brief Disables the MMC Counter Freeze.
1949 * @param __HANDLE__ ETH Handle.
1950 * @retval None
1951 */
1952#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
1953
1954/**
1955 * @brief Enables the MMC Reset On Read.
1956 * @param __HANDLE__ ETH Handle.
1957 * @retval None
1958 */
1959#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
1960
1961/**
1962 * @brief Disables the MMC Reset On Read.
1963 * @param __HANDLE__ ETH Handle.
1964 * @retval None
1965 */
1966#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
1967
1968/**
1969 * @brief Enables the MMC Counter Stop Rollover.
1970 * @param __HANDLE__ ETH Handle.
1971 * @retval None
1972 */
1973#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
1974
1975/**
1976 * @brief Disables the MMC Counter Stop Rollover.
1977 * @param __HANDLE__ ETH Handle.
1978 * @retval None
1979 */
1980#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
1981
1982/**
1983 * @brief Resets the MMC Counters.
1984 * @param __HANDLE__ ETH Handle.
1985 * @retval None
1986 */
1987#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
1988
1989/**
1990 * @brief Enables the specified ETHERNET MMC Rx interrupts.
1991 * @param __HANDLE__ ETH Handle.
1992 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
1993 * This parameter can be one of the following values:
1994 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
1995 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
1996 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
1997 * @retval None
1998 */
1999#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
2000/**
2001 * @brief Disables the specified ETHERNET MMC Rx interrupts.
2002 * @param __HANDLE__ ETH Handle.
2003 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2004 * This parameter can be one of the following values:
2005 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
2006 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
2007 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
2008 * @retval None
2009 */
2010#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
2011/**
2012 * @brief Enables the specified ETHERNET MMC Tx interrupts.
2013 * @param __HANDLE__ ETH Handle.
2014 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2015 * This parameter can be one of the following values:
2016 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
2017 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2018 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2019 * @retval None
2020 */
2021#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
2022
2023/**
2024 * @brief Disables the specified ETHERNET MMC Tx interrupts.
2025 * @param __HANDLE__ ETH Handle.
2026 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2027 * This parameter can be one of the following values:
2028 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
2029 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2030 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2031 * @retval None
2032 */
2033#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
2034
2035/**
2036 * @brief Enables the ETH External interrupt line.
2037 * @retval None
2038 */
2039#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
2040
2041/**
2042 * @brief Disables the ETH External interrupt line.
2043 * @retval None
2044 */
2045#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
2046
2047/**
2048 * @brief Enable event on ETH External event line.
2049 * @retval None.
2050 */
2051#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
2052
2053/**
2054 * @brief Disable event on ETH External event line
2055 * @retval None.
2056 */
2057#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
2058
2059/**
2060 * @brief Get flag of the ETH External interrupt line.
2061 * @retval None
2062 */
2063#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
2064
2065/**
2066 * @brief Clear flag of the ETH External interrupt line.
2067 * @retval None
2068 */
2069#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
2070
2071/**
2072 * @brief Enables rising edge trigger to the ETH External interrupt line.
2073 * @retval None
2074 */
2075#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
2076
2077/**
2078 * @brief Disables the rising edge trigger to the ETH External interrupt line.
2079 * @retval None
2080 */
2081#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2082
2083/**
2084 * @brief Enables falling edge trigger to the ETH External interrupt line.
2085 * @retval None
2086 */
2087#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
2088
2089/**
2090 * @brief Disables falling edge trigger to the ETH External interrupt line.
2091 * @retval None
2092 */
2093#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2094
2095/**
2096 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
2097 * @retval None
2098 */
2099#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
2100 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
2101 }while(0U)
2102
2103/**
2104 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
2105 * @retval None
2106 */
2107#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2108 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2109 }while(0U)
2110
2111/**
2112 * @brief Generate a Software interrupt on selected EXTI line.
2113 * @retval None.
2114 */
2115#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
2116
2117/**
2118 * @}
2119 */
2120/* Exported functions --------------------------------------------------------*/
2121
2122/** @addtogroup ETH_Exported_Functions
2123 * @{
2124 */
2125
2126/* Initialization and de-initialization functions ****************************/
2127
2128/** @addtogroup ETH_Exported_Functions_Group1
2129 * @{
2130 */
2131HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
2132HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
2133void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
2134void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
2135HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
2136HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
2137/* Callbacks Register/UnRegister functions ***********************************/
2138#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
2139HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
2140HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
2141#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
2142
2143/**
2144 * @}
2145 */
2146/* IO operation functions ****************************************************/
2147
2148/** @addtogroup ETH_Exported_Functions_Group2
2149 * @{
2150 */
2151HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
2152HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
2153/* Communication with PHY functions*/
2154HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
2155HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
2156/* Non-Blocking mode: Interrupt */
2157HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
2158void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
2159/* Callback in non blocking modes (Interrupt) */
2160void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
2161void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
2162void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
2163/**
2164 * @}
2165 */
2166
2167/* Peripheral Control functions **********************************************/
2168
2169/** @addtogroup ETH_Exported_Functions_Group3
2170 * @{
2171 */
2172
2173HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
2174HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
2175HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
2176HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
2177/**
2178 * @}
2179 */
2180
2181/* Peripheral State functions ************************************************/
2182
2183/** @addtogroup ETH_Exported_Functions_Group4
2184 * @{
2185 */
2186HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
2187/**
2188 * @}
2189 */
2190
2191/**
2192 * @}
2193 */
2194
2195/**
2196 * @}
2197 */
2198
2199/**
2200 * @}
2201 */
2202
2203#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
2204 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
2205
2206#ifdef __cplusplus
2207}
2208#endif
2209
2210#endif /* __STM32F4xx_HAL_ETH_H */
2211
2212
2213/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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