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stm32f4xx_hal_fmpsmbus.h

Last change on this file was 1, checked in by AlexLir, 4 years ago

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_hal_fmpsmbus.h
4	* @author MCD Application Team
5	* @brief Header file of FMPSMBUS HAL module.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19
20	/* Define to prevent recursive inclusion -------------------------------------*/
21	#ifndef STM32F4xx_HAL_FMPSMBUS_H
22	#define STM32F4xx_HAL_FMPSMBUS_H
23
24	#ifdef __cplusplus
25	extern "C" {
26	#endif
27
28	#if defined(FMPI2C_CR1_PE)
29	/* Includes ------------------------------------------------------------------*/
30	#include "stm32f4xx_hal_def.h"
31	#include "stm32f4xx_hal_fmpsmbus_ex.h"
32
33	/** @addtogroup STM32F4xx_HAL_Driver
34	* @{
35	*/
36
37	/** @addtogroup FMPSMBUS
38	* @{
39	*/
40
41	/* Exported types ------------------------------------------------------------*/
42	/** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types
43	* @{
44	*/
45
46	/** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition
47	* @brief FMPSMBUS Configuration Structure definition
48	* @{
49	*/
50	typedef struct
51	{
52	uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value.
53	This parameter calculated by referring to FMPSMBUS initialization
54	section in Reference manual */
55	uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
56	This parameter can be a value of @ref FMPSMBUS_Analog_Filter */
57
58	uint32_t OwnAddress1; /*!< Specifies the first device own address.
59	This parameter can be a 7-bit or 10-bit address. */
60
61	uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
62	This parameter can be a value of @ref FMPSMBUS_addressing_mode */
63
64	uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
65	This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */
66
67	uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
68	This parameter can be a 7-bit address. */
69
70	uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
71	This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */
72
73	uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
74	This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */
75
76	uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
77	This parameter can be a value of @ref FMPSMBUS_nostretch_mode */
78
79	uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
80	This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */
81
82	uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
83	This parameter can be a value of @ref FMPSMBUS_peripheral_mode */
84
85	uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value.
86	(Enable bits and different timeout values)
87	This parameter calculated by referring to FMPSMBUS initialization
88	section in Reference manual */
89	} FMPSMBUS_InitTypeDef;
90	/**
91	* @}
92	*/
93
94	/** @defgroup HAL_state_definition HAL state definition
95	* @brief HAL State definition
96	* @{
97	*/
98	#define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /!< FMPSMBUS not yet initialized or disabled /
99	#define HAL_FMPSMBUS_STATE_READY (0x00000001U) /!< FMPSMBUS initialized and ready for use /
100	#define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /!< FMPSMBUS internal process is ongoing /
101	#define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /!< Master Data Transmission process is ongoing /
102	#define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /!< Master Data Reception process is ongoing /
103	#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /!< Slave Data Transmission process is ongoing /
104	#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /!< Slave Data Reception process is ongoing /
105	#define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /!< Timeout state /
106	#define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /!< Reception process is ongoing /
107	#define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /!< Address Listen Mode is ongoing /
108	/**
109	* @}
110	*/
111
112	/** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition
113	* @brief FMPSMBUS Error Code definition
114	* @{
115	*/
116	#define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /!< No error /
117	#define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /!< BERR error /
118	#define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /!< ARLO error /
119	#define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /!< ACKF error /
120	#define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /!< OVR error /
121	#define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /!< Timeout error /
122	#define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /!< Bus Timeout error /
123	#define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /!< Alert error /
124	#define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /!< PEC error /
125	#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
126	#define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /!< Invalid Callback error /
127	#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
128	#define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /!< Invalid Parameters error /
129	/**
130	* @}
131	*/
132
133	/** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition
134	* @brief FMPSMBUS handle Structure definition
135	* @{
136	*/
137	#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
138	typedef struct __FMPSMBUS_HandleTypeDef
139	#else
140	typedef struct
141	#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
142	{
143	FMPI2C_TypeDef Instance; /!< FMPSMBUS registers base address */
144
145	FMPSMBUS_InitTypeDef Init; /!< FMPSMBUS communication parameters /
146
147	uint8_t pBuffPtr; /!< Pointer to FMPSMBUS transfer buffer */
148
149	uint16_t XferSize; /!< FMPSMBUS transfer size /
150
151	__IO uint16_t XferCount; /!< FMPSMBUS transfer counter /
152
153	__IO uint32_t XferOptions; /!< FMPSMBUS transfer options /
154
155	__IO uint32_t PreviousState; /!< FMPSMBUS communication Previous state /
156
157	HAL_LockTypeDef Lock; /!< FMPSMBUS locking object /
158
159	__IO uint32_t State; /!< FMPSMBUS communication state /
160
161	__IO uint32_t ErrorCode; /!< FMPSMBUS Error code /
162
163	#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
164	void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef hfmpsmbus); /!< FMPSMBUS Master Tx Transfer completed callback */
165	void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef hfmpsmbus); /!< FMPSMBUS Master Rx Transfer completed callback */
166	void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef hfmpsmbus); /!< FMPSMBUS Slave Tx Transfer completed callback */
167	void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef hfmpsmbus); /!< FMPSMBUS Slave Rx Transfer completed callback */
168	void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef hfmpsmbus); /!< FMPSMBUS Listen Complete callback */
169	void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef hfmpsmbus); /!< FMPSMBUS Error callback */
170
171	void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /!< FMPSMBUS Slave Address Match callback */
172
173	void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef hfmpsmbus); /!< FMPSMBUS Msp Init callback */
174	void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef hfmpsmbus); /!< FMPSMBUS Msp DeInit callback */
175
176	#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
177	} FMPSMBUS_HandleTypeDef;
178
179	#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
180	/**
181	* @brief HAL FMPSMBUS Callback ID enumeration definition
182	*/
183	typedef enum
184	{
185	HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /!< FMPSMBUS Master Tx Transfer completed callback ID /
186	HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /!< FMPSMBUS Master Rx Transfer completed callback ID /
187	HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /!< FMPSMBUS Slave Tx Transfer completed callback ID /
188	HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /!< FMPSMBUS Slave Rx Transfer completed callback ID /
189	HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /!< FMPSMBUS Listen Complete callback ID /
190	HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /!< FMPSMBUS Error callback ID /
191
192	HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /!< FMPSMBUS Msp Init callback ID /
193	HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /!< FMPSMBUS Msp DeInit callback ID /
194
195	} HAL_FMPSMBUS_CallbackIDTypeDef;
196
197	/**
198	* @brief HAL FMPSMBUS Callback pointer definition
199	*/
200	typedef void (pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef hfmpsmbus); /!< pointer to an FMPSMBUS callback function /
201	typedef void (pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /!< pointer to an FMPSMBUS Address Match callback function /
202
203	#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
204	/**
205	* @}
206	*/
207
208	/**
209	* @}
210	*/
211	/* Exported constants --------------------------------------------------------*/
212
213	/** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants
214	* @{
215	*/
216
217	/** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter
218	* @{
219	*/
220	#define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U)
221	#define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF
222	/**
223	* @}
224	*/
225
226	/** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode
227	* @{
228	*/
229	#define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
230	#define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
231	/**
232	* @}
233	*/
234
235	/** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode
236	* @{
237	*/
238
239	#define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U)
240	#define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN
241	/**
242	* @}
243	*/
244
245	/** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks
246	* @{
247	*/
248
249	#define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U)
250	#define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U)
251	#define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U)
252	#define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U)
253	#define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U)
254	#define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U)
255	#define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U)
256	#define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U)
257	/**
258	* @}
259	*/
260
261
262	/** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode
263	* @{
264	*/
265	#define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U)
266	#define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN
267	/**
268	* @}
269	*/
270
271	/** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode
272	* @{
273	*/
274	#define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U)
275	#define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH
276	/**
277	* @}
278	*/
279
280	/** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode
281	* @{
282	*/
283	#define FMPSMBUS_PEC_DISABLE (0x00000000U)
284	#define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN
285	/**
286	* @}
287	*/
288
289	/** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode
290	* @{
291	*/
292	#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN
293	#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U)
294	#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN
295	/**
296	* @}
297	*/
298
299	/** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition
300	* @{
301	*/
302
303	#define FMPSMBUS_SOFTEND_MODE (0x00000000U)
304	#define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD
305	#define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND
306	#define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE
307	/**
308	* @}
309	*/
310
311	/** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition
312	* @{
313	*/
314
315	#define FMPSMBUS_NO_STARTSTOP (0x00000000U)
316	#define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U \| FMPI2C_CR2_STOP)
317	#define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U \| FMPI2C_CR2_START \| FMPI2C_CR2_RD_WRN)
318	#define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U \| FMPI2C_CR2_START)
319	/**
320	* @}
321	*/
322
323	/** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition
324	* @{
325	*/
326
327	/* List of XferOptions in usage of :
328	* 1- Restart condition when direction change
329	* 2- No Restart condition in other use cases
330	*/
331	#define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE
332	#define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE \| FMPSMBUS_SOFTEND_MODE))
333	#define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE
334	#define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE
335	#define FMPSMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_SOFTEND_MODE \| FMPSMBUS_SENDPEC_MODE))
336	#define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE \| FMPSMBUS_SENDPEC_MODE))
337	#define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE \| FMPSMBUS_SENDPEC_MODE))
338
339	/* List of XferOptions in usage of :
340	* 1- Restart condition in all use cases (direction change or not)
341	*/
342	#define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
343	#define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
344	#define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
345	#define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
346	/**
347	* @}
348	*/
349
350	/** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition
351	* @brief FMPSMBUS Interrupt definition
352	* Elements values convention: 0xXXXXXXXX
353	* - XXXXXXXX : Interrupt control mask
354	* @{
355	*/
356	#define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE
357	#define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE
358	#define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE
359	#define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE
360	#define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE
361	#define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE
362	#define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE
363	#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI \| FMPSMBUS_IT_TCI \| FMPSMBUS_IT_STOPI \| FMPSMBUS_IT_NACKI \| \
364	FMPSMBUS_IT_TXI)
365	#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI \| FMPSMBUS_IT_TCI \| FMPSMBUS_IT_NACKI \| FMPSMBUS_IT_RXI)
366	#define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI)
367	#define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI \| FMPSMBUS_IT_STOPI \| FMPSMBUS_IT_NACKI)
368	/**
369	* @}
370	*/
371
372	/** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition
373	* @brief Flag definition
374	* Elements values convention: 0xXXXXYYYY
375	* - XXXXXXXX : Flag mask
376	* @{
377	*/
378
379	#define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE
380	#define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS
381	#define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE
382	#define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR
383	#define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF
384	#define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF
385	#define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC
386	#define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR
387	#define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR
388	#define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO
389	#define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR
390	#define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR
391	#define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
392	#define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT
393	#define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY
394	#define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR
395	/**
396	* @}
397	*/
398
399	/**
400	* @}
401	*/
402
403	/* Exported macros ------------------------------------------------------------*/
404	/** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros
405	* @{
406	*/
407
408	/** @brief Reset FMPSMBUS handle state.
409	* @param __HANDLE__ specifies the FMPSMBUS Handle.
410	* @retval None
411	*/
412	#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
413	#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
414	(__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \
415	(__HANDLE__)->MspInitCallback = NULL; \
416	(__HANDLE__)->MspDeInitCallback = NULL; \
417	} while(0)
418	#else
419	#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET)
420	#endif
421
422	/** @brief Enable the specified FMPSMBUS interrupts.
423	* @param __HANDLE__ specifies the FMPSMBUS Handle.
424	* @param __INTERRUPT__ specifies the interrupt source to enable.
425	* This parameter can be one of the following values:
426	* @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
427	* @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
428	* @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
429	* @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
430	* @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
431	* @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
432	* @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
433	*
434	* @retval None
435	*/
436	#define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 \|= (__INTERRUPT__))
437
438	/** @brief Disable the specified FMPSMBUS interrupts.
439	* @param __HANDLE__ specifies the FMPSMBUS Handle.
440	* @param __INTERRUPT__ specifies the interrupt source to disable.
441	* This parameter can be one of the following values:
442	* @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
443	* @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
444	* @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
445	* @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
446	* @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
447	* @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
448	* @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
449	*
450	* @retval None
451	*/
452	#define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
453
454	/** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not.
455	* @param __HANDLE__ specifies the FMPSMBUS Handle.
456	* @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check.
457	* This parameter can be one of the following values:
458	* @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
459	* @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
460	* @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
461	* @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
462	* @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
463	* @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
464	* @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
465	*
466	* @retval The new state of __IT__ (SET or RESET).
467	*/
468	#define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
469	((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
470
471	/** @brief Check whether the specified FMPSMBUS flag is set or not.
472	* @param __HANDLE__ specifies the FMPSMBUS Handle.
473	* @param __FLAG__ specifies the flag to check.
474	* This parameter can be one of the following values:
475	* @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty
476	* @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status
477	* @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty
478	* @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode)
479	* @arg @ref FMPSMBUS_FLAG_AF NACK received flag
480	* @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag
481	* @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode)
482	* @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload
483	* @arg @ref FMPSMBUS_FLAG_BERR Bus error
484	* @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost
485	* @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun
486	* @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception
487	* @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
488	* @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert
489	* @arg @ref FMPSMBUS_FLAG_BUSY Bus busy
490	* @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode)
491	*
492	* @retval The new state of __FLAG__ (SET or RESET).
493	*/
494	#define FMPSMBUS_FLAG_MASK (0x0001FFFFU)
495	#define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
496	(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
497
498	/** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit.
499	* @param __HANDLE__ specifies the FMPSMBUS Handle.
500	* @param __FLAG__ specifies the flag to clear.
501	* This parameter can be any combination of the following values:
502	* @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode)
503	* @arg @ref FMPSMBUS_FLAG_AF NACK received flag
504	* @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag
505	* @arg @ref FMPSMBUS_FLAG_BERR Bus error
506	* @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost
507	* @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun
508	* @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception
509	* @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
510	* @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert
511	*
512	* @retval None
513	*/
514	#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
515
516	/** @brief Enable the specified FMPSMBUS peripheral.
517	* @param __HANDLE__ specifies the FMPSMBUS Handle.
518	* @retval None
519	*/
520	#define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
521
522	/** @brief Disable the specified FMPSMBUS peripheral.
523	* @param __HANDLE__ specifies the FMPSMBUS Handle.
524	* @retval None
525	*/
526	#define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
527
528	/** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode.
529	* @param __HANDLE__ specifies the FMPSMBUS Handle.
530	* @retval None
531	*/
532	#define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK))
533
534	/**
535	* @}
536	*/
537
538
539	/* Private constants ---------------------------------------------------------*/
540
541	/* Private macros ------------------------------------------------------------*/
542	/** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros
543	* @{
544	*/
545
546	#define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) \|\| \
547	((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE))
548
549	#define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
550
551	#define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) \|\| \
552	((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT))
553
554	#define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) \|\| \
555	((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE))
556
557	#define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) \|\| \
558	((MASK) == FMPSMBUS_OA2_MASK01) \|\| \
559	((MASK) == FMPSMBUS_OA2_MASK02) \|\| \
560	((MASK) == FMPSMBUS_OA2_MASK03) \|\| \
561	((MASK) == FMPSMBUS_OA2_MASK04) \|\| \
562	((MASK) == FMPSMBUS_OA2_MASK05) \|\| \
563	((MASK) == FMPSMBUS_OA2_MASK06) \|\| \
564	((MASK) == FMPSMBUS_OA2_MASK07))
565
566	#define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) \|\| \
567	((CALL) == FMPSMBUS_GENERALCALL_ENABLE))
568
569	#define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) \|\| \
570	((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE))
571
572	#define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) \|\| \
573	((PEC) == FMPSMBUS_PEC_ENABLE))
574
575	#define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) \|\| \
576	((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) \|\| \
577	((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))
578
579	#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) \|\| \
580	((MODE) == FMPSMBUS_AUTOEND_MODE) \|\| \
581	((MODE) == FMPSMBUS_SOFTEND_MODE) \|\| \
582	((MODE) == FMPSMBUS_SENDPEC_MODE) \|\| \
583	((MODE) == (FMPSMBUS_RELOAD_MODE \| FMPSMBUS_SENDPEC_MODE)) \|\| \
584	((MODE) == (FMPSMBUS_AUTOEND_MODE \| FMPSMBUS_SENDPEC_MODE)) \|\| \
585	((MODE) == (FMPSMBUS_AUTOEND_MODE \| FMPSMBUS_RELOAD_MODE)) \|\| \
586	((MODE) == (FMPSMBUS_AUTOEND_MODE \| FMPSMBUS_SENDPEC_MODE \| FMPSMBUS_RELOAD_MODE )))
587
588
589	#define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) \|\| \
590	((REQUEST) == FMPSMBUS_GENERATE_START_READ) \|\| \
591	((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) \|\| \
592	((REQUEST) == FMPSMBUS_NO_STARTSTOP))
593
594
595	#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) \|\| \
596	((REQUEST) == FMPSMBUS_FIRST_FRAME) \|\| \
597	((REQUEST) == FMPSMBUS_NEXT_FRAME) \|\| \
598	((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) \|\| \
599	((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) \|\| \
600	((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) \|\| \
601	((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) \|\| \
602	((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC))
603
604	#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) \|\| \
605	((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) \|\| \
606	((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) \|\| \
607	((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
608
609	#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
610	(uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN \| FMPI2C_CR1_SMBDEN \| FMPI2C_CR1_PECEN)))
611	#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
612	(uint32_t)~((uint32_t)(FMPI2C_CR2_SADD \| FMPI2C_CR2_HEAD10R \| FMPI2C_CR2_NBYTES \| FMPI2C_CR2_RELOAD \| FMPI2C_CR2_RD_WRN)))
613
614	#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) \| (FMPI2C_CR2_START) \| (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
615	(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) \| (FMPI2C_CR2_ADD10) \| (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
616
617	#define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U)
618	#define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)
619	#define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
620	#define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE)
621	#define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN)
622
623	#define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \
624	((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
625	#define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
626
627	#define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
628	#define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
629
630	/**
631	* @}
632	*/
633
634	/* Exported functions --------------------------------------------------------*/
635	/** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions
636	* @{
637	*/
638
639	/** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
640	* @{
641	*/
642
643	/* Initialization and de-initialization functions ****************************/
644	HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus);
645	HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
646	void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
647	void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
648	HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter);
649	HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter);
650
651	/* Callbacks Register/UnRegister functions ***********************************/
652	#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
653	HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
654	pFMPSMBUS_CallbackTypeDef pCallback);
655	HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID);
656
657	HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback);
658	HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
659	#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
660	/**
661	* @}
662	*/
663
664	/** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions
665	* @{
666	*/
667
668	/* IO operation functions *****************************************************/
669	/** @addtogroup Blocking_mode_Polling Blocking mode Polling
670	* @{
671	*/
672	/******* Blocking mode: Polling */
673	HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials,
674	uint32_t Timeout);
675	/**
676	* @}
677	*/
678
679	/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
680	* @{
681	*/
682	/******* Non-Blocking mode: Interrupt */
683	HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef hfmpsmbus, uint16_t DevAddress, uint8_t pData,
684	uint16_t Size, uint32_t XferOptions);
685	HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef hfmpsmbus, uint16_t DevAddress, uint8_t pData,
686	uint16_t Size, uint32_t XferOptions);
687	HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress);
688	HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef hfmpsmbus, uint8_t pData, uint16_t Size,
689	uint32_t XferOptions);
690	HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef hfmpsmbus, uint8_t pData, uint16_t Size,
691	uint32_t XferOptions);
692
693	HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
694	HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
695	HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
696	HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
697	/**
698	* @}
699	*/
700
701	/** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
702	* @{
703	*/
704	/******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
705	void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
706	void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
707	void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
708	void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
709	void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
710	void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
711	void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
712	void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
713	void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
714
715	/**
716	* @}
717	*/
718
719	/** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
720	* @{
721	*/
722
723	/* Peripheral State and Errors functions **************************************************/
724	uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus);
725	uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus);
726
727	/**
728	* @}
729	*/
730
731	/**
732	* @}
733	*/
734
735	/* Private Functions ---------------------------------------------------------*/
736	/** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions
737	* @{
738	*/
739	/* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */
740	/**
741	* @}
742	*/
743
744	/**
745	* @}
746	*/
747
748	/**
749	* @}
750	*/
751
752	/**
753	* @}
754	*/
755
756	#endif /* FMPI2C_CR1_PE */
757	#ifdef __cplusplus
758	}
759	#endif
760
761
762	#endif /* STM32F4xx_HAL_FMPSMBUS_H */
763
764	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h

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