source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h

Last change on this file was 1, checked in by AlexLir, 3 years ago
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_i2s.h
4 * @author MCD Application Team
5 * @brief Header file of I2S HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef STM32F4xx_HAL_I2S_H
22#define STM32F4xx_HAL_I2S_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f4xx_hal_def.h"
30
31/** @addtogroup STM32F4xx_HAL_Driver
32 * @{
33 */
34
35/** @addtogroup I2S
36 * @{
37 */
38
39/* Exported types ------------------------------------------------------------*/
40/** @defgroup I2S_Exported_Types I2S Exported Types
41 * @{
42 */
43
44/**
45 * @brief I2S Init structure definition
46 */
47typedef struct
48{
49 uint32_t Mode; /*!< Specifies the I2S operating mode.
50 This parameter can be a value of @ref I2S_Mode */
51
52 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
53 This parameter can be a value of @ref I2S_Standard */
54
55 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
56 This parameter can be a value of @ref I2S_Data_Format */
57
58 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
59 This parameter can be a value of @ref I2S_MCLK_Output */
60
61 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
62 This parameter can be a value of @ref I2S_Audio_Frequency */
63
64 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
65 This parameter can be a value of @ref I2S_Clock_Polarity */
66
67 uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
68 This parameter can be a value of @ref I2S_Clock_Source */
69 uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
70 This parameter can be a value of @ref I2S_FullDuplex_Mode */
71} I2S_InitTypeDef;
72
73/**
74 * @brief HAL State structures definition
75 */
76typedef enum
77{
78 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
79 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
80 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
81 HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
82 HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
83 HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
84 HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
85 HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
86} HAL_I2S_StateTypeDef;
87
88/**
89 * @brief I2S handle Structure definition
90 */
91typedef struct __I2S_HandleTypeDef
92{
93 SPI_TypeDef *Instance; /*!< I2S registers base address */
94
95 I2S_InitTypeDef Init; /*!< I2S communication parameters */
96
97 uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
98
99 __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
100
101 __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
102
103 uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
104
105 __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
106
107 __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
108 (This field is initialized at the
109 same value as transfer size at the
110 beginning of the transfer and
111 decremented when a sample is received
112 NbSamplesReceived = RxBufferSize-RxBufferCount) */
113 void (*IrqHandlerISR)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */
114
115 DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
116
117 DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
118
119 __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
120
121 __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
122
123 __IO uint32_t ErrorCode; /*!< I2S Error code
124 This parameter can be a value of @ref I2S_Error */
125
126#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
127 void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
128 void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
129 void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */
130 void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
131 void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
132 void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */
133 void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
134 void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
135 void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
136
137#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
138} I2S_HandleTypeDef;
139
140#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
141/**
142 * @brief HAL I2S Callback ID enumeration definition
143 */
144typedef enum
145{
146 HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
147 HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
148 HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< I2S TxRx Completed callback ID */
149 HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
150 HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
151 HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< I2S TxRx Half Completed callback ID */
152 HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
153 HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
154 HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
155
156} HAL_I2S_CallbackIDTypeDef;
157
158/**
159 * @brief HAL I2S Callback pointer definition
160 */
161typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
162
163#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
164/**
165 * @}
166 */
167
168/* Exported constants --------------------------------------------------------*/
169/** @defgroup I2S_Exported_Constants I2S Exported Constants
170 * @{
171 */
172/** @defgroup I2S_Error I2S Error
173 * @{
174 */
175#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
176#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
177#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
178#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
179#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
180#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
181#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
182#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
183#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
184#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
185/**
186 * @}
187 */
188
189/** @defgroup I2S_Mode I2S Mode
190 * @{
191 */
192#define I2S_MODE_SLAVE_TX (0x00000000U)
193#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
194#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
195#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
196/**
197 * @}
198 */
199
200/** @defgroup I2S_Standard I2S Standard
201 * @{
202 */
203#define I2S_STANDARD_PHILIPS (0x00000000U)
204#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
205#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
206#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
207#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
208/**
209 * @}
210 */
211
212/** @defgroup I2S_Data_Format I2S Data Format
213 * @{
214 */
215#define I2S_DATAFORMAT_16B (0x00000000U)
216#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
217#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
218#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
219/**
220 * @}
221 */
222
223/** @defgroup I2S_MCLK_Output I2S MCLK Output
224 * @{
225 */
226#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
227#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
228/**
229 * @}
230 */
231
232/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
233 * @{
234 */
235#define I2S_AUDIOFREQ_192K (192000U)
236#define I2S_AUDIOFREQ_96K (96000U)
237#define I2S_AUDIOFREQ_48K (48000U)
238#define I2S_AUDIOFREQ_44K (44100U)
239#define I2S_AUDIOFREQ_32K (32000U)
240#define I2S_AUDIOFREQ_22K (22050U)
241#define I2S_AUDIOFREQ_16K (16000U)
242#define I2S_AUDIOFREQ_11K (11025U)
243#define I2S_AUDIOFREQ_8K (8000U)
244#define I2S_AUDIOFREQ_DEFAULT (2U)
245/**
246 * @}
247 */
248
249/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
250 * @{
251 */
252#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
253#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
254/**
255 * @}
256 */
257
258/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
259 * @{
260 */
261#define I2S_CPOL_LOW (0x00000000U)
262#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
263/**
264 * @}
265 */
266
267/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
268 * @{
269 */
270#define I2S_IT_TXE SPI_CR2_TXEIE
271#define I2S_IT_RXNE SPI_CR2_RXNEIE
272#define I2S_IT_ERR SPI_CR2_ERRIE
273/**
274 * @}
275 */
276
277/** @defgroup I2S_Flags_Definition I2S Flags Definition
278 * @{
279 */
280#define I2S_FLAG_TXE SPI_SR_TXE
281#define I2S_FLAG_RXNE SPI_SR_RXNE
282
283#define I2S_FLAG_UDR SPI_SR_UDR
284#define I2S_FLAG_OVR SPI_SR_OVR
285#define I2S_FLAG_FRE SPI_SR_FRE
286
287#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
288#define I2S_FLAG_BSY SPI_SR_BSY
289
290#define I2S_FLAG_MASK (SPI_SR_RXNE\
291 | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
292/**
293 * @}
294 */
295
296/** @defgroup I2S_Clock_Source I2S Clock Source Definition
297 * @{
298 */
299#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx)
300#define I2S_CLOCK_PLL (0x00000000U)
301#define I2S_CLOCK_EXTERNAL (0x00000001U)
302#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
303 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
304
305#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
306#define I2S_CLOCK_PLL (0x00000000U)
307#define I2S_CLOCK_EXTERNAL (0x00000001U)
308#define I2S_CLOCK_PLLR (0x00000002U)
309#define I2S_CLOCK_PLLSRC (0x00000003U)
310#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
311
312#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
313#define I2S_CLOCK_PLLSRC (0x00000000U)
314#define I2S_CLOCK_EXTERNAL (0x00000001U)
315#define I2S_CLOCK_PLLR (0x00000002U)
316#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
317/**
318 * @}
319 */
320
321/**
322 * @}
323 */
324
325/* Exported macros -----------------------------------------------------------*/
326/** @defgroup I2S_Exported_macros I2S Exported Macros
327 * @{
328 */
329
330/** @brief Reset I2S handle state
331 * @param __HANDLE__ specifies the I2S Handle.
332 * @retval None
333 */
334#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
335#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
336 (__HANDLE__)->State = HAL_I2S_STATE_RESET; \
337 (__HANDLE__)->MspInitCallback = NULL; \
338 (__HANDLE__)->MspDeInitCallback = NULL; \
339 } while(0)
340#else
341#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
342#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
343
344/** @brief Enable the specified SPI peripheral (in I2S mode).
345 * @param __HANDLE__ specifies the I2S Handle.
346 * @retval None
347 */
348#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
349
350/** @brief Disable the specified SPI peripheral (in I2S mode).
351 * @param __HANDLE__ specifies the I2S Handle.
352 * @retval None
353 */
354#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
355
356/** @brief Enable the specified I2S interrupts.
357 * @param __HANDLE__ specifies the I2S Handle.
358 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
359 * This parameter can be one of the following values:
360 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
361 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
362 * @arg I2S_IT_ERR: Error interrupt enable
363 * @retval None
364 */
365#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
366
367/** @brief Disable the specified I2S interrupts.
368 * @param __HANDLE__ specifies the I2S Handle.
369 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
370 * This parameter can be one of the following values:
371 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
372 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
373 * @arg I2S_IT_ERR: Error interrupt enable
374 * @retval None
375 */
376#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
377
378/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
379 * @param __HANDLE__ specifies the I2S Handle.
380 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
381 * @param __INTERRUPT__ specifies the I2S interrupt source to check.
382 * This parameter can be one of the following values:
383 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
384 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
385 * @arg I2S_IT_ERR: Error interrupt enable
386 * @retval The new state of __IT__ (TRUE or FALSE).
387 */
388#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
389 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
390
391/** @brief Checks whether the specified I2S flag is set or not.
392 * @param __HANDLE__ specifies the I2S Handle.
393 * @param __FLAG__ specifies the flag to check.
394 * This parameter can be one of the following values:
395 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
396 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
397 * @arg I2S_FLAG_UDR: Underrun flag
398 * @arg I2S_FLAG_OVR: Overrun flag
399 * @arg I2S_FLAG_FRE: Frame error flag
400 * @arg I2S_FLAG_CHSIDE: Channel Side flag
401 * @arg I2S_FLAG_BSY: Busy flag
402 * @retval The new state of __FLAG__ (TRUE or FALSE).
403 */
404#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
405
406/** @brief Clears the I2S OVR pending flag.
407 * @param __HANDLE__ specifies the I2S Handle.
408 * @retval None
409 */
410#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
411 __IO uint32_t tmpreg_ovr = 0x00U; \
412 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
413 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
414 UNUSED(tmpreg_ovr); \
415 }while(0U)
416/** @brief Clears the I2S UDR pending flag.
417 * @param __HANDLE__ specifies the I2S Handle.
418 * @retval None
419 */
420#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
421 __IO uint32_t tmpreg_udr = 0x00U;\
422 tmpreg_udr = ((__HANDLE__)->Instance->SR);\
423 UNUSED(tmpreg_udr); \
424 }while(0U)
425/** @brief Flush the I2S DR Register.
426 * @param __HANDLE__ specifies the I2S Handle.
427 * @retval None
428 */
429#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
430 __IO uint32_t tmpreg_dr = 0x00U;\
431 tmpreg_dr = ((__HANDLE__)->Instance->DR);\
432 UNUSED(tmpreg_dr); \
433 }while(0U)
434/**
435 * @}
436 */
437
438/* Include I2S Extension module */
439#include "stm32f4xx_hal_i2s_ex.h"
440
441/* Exported functions --------------------------------------------------------*/
442/** @addtogroup I2S_Exported_Functions
443 * @{
444 */
445
446/** @addtogroup I2S_Exported_Functions_Group1
447 * @{
448 */
449/* Initialization/de-initialization functions ********************************/
450HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
451HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
452void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
453void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
454
455/* Callbacks Register/UnRegister functions ***********************************/
456#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
457HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
458 pI2S_CallbackTypeDef pCallback);
459HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
460#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
461/**
462 * @}
463 */
464
465/** @addtogroup I2S_Exported_Functions_Group2
466 * @{
467 */
468/* I/O operation functions ***************************************************/
469/* Blocking mode: Polling */
470HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
471HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
472
473/* Non-Blocking mode: Interrupt */
474HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
475HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
476void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
477
478/* Non-Blocking mode: DMA */
479HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
480HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
481
482HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
483HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
484HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
485
486/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
487void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
488void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
489void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
490void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
491void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
492/**
493 * @}
494 */
495
496/** @addtogroup I2S_Exported_Functions_Group3
497 * @{
498 */
499/* Peripheral Control and State functions ************************************/
500HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
501uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
502/**
503 * @}
504 */
505
506/**
507 * @}
508 */
509
510/* Private types -------------------------------------------------------------*/
511/* Private variables ---------------------------------------------------------*/
512/* Private constants ---------------------------------------------------------*/
513/* Private macros ------------------------------------------------------------*/
514/** @defgroup I2S_Private_Macros I2S Private Macros
515 * @{
516 */
517
518/** @brief Check whether the specified SPI flag is set or not.
519 * @param __SR__ copy of I2S SR register.
520 * @param __FLAG__ specifies the flag to check.
521 * This parameter can be one of the following values:
522 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
523 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
524 * @arg I2S_FLAG_UDR: Underrun error flag
525 * @arg I2S_FLAG_OVR: Overrun flag
526 * @arg I2S_FLAG_CHSIDE: Channel side flag
527 * @arg I2S_FLAG_BSY: Busy flag
528 * @retval SET or RESET.
529 */
530#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
531 & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
532
533/** @brief Check whether the specified SPI Interrupt is set or not.
534 * @param __CR2__ copy of I2S CR2 register.
535 * @param __INTERRUPT__ specifies the SPI interrupt source to check.
536 * This parameter can be one of the following values:
537 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
538 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
539 * @arg I2S_IT_ERR: Error interrupt enable
540 * @retval SET or RESET.
541 */
542#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
543 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
544
545/** @brief Checks if I2S Mode parameter is in allowed range.
546 * @param __MODE__ specifies the I2S Mode.
547 * This parameter can be a value of @ref I2S_Mode
548 * @retval None
549 */
550#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
551 ((__MODE__) == I2S_MODE_SLAVE_RX) || \
552 ((__MODE__) == I2S_MODE_MASTER_TX) || \
553 ((__MODE__) == I2S_MODE_MASTER_RX))
554
555#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
556 ((__STANDARD__) == I2S_STANDARD_MSB) || \
557 ((__STANDARD__) == I2S_STANDARD_LSB) || \
558 ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
559 ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
560
561#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
562 ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
563 ((__FORMAT__) == I2S_DATAFORMAT_24B) || \
564 ((__FORMAT__) == I2S_DATAFORMAT_32B))
565
566#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
567 ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
568
569#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
570 ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
571 ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
572
573#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
574 ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
575
576/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
577 * @param __CPOL__ specifies the I2S serial clock steady state.
578 * This parameter can be a value of @ref I2S_Clock_Polarity
579 * @retval None
580 */
581#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
582 ((__CPOL__) == I2S_CPOL_HIGH))
583
584#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx)
585#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
586 ((CLOCK) == I2S_CLOCK_PLL))
587#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
588 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
589
590#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined (STM32F413xx) || defined(STM32F423xx)
591#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
592 ((CLOCK) == I2S_CLOCK_PLL) ||\
593 ((CLOCK) == I2S_CLOCK_PLLSRC) ||\
594 ((CLOCK) == I2S_CLOCK_PLLR))
595#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
596
597#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
598#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
599 ((CLOCK) == I2S_CLOCK_PLLSRC) ||\
600 ((CLOCK) == I2S_CLOCK_PLLR))
601#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
602/**
603 * @}
604 */
605
606/**
607 * @}
608 */
609
610/**
611 * @}
612 */
613
614#ifdef __cplusplus
615}
616#endif
617
618#endif /* STM32F4xx_HAL_I2S_H */
619
620/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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