source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h@ 1

Last change on this file since 1 was 1, checked in by AlexLir, 3 years ago
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_nand.h
4 * @author MCD Application Team
5 * @brief Header file of NAND HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef __STM32F4xx_HAL_NAND_H
22#define __STM32F4xx_HAL_NAND_H
23
24#ifdef __cplusplus
25 extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
30 #include "stm32f4xx_ll_fsmc.h"
31#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
32
33#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
34 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
35 #include "stm32f4xx_ll_fmc.h"
36#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
37 STM32F479xx */
38
39/** @addtogroup STM32F4xx_HAL_Driver
40 * @{
41 */
42
43/** @addtogroup NAND
44 * @{
45 */
46
47#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
48 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
49 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
50
51/* Exported typedef ----------------------------------------------------------*/
52/* Exported types ------------------------------------------------------------*/
53/** @defgroup NAND_Exported_Types NAND Exported Types
54 * @{
55 */
56
57/**
58 * @brief HAL NAND State structures definition
59 */
60typedef enum
61{
62 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
63 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
64 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
65 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
66}HAL_NAND_StateTypeDef;
67
68/**
69 * @brief NAND Memory electronic signature Structure definition
70 */
71typedef struct
72{
73 /*<! NAND memory electronic signature maker and device IDs */
74
75 uint8_t Maker_Id;
76
77 uint8_t Device_Id;
78
79 uint8_t Third_Id;
80
81 uint8_t Fourth_Id;
82}NAND_IDTypeDef;
83
84/**
85 * @brief NAND Memory address Structure definition
86 */
87typedef struct
88{
89 uint16_t Page; /*!< NAND memory Page address */
90
91 uint16_t Plane; /*!< NAND memory Plane address */
92
93 uint16_t Block; /*!< NAND memory Block address */
94
95}NAND_AddressTypeDef;
96
97/**
98 * @brief NAND Memory info Structure definition
99 */
100typedef struct
101{
102 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
103 for 8 bits adressing or words for 16 bits addressing */
104
105 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
106 for 8 bits adressing or words for 16 bits addressing */
107
108 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
109
110 uint32_t BlockNbr; /*!< NAND memory number of total blocks */
111
112 uint32_t PlaneNbr; /*!< NAND memory number of planes */
113
114 uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */
115
116 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
117 parameter is mandatory for some NAND parts after the read
118 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
119 Example: Toshiba THTH58BYG3S0HBAI6.
120 This parameter could be ENABLE or DISABLE
121 Please check the Read Mode sequnece in the NAND device datasheet */
122}NAND_DeviceConfigTypeDef;
123
124/**
125 * @brief NAND handle Structure definition
126 */
127#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
128typedef struct __NAND_HandleTypeDef
129#else
130typedef struct
131#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
132{
133 FMC_NAND_TypeDef *Instance; /*!< Register base address */
134
135 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
136
137 HAL_LockTypeDef Lock; /*!< NAND locking object */
138
139 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
140
141 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
142
143#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
144 void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */
145 void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */
146 void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */
147#endif
148} NAND_HandleTypeDef;
149
150#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
151/**
152 * @brief HAL NAND Callback ID enumeration definition
153 */
154typedef enum
155{
156 HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
157 HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
158 HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
159}HAL_NAND_CallbackIDTypeDef;
160
161/**
162 * @brief HAL NAND Callback pointer definition
163 */
164typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
165#endif
166
167/**
168 * @}
169 */
170
171/* Exported constants --------------------------------------------------------*/
172/* Exported macros ------------------------------------------------------------*/
173/** @defgroup NAND_Exported_Macros NAND Exported Macros
174 * @{
175 */
176
177/** @brief Reset NAND handle state
178 * @param __HANDLE__ specifies the NAND handle.
179 * @retval None
180 */
181#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
182#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \
183 (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
184 (__HANDLE__)->MspInitCallback = NULL; \
185 (__HANDLE__)->MspDeInitCallback = NULL; \
186 } while(0)
187#else
188#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
189#endif
190
191/**
192 * @}
193 */
194
195/* Exported functions --------------------------------------------------------*/
196/** @addtogroup NAND_Exported_Functions NAND Exported Functions
197 * @{
198 */
199
200/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
201 * @{
202 */
203
204/* Initialization/de-initialization functions ********************************/
205/* Initialization/de-initialization functions ********************************/
206HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
207HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
208
209HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
210
211HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
212
213void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
214void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
215void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
216void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
217
218/**
219 * @}
220 */
221
222/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
223 * @{
224 */
225
226/* IO operation functions ****************************************************/
227HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
228
229HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
230HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
231HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
232HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
233
234HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
235HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
236HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
237HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
238
239HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
240
241uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
242uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
243
244#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
245/* NAND callback registering/unregistering */
246HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
247HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
248#endif
249
250/**
251 * @}
252 */
253
254/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
255 * @{
256 */
257
258/* NAND Control functions ****************************************************/
259HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
260HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
261HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
262
263/**
264 * @}
265 */
266
267/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
268 * @{
269 */
270/* NAND State functions *******************************************************/
271HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
272/**
273 * @}
274 */
275
276/**
277 * @}
278 */
279
280/* Private types -------------------------------------------------------------*/
281/* Private variables ---------------------------------------------------------*/
282/* Private constants ---------------------------------------------------------*/
283/** @defgroup NAND_Private_Constants NAND Private Constants
284 * @{
285 */
286#define NAND_DEVICE1 0x70000000U
287#define NAND_DEVICE2 0x80000000U
288#define NAND_WRITE_TIMEOUT 0x01000000U
289
290#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
291#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
292
293#define NAND_CMD_AREA_A ((uint8_t)0x00)
294#define NAND_CMD_AREA_B ((uint8_t)0x01)
295#define NAND_CMD_AREA_C ((uint8_t)0x50)
296#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
297
298#define NAND_CMD_WRITE0 ((uint8_t)0x80)
299#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
300#define NAND_CMD_ERASE0 ((uint8_t)0x60)
301#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
302#define NAND_CMD_READID ((uint8_t)0x90)
303#define NAND_CMD_STATUS ((uint8_t)0x70)
304#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
305#define NAND_CMD_RESET ((uint8_t)0xFF)
306
307/* NAND memory status */
308#define NAND_VALID_ADDRESS 0x00000100U
309#define NAND_INVALID_ADDRESS 0x00000200U
310#define NAND_TIMEOUT_ERROR 0x00000400U
311#define NAND_BUSY 0x00000000U
312#define NAND_ERROR 0x00000001U
313#define NAND_READY 0x00000040U
314/**
315 * @}
316 */
317
318/* Private macros ------------------------------------------------------------*/
319/** @defgroup NAND_Private_Macros NAND Private Macros
320 * @{
321 */
322
323/**
324 * @brief NAND memory address computation.
325 * @param __ADDRESS__ NAND memory address.
326 * @param __HANDLE__ NAND handle.
327 * @retval NAND Raw address value
328 */
329#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
330 (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
331
332/**
333 * @brief NAND memory Column address computation.
334 * @param __HANDLE__ NAND handle.
335 * @retval NAND Raw address value
336 */
337#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
338
339/**
340 * @brief NAND memory address cycling.
341 * @param __ADDRESS__ NAND memory address.
342 * @retval NAND address cycling value.
343 */
344#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
345#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
346#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
347#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
348
349/**
350 * @brief NAND memory Columns cycling.
351 * @param __ADDRESS__ NAND memory address.
352 * @retval NAND Column address cycling value.
353 */
354#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
355#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
356
357/**
358 * @}
359 */
360#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
361 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
362 STM32F446xx || STM32F469xx || STM32F479xx */
363
364/**
365 * @}
366 */
367/**
368 * @}
369 */
370
371/**
372 * @}
373 */
374
375#ifdef __cplusplus
376}
377#endif
378
379#endif /* __STM32F4xx_HAL_NAND_H */
380
381/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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