1 | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_hal_nand.h
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4 | * @author MCD Application Team
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5 | * @brief Header file of NAND HAL module.
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6 | ******************************************************************************
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7 | * @attention
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8 | *
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9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics.
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10 | * All rights reserved.</center></h2>
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11 | *
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12 | * This software component is licensed by ST under BSD 3-Clause license,
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13 | * the "License"; You may not use this file except in compliance with the
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14 | * License. You may obtain a copy of the License at:
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15 | * opensource.org/licenses/BSD-3-Clause
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16 | *
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17 | ******************************************************************************
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18 | */
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19 |
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20 | /* Define to prevent recursive inclusion -------------------------------------*/
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21 | #ifndef __STM32F4xx_HAL_NAND_H
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22 | #define __STM32F4xx_HAL_NAND_H
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23 |
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24 | #ifdef __cplusplus
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25 | extern "C" {
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26 | #endif
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27 |
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28 | /* Includes ------------------------------------------------------------------*/
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29 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
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30 | #include "stm32f4xx_ll_fsmc.h"
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31 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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32 |
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33 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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34 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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35 | #include "stm32f4xx_ll_fmc.h"
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36 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
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37 | STM32F479xx */
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38 |
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39 | /** @addtogroup STM32F4xx_HAL_Driver
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40 | * @{
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41 | */
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42 |
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43 | /** @addtogroup NAND
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44 | * @{
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45 | */
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46 |
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47 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
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48 | defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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49 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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50 |
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51 | /* Exported typedef ----------------------------------------------------------*/
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52 | /* Exported types ------------------------------------------------------------*/
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53 | /** @defgroup NAND_Exported_Types NAND Exported Types
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54 | * @{
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55 | */
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56 |
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57 | /**
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58 | * @brief HAL NAND State structures definition
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59 | */
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60 | typedef enum
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61 | {
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62 | HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
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63 | HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
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64 | HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
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65 | HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
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66 | }HAL_NAND_StateTypeDef;
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67 |
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68 | /**
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69 | * @brief NAND Memory electronic signature Structure definition
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70 | */
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71 | typedef struct
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72 | {
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73 | /*<! NAND memory electronic signature maker and device IDs */
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74 |
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75 | uint8_t Maker_Id;
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76 |
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77 | uint8_t Device_Id;
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78 |
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79 | uint8_t Third_Id;
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80 |
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81 | uint8_t Fourth_Id;
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82 | }NAND_IDTypeDef;
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83 |
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84 | /**
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85 | * @brief NAND Memory address Structure definition
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86 | */
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87 | typedef struct
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88 | {
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89 | uint16_t Page; /*!< NAND memory Page address */
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90 |
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91 | uint16_t Plane; /*!< NAND memory Plane address */
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92 |
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93 | uint16_t Block; /*!< NAND memory Block address */
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94 |
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95 | }NAND_AddressTypeDef;
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96 |
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97 | /**
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98 | * @brief NAND Memory info Structure definition
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99 | */
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100 | typedef struct
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101 | {
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102 | uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
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103 | for 8 bits adressing or words for 16 bits addressing */
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104 |
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105 | uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
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106 | for 8 bits adressing or words for 16 bits addressing */
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107 |
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108 | uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
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109 |
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110 | uint32_t BlockNbr; /*!< NAND memory number of total blocks */
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111 |
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112 | uint32_t PlaneNbr; /*!< NAND memory number of planes */
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113 |
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114 | uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */
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115 |
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116 | FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
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117 | parameter is mandatory for some NAND parts after the read
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118 | command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
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119 | Example: Toshiba THTH58BYG3S0HBAI6.
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120 | This parameter could be ENABLE or DISABLE
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121 | Please check the Read Mode sequnece in the NAND device datasheet */
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122 | }NAND_DeviceConfigTypeDef;
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123 |
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124 | /**
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125 | * @brief NAND handle Structure definition
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126 | */
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127 | #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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128 | typedef struct __NAND_HandleTypeDef
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129 | #else
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130 | typedef struct
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131 | #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
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132 | {
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133 | FMC_NAND_TypeDef *Instance; /*!< Register base address */
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134 |
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135 | FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
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136 |
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137 | HAL_LockTypeDef Lock; /*!< NAND locking object */
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138 |
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139 | __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
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140 |
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141 | NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
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142 |
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143 | #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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144 | void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */
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145 | void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */
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146 | void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */
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147 | #endif
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148 | } NAND_HandleTypeDef;
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149 |
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150 | #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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151 | /**
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152 | * @brief HAL NAND Callback ID enumeration definition
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153 | */
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154 | typedef enum
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155 | {
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156 | HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
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157 | HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
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158 | HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
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159 | }HAL_NAND_CallbackIDTypeDef;
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160 |
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161 | /**
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162 | * @brief HAL NAND Callback pointer definition
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163 | */
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164 | typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
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165 | #endif
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166 |
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167 | /**
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168 | * @}
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169 | */
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170 |
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171 | /* Exported constants --------------------------------------------------------*/
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172 | /* Exported macros ------------------------------------------------------------*/
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173 | /** @defgroup NAND_Exported_Macros NAND Exported Macros
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174 | * @{
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175 | */
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176 |
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177 | /** @brief Reset NAND handle state
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178 | * @param __HANDLE__ specifies the NAND handle.
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179 | * @retval None
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180 | */
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181 | #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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182 | #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \
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183 | (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
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184 | (__HANDLE__)->MspInitCallback = NULL; \
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185 | (__HANDLE__)->MspDeInitCallback = NULL; \
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186 | } while(0)
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187 | #else
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188 | #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
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189 | #endif
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190 |
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191 | /**
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192 | * @}
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193 | */
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194 |
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195 | /* Exported functions --------------------------------------------------------*/
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196 | /** @addtogroup NAND_Exported_Functions NAND Exported Functions
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197 | * @{
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198 | */
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199 |
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200 | /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
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201 | * @{
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202 | */
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203 |
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204 | /* Initialization/de-initialization functions ********************************/
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205 | /* Initialization/de-initialization functions ********************************/
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206 | HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
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207 | HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
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208 |
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209 | HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
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210 |
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211 | HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
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212 |
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213 | void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
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214 | void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
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215 | void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
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216 | void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
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217 |
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218 | /**
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219 | * @}
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220 | */
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221 |
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222 | /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
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223 | * @{
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224 | */
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225 |
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226 | /* IO operation functions ****************************************************/
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227 | HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
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228 |
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229 | HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
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230 | HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
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231 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
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232 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
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233 |
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234 | HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
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235 | HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
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236 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
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237 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
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238 |
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239 | HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
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240 |
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241 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
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242 | uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
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243 |
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244 | #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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245 | /* NAND callback registering/unregistering */
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246 | HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
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247 | HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
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248 | #endif
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249 |
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250 | /**
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251 | * @}
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252 | */
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253 |
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254 | /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
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255 | * @{
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256 | */
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257 |
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258 | /* NAND Control functions ****************************************************/
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259 | HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
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260 | HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
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261 | HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
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262 |
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263 | /**
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264 | * @}
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265 | */
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266 |
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267 | /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
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268 | * @{
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269 | */
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270 | /* NAND State functions *******************************************************/
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271 | HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
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272 | /**
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273 | * @}
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274 | */
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275 |
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276 | /**
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277 | * @}
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278 | */
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279 |
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280 | /* Private types -------------------------------------------------------------*/
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281 | /* Private variables ---------------------------------------------------------*/
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282 | /* Private constants ---------------------------------------------------------*/
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283 | /** @defgroup NAND_Private_Constants NAND Private Constants
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284 | * @{
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285 | */
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286 | #define NAND_DEVICE1 0x70000000U
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287 | #define NAND_DEVICE2 0x80000000U
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288 | #define NAND_WRITE_TIMEOUT 0x01000000U
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289 |
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290 | #define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
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291 | #define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
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292 |
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293 | #define NAND_CMD_AREA_A ((uint8_t)0x00)
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294 | #define NAND_CMD_AREA_B ((uint8_t)0x01)
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295 | #define NAND_CMD_AREA_C ((uint8_t)0x50)
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296 | #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
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297 |
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298 | #define NAND_CMD_WRITE0 ((uint8_t)0x80)
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299 | #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
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300 | #define NAND_CMD_ERASE0 ((uint8_t)0x60)
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301 | #define NAND_CMD_ERASE1 ((uint8_t)0xD0)
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302 | #define NAND_CMD_READID ((uint8_t)0x90)
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303 | #define NAND_CMD_STATUS ((uint8_t)0x70)
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304 | #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
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305 | #define NAND_CMD_RESET ((uint8_t)0xFF)
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306 |
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307 | /* NAND memory status */
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308 | #define NAND_VALID_ADDRESS 0x00000100U
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309 | #define NAND_INVALID_ADDRESS 0x00000200U
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310 | #define NAND_TIMEOUT_ERROR 0x00000400U
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311 | #define NAND_BUSY 0x00000000U
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312 | #define NAND_ERROR 0x00000001U
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313 | #define NAND_READY 0x00000040U
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314 | /**
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315 | * @}
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316 | */
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317 |
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318 | /* Private macros ------------------------------------------------------------*/
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319 | /** @defgroup NAND_Private_Macros NAND Private Macros
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320 | * @{
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321 | */
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322 |
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323 | /**
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324 | * @brief NAND memory address computation.
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325 | * @param __ADDRESS__ NAND memory address.
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326 | * @param __HANDLE__ NAND handle.
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327 | * @retval NAND Raw address value
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328 | */
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329 | #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
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330 | (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
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331 |
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332 | /**
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333 | * @brief NAND memory Column address computation.
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334 | * @param __HANDLE__ NAND handle.
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335 | * @retval NAND Raw address value
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336 | */
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337 | #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
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338 |
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339 | /**
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340 | * @brief NAND memory address cycling.
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341 | * @param __ADDRESS__ NAND memory address.
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342 | * @retval NAND address cycling value.
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343 | */
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344 | #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
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345 | #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
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346 | #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
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347 | #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
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348 |
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349 | /**
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350 | * @brief NAND memory Columns cycling.
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351 | * @param __ADDRESS__ NAND memory address.
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352 | * @retval NAND Column address cycling value.
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353 | */
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354 | #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
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355 | #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
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356 |
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357 | /**
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358 | * @}
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359 | */
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360 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
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361 | STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
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362 | STM32F446xx || STM32F469xx || STM32F479xx */
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363 |
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364 | /**
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365 | * @}
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366 | */
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367 | /**
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368 | * @}
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369 | */
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370 |
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371 | /**
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372 | * @}
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373 | */
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374 |
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375 | #ifdef __cplusplus
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376 | }
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377 | #endif
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378 |
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379 | #endif /* __STM32F4xx_HAL_NAND_H */
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380 |
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381 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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