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stm32f4xx_hal_rcc.h

Last change on this file was 1, checked in by AlexLir, 3 years ago

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_hal_rcc.h
4	* @author MCD Application Team
5	* @brief Header file of RCC HAL module.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19
20	/* Define to prevent recursive inclusion -------------------------------------*/
21	#ifndef __STM32F4xx_HAL_RCC_H
22	#define __STM32F4xx_HAL_RCC_H
23
24	#ifdef __cplusplus
25	extern "C" {
26	#endif
27
28	/* Includes ------------------------------------------------------------------*/
29	#include "stm32f4xx_hal_def.h"
30
31	/* Include RCC HAL Extended module */
32	/* (include on top of file since RCC structures are defined in extended file) */
33	#include "stm32f4xx_hal_rcc_ex.h"
34
35	/** @addtogroup STM32F4xx_HAL_Driver
36	* @{
37	*/
38
39	/** @addtogroup RCC
40	* @{
41	*/
42
43	/* Exported types ------------------------------------------------------------*/
44	/** @defgroup RCC_Exported_Types RCC Exported Types
45	* @{
46	*/
47
48	/**
49	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
50	*/
51	typedef struct
52	{
53	uint32_t OscillatorType; /*!< The oscillators to be configured.
54	This parameter can be a value of @ref RCC_Oscillator_Type */
55
56	uint32_t HSEState; /*!< The new state of the HSE.
57	This parameter can be a value of @ref RCC_HSE_Config */
58
59	uint32_t LSEState; /*!< The new state of the LSE.
60	This parameter can be a value of @ref RCC_LSE_Config */
61
62	uint32_t HSIState; /*!< The new state of the HSI.
63	This parameter can be a value of @ref RCC_HSI_Config */
64
65	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
66	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
67
68	uint32_t LSIState; /*!< The new state of the LSI.
69	This parameter can be a value of @ref RCC_LSI_Config */
70
71	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
72	}RCC_OscInitTypeDef;
73
74	/**
75	* @brief RCC System, AHB and APB busses clock configuration structure definition
76	*/
77	typedef struct
78	{
79	uint32_t ClockType; /*!< The clock to be configured.
80	This parameter can be a value of @ref RCC_System_Clock_Type */
81
82	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
83	This parameter can be a value of @ref RCC_System_Clock_Source */
84
85	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
86	This parameter can be a value of @ref RCC_AHB_Clock_Source */
87
88	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
89	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
90
91	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
92	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
93
94	}RCC_ClkInitTypeDef;
95
96	/**
97	* @}
98	*/
99
100	/* Exported constants --------------------------------------------------------*/
101	/** @defgroup RCC_Exported_Constants RCC Exported Constants
102	* @{
103	*/
104
105	/** @defgroup RCC_Oscillator_Type Oscillator Type
106	* @{
107	*/
108	#define RCC_OSCILLATORTYPE_NONE 0x00000000U
109	#define RCC_OSCILLATORTYPE_HSE 0x00000001U
110	#define RCC_OSCILLATORTYPE_HSI 0x00000002U
111	#define RCC_OSCILLATORTYPE_LSE 0x00000004U
112	#define RCC_OSCILLATORTYPE_LSI 0x00000008U
113	/**
114	* @}
115	*/
116
117	/** @defgroup RCC_HSE_Config HSE Config
118	* @{
119	*/
120	#define RCC_HSE_OFF 0x00000000U
121	#define RCC_HSE_ON RCC_CR_HSEON
122	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
123	/**
124	* @}
125	*/
126
127	/** @defgroup RCC_LSE_Config LSE Config
128	* @{
129	*/
130	#define RCC_LSE_OFF 0x00000000U
131	#define RCC_LSE_ON RCC_BDCR_LSEON
132	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON))
133	/**
134	* @}
135	*/
136
137	/** @defgroup RCC_HSI_Config HSI Config
138	* @{
139	*/
140	#define RCC_HSI_OFF ((uint8_t)0x00)
141	#define RCC_HSI_ON ((uint8_t)0x01)
142
143	#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
144	/**
145	* @}
146	*/
147
148	/** @defgroup RCC_LSI_Config LSI Config
149	* @{
150	*/
151	#define RCC_LSI_OFF ((uint8_t)0x00)
152	#define RCC_LSI_ON ((uint8_t)0x01)
153	/**
154	* @}
155	*/
156
157	/** @defgroup RCC_PLL_Config PLL Config
158	* @{
159	*/
160	#define RCC_PLL_NONE ((uint8_t)0x00)
161	#define RCC_PLL_OFF ((uint8_t)0x01)
162	#define RCC_PLL_ON ((uint8_t)0x02)
163	/**
164	* @}
165	*/
166
167	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
168	* @{
169	*/
170	#define RCC_PLLP_DIV2 0x00000002U
171	#define RCC_PLLP_DIV4 0x00000004U
172	#define RCC_PLLP_DIV6 0x00000006U
173	#define RCC_PLLP_DIV8 0x00000008U
174	/**
175	* @}
176	*/
177
178	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
179	* @{
180	*/
181	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
182	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
183	/**
184	* @}
185	*/
186
187	/** @defgroup RCC_System_Clock_Type System Clock Type
188	* @{
189	*/
190	#define RCC_CLOCKTYPE_SYSCLK 0x00000001U
191	#define RCC_CLOCKTYPE_HCLK 0x00000002U
192	#define RCC_CLOCKTYPE_PCLK1 0x00000004U
193	#define RCC_CLOCKTYPE_PCLK2 0x00000008U
194	/**
195	* @}
196	*/
197
198	/** @defgroup RCC_System_Clock_Source System Clock Source
199	* @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
200	* STM32F446xx devices.
201	* @{
202	*/
203	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
204	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
205	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
206	#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 \| RCC_CFGR_SW_1))
207	/**
208	* @}
209	*/
210
211	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
212	* @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
213	* STM32F446xx devices.
214	* @{
215	*/
216	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
217	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
218	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
219	#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 \| RCC_CFGR_SWS_1)) /!< PLLR used as system clock /
220	/**
221	* @}
222	*/
223
224	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
225	* @{
226	*/
227	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
228	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
229	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
230	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
231	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
232	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
233	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
234	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
235	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
236	/**
237	* @}
238	*/
239
240	/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
241	* @{
242	*/
243	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
244	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
245	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
246	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
247	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
248	/**
249	* @}
250	*/
251
252	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
253	* @{
254	*/
255	#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
256	#define RCC_RTCCLKSOURCE_LSE 0x00000100U
257	#define RCC_RTCCLKSOURCE_LSI 0x00000200U
258	#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
259	#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
260	#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
261	#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
262	#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
263	#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
264	#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
265	#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
266	#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
267	#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
268	#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
269	#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
270	#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
271	#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
272	#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
273	#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
274	#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
275	#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
276	#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
277	#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
278	#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
279	#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
280	#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
281	#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
282	#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
283	#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
284	#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
285	#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
286	#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
287	#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
288	#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
289	/**
290	* @}
291	*/
292
293	/** @defgroup RCC_MCO_Index MCO Index
294	* @{
295	*/
296	#define RCC_MCO1 0x00000000U
297	#define RCC_MCO2 0x00000001U
298	/**
299	* @}
300	*/
301
302	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
303	* @{
304	*/
305	#define RCC_MCO1SOURCE_HSI 0x00000000U
306	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
307	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
308	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
309	/**
310	* @}
311	*/
312
313	/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
314	* @{
315	*/
316	#define RCC_MCODIV_1 0x00000000U
317	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
318	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
319	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
320	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
321	/**
322	* @}
323	*/
324
325	/** @defgroup RCC_Interrupt Interrupts
326	* @{
327	*/
328	#define RCC_IT_LSIRDY ((uint8_t)0x01)
329	#define RCC_IT_LSERDY ((uint8_t)0x02)
330	#define RCC_IT_HSIRDY ((uint8_t)0x04)
331	#define RCC_IT_HSERDY ((uint8_t)0x08)
332	#define RCC_IT_PLLRDY ((uint8_t)0x10)
333	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
334	#define RCC_IT_CSS ((uint8_t)0x80)
335	/**
336	* @}
337	*/
338
339	/** @defgroup RCC_Flag Flags
340	* Elements values convention: 0XXYYYYYb
341	* - YYYYY : Flag position in the register
342	* - 0XX : Register index
343	* - 01: CR register
344	* - 10: BDCR register
345	* - 11: CSR register
346	* @{
347	*/
348	/* Flags in the CR register */
349	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
350	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
351	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
352	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
353
354	/* Flags in the BDCR register */
355	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
356
357	/* Flags in the CSR register */
358	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
359	#define RCC_FLAG_BORRST ((uint8_t)0x79)
360	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
361	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
362	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
363	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
364	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
365	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
366	/**
367	* @}
368	*/
369
370	/**
371	* @}
372	*/
373
374	/* Exported macro ------------------------------------------------------------*/
375	/** @defgroup RCC_Exported_Macros RCC Exported Macros
376	* @{
377	*/
378
379	/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
380	* @brief Enable or disable the AHB1 peripheral clock.
381	* @note After reset, the peripheral clock (used for registers read/write access)
382	* is disabled and the application software has to enable this clock before
383	* using it.
384	* @{
385	*/
386	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
387	__IO uint32_t tmpreg = 0x00U; \
388	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
389	/* Delay after an RCC peripheral clock enabling */ \
390	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
391	UNUSED(tmpreg); \
392	} while(0U)
393	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
394	__IO uint32_t tmpreg = 0x00U; \
395	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
396	/* Delay after an RCC peripheral clock enabling */ \
397	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
398	UNUSED(tmpreg); \
399	} while(0U)
400	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
401	__IO uint32_t tmpreg = 0x00U; \
402	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
403	/* Delay after an RCC peripheral clock enabling */ \
404	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
405	UNUSED(tmpreg); \
406	} while(0U)
407	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
408	__IO uint32_t tmpreg = 0x00U; \
409	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
410	/* Delay after an RCC peripheral clock enabling */ \
411	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
412	UNUSED(tmpreg); \
413	} while(0U)
414	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
415	__IO uint32_t tmpreg = 0x00U; \
416	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
417	/* Delay after an RCC peripheral clock enabling */ \
418	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
419	UNUSED(tmpreg); \
420	} while(0U)
421	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
422	__IO uint32_t tmpreg = 0x00U; \
423	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
424	/* Delay after an RCC peripheral clock enabling */ \
425	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
426	UNUSED(tmpreg); \
427	} while(0U)
428
429	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
430	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
431	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
432	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
433	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
434	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
435	/**
436	* @}
437	*/
438
439	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
440	* @brief Get the enable or disable status of the AHB1 peripheral clock.
441	* @note After reset, the peripheral clock (used for registers read/write access)
442	* is disabled and the application software has to enable this clock before
443	* using it.
444	* @{
445	*/
446	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
447	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
448	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
449	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
450	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
451	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
452
453	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
454	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
455	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
456	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
457	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
458	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
459	/**
460	* @}
461	*/
462
463	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
464	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
465	* @note After reset, the peripheral clock (used for registers read/write access)
466	* is disabled and the application software has to enable this clock before
467	* using it.
468	* @{
469	*/
470	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
471	__IO uint32_t tmpreg = 0x00U; \
472	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
473	/* Delay after an RCC peripheral clock enabling */ \
474	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
475	UNUSED(tmpreg); \
476	} while(0U)
477	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
478	__IO uint32_t tmpreg = 0x00U; \
479	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
480	/* Delay after an RCC peripheral clock enabling */ \
481	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
482	UNUSED(tmpreg); \
483	} while(0U)
484	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
485	__IO uint32_t tmpreg = 0x00U; \
486	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
487	/* Delay after an RCC peripheral clock enabling */ \
488	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
489	UNUSED(tmpreg); \
490	} while(0U)
491	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
492	__IO uint32_t tmpreg = 0x00U; \
493	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
494	/* Delay after an RCC peripheral clock enabling */ \
495	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
496	UNUSED(tmpreg); \
497	} while(0U)
498	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
499	__IO uint32_t tmpreg = 0x00U; \
500	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
501	/* Delay after an RCC peripheral clock enabling */ \
502	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
503	UNUSED(tmpreg); \
504	} while(0U)
505	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
506	__IO uint32_t tmpreg = 0x00U; \
507	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
508	/* Delay after an RCC peripheral clock enabling */ \
509	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
510	UNUSED(tmpreg); \
511	} while(0U)
512	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
513	__IO uint32_t tmpreg = 0x00U; \
514	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
515	/* Delay after an RCC peripheral clock enabling */ \
516	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
517	UNUSED(tmpreg); \
518	} while(0U)
519
520	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
521	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
522	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
523	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
524	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
525	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
526	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
527	/**
528	* @}
529	*/
530
531	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
532	* @brief Get the enable or disable status of the APB1 peripheral clock.
533	* @note After reset, the peripheral clock (used for registers read/write access)
534	* is disabled and the application software has to enable this clock before
535	* using it.
536	* @{
537	*/
538	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
539	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
540	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
541	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
542	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
543	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
544	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
545
546	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
547	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
548	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
549	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
550	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
551	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
552	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
553	/**
554	* @}
555	*/
556
557	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
558	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
559	* @note After reset, the peripheral clock (used for registers read/write access)
560	* is disabled and the application software has to enable this clock before
561	* using it.
562	* @{
563	*/
564	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
565	__IO uint32_t tmpreg = 0x00U; \
566	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
567	/* Delay after an RCC peripheral clock enabling */ \
568	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
569	UNUSED(tmpreg); \
570	} while(0U)
571	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
572	__IO uint32_t tmpreg = 0x00U; \
573	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
574	/* Delay after an RCC peripheral clock enabling */ \
575	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
576	UNUSED(tmpreg); \
577	} while(0U)
578	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
579	__IO uint32_t tmpreg = 0x00U; \
580	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
581	/* Delay after an RCC peripheral clock enabling */ \
582	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
583	UNUSED(tmpreg); \
584	} while(0U)
585	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
586	__IO uint32_t tmpreg = 0x00U; \
587	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
588	/* Delay after an RCC peripheral clock enabling */ \
589	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
590	UNUSED(tmpreg); \
591	} while(0U)
592	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
593	__IO uint32_t tmpreg = 0x00U; \
594	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
595	/* Delay after an RCC peripheral clock enabling */ \
596	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
597	UNUSED(tmpreg); \
598	} while(0U)
599	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
600	__IO uint32_t tmpreg = 0x00U; \
601	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
602	/* Delay after an RCC peripheral clock enabling */ \
603	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
604	UNUSED(tmpreg); \
605	} while(0U)
606	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
607	__IO uint32_t tmpreg = 0x00U; \
608	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
609	/* Delay after an RCC peripheral clock enabling */ \
610	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
611	UNUSED(tmpreg); \
612	} while(0U)
613	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
614	__IO uint32_t tmpreg = 0x00U; \
615	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
616	/* Delay after an RCC peripheral clock enabling */ \
617	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
618	UNUSED(tmpreg); \
619	} while(0U)
620
621	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
622	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
623	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
624	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
625	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
626	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
627	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
628	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
629	/**
630	* @}
631	*/
632
633	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
634	* @brief Get the enable or disable status of the APB2 peripheral clock.
635	* @note After reset, the peripheral clock (used for registers read/write access)
636	* is disabled and the application software has to enable this clock before
637	* using it.
638	* @{
639	*/
640	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
641	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
642	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
643	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
644	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
645	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
646	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
647	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
648
649	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
650	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
651	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
652	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
653	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
654	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
655	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
656	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
657	/**
658	* @}
659	*/
660
661	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
662	* @brief Force or release AHB1 peripheral reset.
663	* @{
664	*/
665	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
666	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
667	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
668	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
669	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
670	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
671	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
672
673	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
674	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
675	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
676	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
677	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
678	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
679	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
680	/**
681	* @}
682	*/
683
684	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
685	* @brief Force or release APB1 peripheral reset.
686	* @{
687	*/
688	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
689	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
690	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
691	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
692	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
693	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
694	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
695	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
696
697	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
698	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
699	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
700	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
701	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
702	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
703	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
704	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
705	/**
706	* @}
707	*/
708
709	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
710	* @brief Force or release APB2 peripheral reset.
711	* @{
712	*/
713	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
714	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
715	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
716	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
717	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
718	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
719	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
720	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
721	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
722
723	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
724	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
725	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
726	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
727	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
728	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
729	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
730	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
731	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
732	/**
733	* @}
734	*/
735
736	/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
737	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
738	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
739	* power consumption.
740	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
741	* @note By default, all peripheral clocks are enabled during SLEEP mode.
742	* @{
743	*/
744	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
745	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
746	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
747	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
748	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
749	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
750
751	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
752	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
753	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
754	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
755	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
756	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
757	/**
758	* @}
759	*/
760
761	/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
762	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
763	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
764	* power consumption.
765	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
766	* @note By default, all peripheral clocks are enabled during SLEEP mode.
767	* @{
768	*/
769	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
770	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
771	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
772	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
773	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
774	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
775	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
776
777	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
778	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
779	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
780	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
781	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
782	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
783	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
784	/**
785	* @}
786	*/
787
788	/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
789	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
790	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
791	* power consumption.
792	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
793	* @note By default, all peripheral clocks are enabled during SLEEP mode.
794	* @{
795	*/
796	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
797	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
798	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
799	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
800	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
801	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
802	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
803	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
804
805	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
806	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
807	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
808	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
809	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
810	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
811	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
812	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
813	/**
814	* @}
815	*/
816
817	/** @defgroup RCC_HSI_Configuration HSI Configuration
818	* @{
819	*/
820
821	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
822	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
823	* It is used (enabled by hardware) as system clock source after startup
824	* from Reset, wake-up from STOP and STANDBY mode, or in case of failure
825	* of the HSE used directly or indirectly as system clock (if the Clock
826	* Security System CSS is enabled).
827	* @note HSI can not be stopped if it is used as system clock source. In this case,
828	* you have to select another source of the system clock then stop the HSI.
829	* @note After enabling the HSI, the application software should wait on HSIRDY
830	* flag to be set indicating that HSI clock is stable and can be used as
831	* system clock source.
832	* This parameter can be: ENABLE or DISABLE.
833	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
834	* clock cycles.
835	*/
836	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
837	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
838
839	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
840	* @note The calibration is used to compensate for the variations in voltage
841	* and temperature that influence the frequency of the internal HSI RC.
842	* @param __HSICalibrationValue__ specifies the calibration trimming value.
843	* (default is RCC_HSICALIBRATION_DEFAULT).
844	* This parameter must be a number between 0 and 0x1F.
845	*/
846	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
847	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
848	/**
849	* @}
850	*/
851
852	/** @defgroup RCC_LSI_Configuration LSI Configuration
853	* @{
854	*/
855
856	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
857	* @note After enabling the LSI, the application software should wait on
858	* LSIRDY flag to be set indicating that LSI clock is stable and can
859	* be used to clock the IWDG and/or the RTC.
860	* @note LSI can not be disabled if the IWDG is running.
861	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
862	* clock cycles.
863	*/
864	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
865	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
866	/**
867	* @}
868	*/
869
870	/** @defgroup RCC_HSE_Configuration HSE Configuration
871	* @{
872	*/
873
874	/**
875	* @brief Macro to configure the External High Speed oscillator (HSE).
876	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
877	* User should request a transition to HSE Off first and then HSE On or HSE Bypass.
878	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
879	* software should wait on HSERDY flag to be set indicating that HSE clock
880	* is stable and can be used to clock the PLL and/or system clock.
881	* @note HSE state can not be changed if it is used directly or through the
882	* PLL as system clock. In this case, you have to select another source
883	* of the system clock then change the HSE state (ex. disable it).
884	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
885	* @note This function reset the CSSON bit, so if the clock security system(CSS)
886	* was previously enabled you have to enable it again after calling this
887	* function.
888	* @param __STATE__ specifies the new state of the HSE.
889	* This parameter can be one of the following values:
890	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
891	* 6 HSE oscillator clock cycles.
892	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
893	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
894	*/
895	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
896	do { \
897	if ((__STATE__) == RCC_HSE_ON) \
898	{ \
899	SET_BIT(RCC->CR, RCC_CR_HSEON); \
900	} \
901	else if ((__STATE__) == RCC_HSE_BYPASS) \
902	{ \
903	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
904	SET_BIT(RCC->CR, RCC_CR_HSEON); \
905	} \
906	else \
907	{ \
908	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
909	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
910	} \
911	} while(0U)
912	/**
913	* @}
914	*/
915
916	/** @defgroup RCC_LSE_Configuration LSE Configuration
917	* @{
918	*/
919
920	/**
921	* @brief Macro to configure the External Low Speed oscillator (LSE).
922	* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
923	* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
924	* @note As the LSE is in the Backup domain and write access is denied to
925	* this domain after reset, you have to enable write access using
926	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
927	* (to be done once after reset).
928	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
929	* software should wait on LSERDY flag to be set indicating that LSE clock
930	* is stable and can be used to clock the RTC.
931	* @param __STATE__ specifies the new state of the LSE.
932	* This parameter can be one of the following values:
933	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
934	* 6 LSE oscillator clock cycles.
935	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
936	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
937	*/
938	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
939	do { \
940	if((__STATE__) == RCC_LSE_ON) \
941	{ \
942	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
943	} \
944	else if((__STATE__) == RCC_LSE_BYPASS) \
945	{ \
946	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
947	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
948	} \
949	else \
950	{ \
951	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
952	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
953	} \
954	} while(0U)
955	/**
956	* @}
957	*/
958
959	/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
960	* @{
961	*/
962
963	/** @brief Macros to enable or disable the RTC clock.
964	* @note These macros must be used only after the RTC clock source was selected.
965	*/
966	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
967	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
968
969	/** @brief Macros to configure the RTC clock (RTCCLK).
970	* @note As the RTC clock configuration bits are in the Backup domain and write
971	* access is denied to this domain after reset, you have to enable write
972	* access using the Power Backup Access macro before to configure
973	* the RTC clock source (to be done once after reset).
974	* @note Once the RTC clock is configured it can't be changed unless the
975	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
976	* a Power On Reset (POR).
977	* @param __RTCCLKSource__ specifies the RTC clock source.
978	* This parameter can be one of the following values:
979	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock.
980	* @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock.
981	* @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock.
982	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
983	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
984	* work in STOP and STANDBY modes, and can be used as wake-up source.
985	* However, when the HSE clock is used as RTC clock source, the RTC
986	* cannot be used in STOP and STANDBY modes.
987	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
988	* RTC clock source).
989	*/
990	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
991	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
992
993	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
994	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFFU); \
995	} while(0U)
996
997	/** @brief Macro to get the RTC clock source.
998	* @retval The clock source can be one of the following values:
999	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
1000	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
1001	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
1002	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
1003	*/
1004	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
1005
1006	/**
1007	* @brief Get the RTC and HSE clock divider (RTCPRE).
1008	* @retval Returned value can be one of the following values:
1009	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
1010	*/
1011	#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) \| RCC_BDCR_RTCSEL)
1012
1013	/** @brief Macros to force or release the Backup domain reset.
1014	* @note This function resets the RTC peripheral (including the backup registers)
1015	* and the RTC clock source selection in RCC_CSR register.
1016	* @note The BKPSRAM is not affected by this reset.
1017	*/
1018	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
1019	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
1020	/**
1021	* @}
1022	*/
1023
1024	/** @defgroup RCC_PLL_Configuration PLL Configuration
1025	* @{
1026	*/
1027
1028	/** @brief Macros to enable or disable the main PLL.
1029	* @note After enabling the main PLL, the application software should wait on
1030	* PLLRDY flag to be set indicating that PLL clock is stable and can
1031	* be used as system clock source.
1032	* @note The main PLL can not be disabled if it is used as system clock source
1033	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
1034	*/
1035	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
1036	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
1037
1038	/** @brief Macro to configure the PLL clock source.
1039	* @note This function must be used only when the main PLL is disabled.
1040	* @param __PLLSOURCE__ specifies the PLL entry clock source.
1041	* This parameter can be one of the following values:
1042	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
1043	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
1044	*
1045	*/
1046	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
1047
1048	/** @brief Macro to configure the PLL multiplication factor.
1049	* @note This function must be used only when the main PLL is disabled.
1050	* @param __PLLM__ specifies the division factor for PLL VCO input clock
1051	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
1052	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
1053	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
1054	* of 2 MHz to limit PLL jitter.
1055	*
1056	*/
1057	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
1058	/**
1059	* @}
1060	*/
1061
1062	/** @defgroup RCC_Get_Clock_source Get Clock source
1063	* @{
1064	*/
1065	/**
1066	* @brief Macro to configure the system clock source.
1067	* @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
1068	* This parameter can be one of the following values:
1069	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
1070	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
1071	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
1072	* - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
1073	* parameter is available only for STM32F446xx devices.
1074	*/
1075	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
1076
1077	/** @brief Macro to get the clock source used as system clock.
1078	* @retval The clock source used as system clock. The returned value can be one
1079	* of the following:
1080	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
1081	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
1082	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
1083	* - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
1084	* is available only for STM32F446xx devices.
1085	*/
1086	#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
1087
1088	/** @brief Macro to get the oscillator used as PLL clock source.
1089	* @retval The oscillator used as PLL clock source. The returned value can be one
1090	* of the following:
1091	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
1092	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
1093	*/
1094	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
1095	/**
1096	* @}
1097	*/
1098
1099	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
1100	* @{
1101	*/
1102
1103	/** @brief Macro to configure the MCO1 clock.
1104	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
1105	* This parameter can be one of the following values:
1106	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
1107	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
1108	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
1109	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
1110	* @param __MCODIV__ specifies the MCO clock prescaler.
1111	* This parameter can be one of the following values:
1112	* @arg RCC_MCODIV_1: no division applied to MCOx clock
1113	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
1114	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
1115	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
1116	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
1117	*/
1118	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1119	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
1120
1121	/** @brief Macro to configure the MCO2 clock.
1122	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
1123	* This parameter can be one of the following values:
1124	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
1125	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
1126	* @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
1127	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
1128	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
1129	* @param __MCODIV__ specifies the MCO clock prescaler.
1130	* This parameter can be one of the following values:
1131	* @arg RCC_MCODIV_1: no division applied to MCOx clock
1132	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
1133	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
1134	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
1135	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
1136	* @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
1137	* at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
1138	*/
1139	#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1140	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) \| ((__MCODIV__) << 3U)));
1141	/**
1142	* @}
1143	*/
1144
1145	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
1146	* @brief macros to manage the specified RCC Flags and interrupts.
1147	* @{
1148	*/
1149
1150	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
1151	* the selected interrupts).
1152	* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
1153	* This parameter can be any combination of the following values:
1154	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
1155	* @arg RCC_IT_LSERDY: LSE ready interrupt.
1156	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
1157	* @arg RCC_IT_HSERDY: HSE ready interrupt.
1158	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1159	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1160	*/
1161	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
1162
1163	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
1164	* the selected interrupts).
1165	* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
1166	* This parameter can be any combination of the following values:
1167	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
1168	* @arg RCC_IT_LSERDY: LSE ready interrupt.
1169	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
1170	* @arg RCC_IT_HSERDY: HSE ready interrupt.
1171	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1172	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1173	*/
1174	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1175
1176	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
1177	* bits to clear the selected interrupt pending bits.
1178	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
1179	* This parameter can be any combination of the following values:
1180	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
1181	* @arg RCC_IT_LSERDY: LSE ready interrupt.
1182	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
1183	* @arg RCC_IT_HSERDY: HSE ready interrupt.
1184	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1185	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1186	* @arg RCC_IT_CSS: Clock Security System interrupt
1187	*/
1188	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1189
1190	/** @brief Check the RCC's interrupt has occurred or not.
1191	* @param __INTERRUPT__ specifies the RCC interrupt source to check.
1192	* This parameter can be one of the following values:
1193	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
1194	* @arg RCC_IT_LSERDY: LSE ready interrupt.
1195	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
1196	* @arg RCC_IT_HSERDY: HSE ready interrupt.
1197	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1198	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1199	* @arg RCC_IT_CSS: Clock Security System interrupt
1200	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1201	*/
1202	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1203
1204	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
1205	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
1206	*/
1207	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
1208
1209	/** @brief Check RCC flag is set or not.
1210	* @param __FLAG__ specifies the flag to check.
1211	* This parameter can be one of the following values:
1212	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
1213	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
1214	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
1215	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
1216	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
1217	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
1218	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
1219	* @arg RCC_FLAG_PINRST: Pin reset.
1220	* @arg RCC_FLAG_PORRST: POR/PDR reset.
1221	* @arg RCC_FLAG_SFTRST: Software reset.
1222	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
1223	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
1224	* @arg RCC_FLAG_LPWRRST: Low Power reset.
1225	* @retval The new state of __FLAG__ (TRUE or FALSE).
1226	*/
1227	#define RCC_FLAG_MASK ((uint8_t)0x1FU)
1228	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
1229
1230	/**
1231	* @}
1232	*/
1233
1234	/**
1235	* @}
1236	*/
1237
1238	/* Exported functions --------------------------------------------------------*/
1239	/** @addtogroup RCC_Exported_Functions
1240	* @{
1241	*/
1242
1243	/** @addtogroup RCC_Exported_Functions_Group1
1244	* @{
1245	*/
1246	/* Initialization and de-initialization functions ******************************/
1247	HAL_StatusTypeDef HAL_RCC_DeInit(void);
1248	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1249	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1250	/**
1251	* @}
1252	*/
1253
1254	/** @addtogroup RCC_Exported_Functions_Group2
1255	* @{
1256	*/
1257	/* Peripheral Control functions ************************************************/
1258	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1259	void HAL_RCC_EnableCSS(void);
1260	void HAL_RCC_DisableCSS(void);
1261	uint32_t HAL_RCC_GetSysClockFreq(void);
1262	uint32_t HAL_RCC_GetHCLKFreq(void);
1263	uint32_t HAL_RCC_GetPCLK1Freq(void);
1264	uint32_t HAL_RCC_GetPCLK2Freq(void);
1265	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1266	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
1267
1268	/* CSS NMI IRQ handler */
1269	void HAL_RCC_NMI_IRQHandler(void);
1270
1271	/* User Callbacks in non blocking mode (IT mode) */
1272	void HAL_RCC_CSSCallback(void);
1273
1274	/**
1275	* @}
1276	*/
1277
1278	/**
1279	* @}
1280	*/
1281
1282	/* Private types -------------------------------------------------------------*/
1283	/* Private variables ---------------------------------------------------------*/
1284	/* Private constants ---------------------------------------------------------*/
1285	/** @defgroup RCC_Private_Constants RCC Private Constants
1286	* @{
1287	*/
1288
1289	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
1290	* @brief RCC registers bit address in the alias region
1291	* @{
1292	*/
1293	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
1294	/* --- CR Register --- */
1295	/* Alias word address of HSION bit */
1296	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
1297	#define RCC_HSION_BIT_NUMBER 0x00U
1298	#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
1299	/* Alias word address of CSSON bit */
1300	#define RCC_CSSON_BIT_NUMBER 0x13U
1301	#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
1302	/* Alias word address of PLLON bit */
1303	#define RCC_PLLON_BIT_NUMBER 0x18U
1304	#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
1305
1306	/* --- BDCR Register --- */
1307	/* Alias word address of RTCEN bit */
1308	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
1309	#define RCC_RTCEN_BIT_NUMBER 0x0FU
1310	#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
1311	/* Alias word address of BDRST bit */
1312	#define RCC_BDRST_BIT_NUMBER 0x10U
1313	#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
1314
1315	/* --- CSR Register --- */
1316	/* Alias word address of LSION bit */
1317	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
1318	#define RCC_LSION_BIT_NUMBER 0x00U
1319	#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
1320
1321	/* CR register byte 3 (Bits[23:16]) base address */
1322	#define RCC_CR_BYTE2_ADDRESS 0x40023802U
1323
1324	/* CIR register byte 2 (Bits[15:8]) base address */
1325	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
1326
1327	/* CIR register byte 3 (Bits[23:16]) base address */
1328	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
1329
1330	/* BDCR register base address */
1331	#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
1332
1333	#define RCC_DBP_TIMEOUT_VALUE 2U
1334	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1335
1336	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1337	#define HSI_TIMEOUT_VALUE 2U /* 2 ms */
1338	#define LSI_TIMEOUT_VALUE 2U /* 2 ms */
1339	#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
1340
1341	/**
1342	* @}
1343	*/
1344
1345	/**
1346	* @}
1347	*/
1348
1349	/* Private macros ------------------------------------------------------------*/
1350	/** @defgroup RCC_Private_Macros RCC Private Macros
1351	* @{
1352	*/
1353
1354	/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
1355	* @{
1356	*/
1357	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
1358
1359	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
1360	((HSE) == RCC_HSE_BYPASS))
1361
1362	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
1363	((LSE) == RCC_LSE_BYPASS))
1364
1365	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
1366
1367	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
1368
1369	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
1370
1371	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
1372	((SOURCE) == RCC_PLLSOURCE_HSE))
1373
1374	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
1375	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
1376	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
1377	((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
1378
1379	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
1380	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
1381	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
1382	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) \|\| \
1383	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
1384	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) \|\| \
1385	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) \|\| \
1386	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) \|\| \
1387	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
1388	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) \|\| \
1389	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) \|\| \
1390	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) \|\| \
1391	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) \|\| \
1392	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) \|\| \
1393	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) \|\| \
1394	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) \|\| \
1395	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) \|\| \
1396	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) \|\| \
1397	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) \|\| \
1398	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) \|\| \
1399	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) \|\| \
1400	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) \|\| \
1401	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) \|\| \
1402	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) \|\| \
1403	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) \|\| \
1404	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) \|\| \
1405	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) \|\| \
1406	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) \|\| \
1407	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) \|\| \
1408	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) \|\| \
1409	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) \|\| \
1410	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
1411
1412	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
1413
1414	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) \|\| ((VALUE) == 4U) \|\| ((VALUE) == 6U) \|\| ((VALUE) == 8U))
1415
1416	#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
1417
1418	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
1419	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
1420	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
1421	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
1422	((HCLK) == RCC_SYSCLK_DIV512))
1423
1424	#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
1425
1426	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
1427	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
1428	((PCLK) == RCC_HCLK_DIV16))
1429
1430	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
1431
1432	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
1433	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
1434
1435	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
1436	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
1437	((DIV) == RCC_MCODIV_5))
1438	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
1439
1440	/**
1441	* @}
1442	*/
1443
1444	/**
1445	* @}
1446	*/
1447
1448	/**
1449	* @}
1450	*/
1451
1452	/**
1453	* @}
1454	*/
1455
1456	#ifdef __cplusplus
1457	}
1458	#endif
1459
1460	#endif /* __STM32F4xx_HAL_RCC_H */
1461
1462	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h

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