source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h

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1/**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef STM32F4xx_LL_DAC_H
22#define STM32F4xx_LL_DAC_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f4xx.h"
30
31/** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35#if defined(DAC)
36
37/** @defgroup DAC_LL DAC
38 * @{
39 */
40
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43
44/* Private constants ---------------------------------------------------------*/
45/** @defgroup DAC_LL_Private_Constants DAC Private Constants
46 * @{
47 */
48
49/* Internal masks for DAC channels definition */
50/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
51/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
52/* - channel bits position into register SWTRIG */
53/* - channel register offset of data holding register DHRx */
54/* - channel register offset of data output register DORx */
55#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
56 CR, MCR, CCR, SHHR, SHRR of channel 1 */
57#if defined(DAC_CHANNEL2_SUPPORT)
58#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
59 CR, MCR, CCR, SHHR, SHRR of channel 2 */
60#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
61#else
62#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET)
63#endif /* DAC_CHANNEL2_SUPPORT */
64
65#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
66#if defined(DAC_CHANNEL2_SUPPORT)
67#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
68#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
69#else
70#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
71#endif /* DAC_CHANNEL2_SUPPORT */
72
73#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
74#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
75 DHR12Rx channel 1 (shifted left of 20 bits) */
76#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
77 DHR12Rx channel 1 (shifted left of 24 bits) */
78#if defined(DAC_CHANNEL2_SUPPORT)
79#define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
80 DHR12Rx channel 1 (shifted left of 16 bits) */
81#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
82 DHR12Rx channel 1 (shifted left of 20 bits) */
83#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
84 DHR12Rx channel 1 (shifted left of 24 bits) */
85#endif /* DAC_CHANNEL2_SUPPORT */
86#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
87#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
88#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
89#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
90 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
91
92#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
93#if defined(DAC_CHANNEL2_SUPPORT)
94#define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
95 DORx channel 2 (shifted left of 28 bits) */
96#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
97#endif /* DAC_CHANNEL2_SUPPORT */
98
99
100#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
101 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
102#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
103 to position 0 */
104#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
105 to position 0 */
106
107#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
108 channel 1 or 2 versus DHR12Rx channel 1
109 (shifted left of 16 bits) */
110#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
111 channel 1 or 2 versus DHR12Rx channel 1
112 (shifted left of 20 bits) */
113#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
114 channel 1 or 2 versus DHR12Rx channel 1
115 (shifted left of 24 bits) */
116#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
117 channel 1 or 2 versus DORx channel 1
118 (shifted left of 28 bits) */
119
120/* DAC registers bits positions */
121#if defined(DAC_CHANNEL2_SUPPORT)
122#endif
123#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
124#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
125#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
126
127/* Miscellaneous data */
128#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
129 bits (voltage range determined by analog voltage
130 references Vref+ and Vref-, refer to reference manual) */
131
132/**
133 * @}
134 */
135
136
137/* Private macros ------------------------------------------------------------*/
138/** @defgroup DAC_LL_Private_Macros DAC Private Macros
139 * @{
140 */
141
142/**
143 * @brief Driver macro reserved for internal use: set a pointer to
144 * a register from a register basis from which an offset
145 * is applied.
146 * @param __REG__ Register basis from which the offset is applied.
147 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
148 * @retval Pointer to register address
149 */
150#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
151 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
152
153/**
154 * @}
155 */
156
157
158/* Exported types ------------------------------------------------------------*/
159#if defined(USE_FULL_LL_DRIVER)
160/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
161 * @{
162 */
163
164/**
165 * @brief Structure definition of some features of DAC instance.
166 */
167typedef struct
168{
169 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
170 internal (SW start) or from external peripheral
171 (timer event, external interrupt line).
172 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
173
174 This feature can be modified afterwards using unitary
175 function @ref LL_DAC_SetTriggerSource(). */
176
177 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
178 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
179
180 This feature can be modified afterwards using unitary
181 function @ref LL_DAC_SetWaveAutoGeneration(). */
182
183 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
184 If waveform automatic generation mode is set to noise, this parameter
185 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
186 If waveform automatic generation mode is set to triangle,
187 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
188 @note If waveform automatic generation mode is disabled,
189 this parameter is discarded.
190
191 This feature can be modified afterwards using unitary
192 function @ref LL_DAC_SetWaveNoiseLFSR(),
193 @ref LL_DAC_SetWaveTriangleAmplitude()
194 depending on the wave automatic generation selected. */
195
196 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
197 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
198
199 This feature can be modified afterwards using unitary
200 function @ref LL_DAC_SetOutputBuffer(). */
201} LL_DAC_InitTypeDef;
202
203/**
204 * @}
205 */
206#endif /* USE_FULL_LL_DRIVER */
207
208/* Exported constants --------------------------------------------------------*/
209/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
210 * @{
211 */
212
213/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
214 * @brief Flags defines which can be used with LL_DAC_ReadReg function
215 * @{
216 */
217/* DAC channel 1 flags */
218#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
219#if defined(DAC_CHANNEL2_SUPPORT)
220/* DAC channel 2 flags */
221#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
222#endif /* DAC_CHANNEL2_SUPPORT */
223/**
224 * @}
225 */
226
227/** @defgroup DAC_LL_EC_IT DAC interruptions
228 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
229 * @{
230 */
231#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
232#if defined(DAC_CHANNEL2_SUPPORT)
233#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
234#endif /* DAC_CHANNEL2_SUPPORT */
235/**
236 * @}
237 */
238
239/** @defgroup DAC_LL_EC_CHANNEL DAC channels
240 * @{
241 */
242#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
243#if defined(DAC_CHANNEL2_SUPPORT)
244#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
245#endif /* DAC_CHANNEL2_SUPPORT */
246/**
247 * @}
248 */
249
250/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
251 * @{
252 */
253#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
254#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
255#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
256#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
257#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
258#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
259#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
260#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
261/**
262 * @}
263 */
264
265/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
266 * @{
267 */
268#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
269#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
270#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
271/**
272 * @}
273 */
274
275/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
276 * @{
277 */
278#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
279#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
280#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
281#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
282#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
283#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
284#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
285#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
286#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
287#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
288#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
289#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
290/**
291 * @}
292 */
293
294/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
295 * @{
296 */
297#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
298#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
299#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
300#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
301#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
302#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
303#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
304#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
305#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
306#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
307#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
308#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
309/**
310 * @}
311 */
312
313/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
314 * @{
315 */
316#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
317#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
318/**
319 * @}
320 */
321
322/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
323 * @{
324 */
325#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
326#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
327/**
328 * @}
329 */
330
331/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
332 * @{
333 */
334/* List of DAC registers intended to be used (most commonly) with */
335/* DMA transfer. */
336/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
337#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
338#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
339#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
340/**
341 * @}
342 */
343
344/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
345 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
346 * not timeout values.
347 * For details on delays values, refer to descriptions in source code
348 * above each literal definition.
349 * @{
350 */
351
352/* Delay for DAC channel voltage settling time from DAC channel startup */
353/* (transition from disable to enable). */
354/* Note: DAC channel startup time depends on board application environment: */
355/* impedance connected to DAC channel output. */
356/* The delay below is specified under conditions: */
357/* - voltage maximum transition (lowest to highest value) */
358/* - until voltage reaches final value +-1LSB */
359/* - DAC channel output buffer enabled */
360/* - load impedance of 5kOhm (min), 50pF (max) */
361/* Literal set to maximum value (refer to device datasheet, */
362/* parameter "tWAKEUP"). */
363/* Unit: us */
364#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
365
366/* Delay for DAC channel voltage settling time. */
367/* Note: DAC channel startup time depends on board application environment: */
368/* impedance connected to DAC channel output. */
369/* The delay below is specified under conditions: */
370/* - voltage maximum transition (lowest to highest value) */
371/* - until voltage reaches final value +-1LSB */
372/* - DAC channel output buffer enabled */
373/* - load impedance of 5kOhm min, 50pF max */
374/* Literal set to maximum value (refer to device datasheet, */
375/* parameter "tSETTLING"). */
376/* Unit: us */
377#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
378
379/**
380 * @}
381 */
382
383/**
384 * @}
385 */
386
387/* Exported macro ------------------------------------------------------------*/
388/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
389 * @{
390 */
391
392/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
393 * @{
394 */
395
396/**
397 * @brief Write a value in DAC register
398 * @param __INSTANCE__ DAC Instance
399 * @param __REG__ Register to be written
400 * @param __VALUE__ Value to be written in the register
401 * @retval None
402 */
403#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
404
405/**
406 * @brief Read a value in DAC register
407 * @param __INSTANCE__ DAC Instance
408 * @param __REG__ Register to be read
409 * @retval Register value
410 */
411#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
412
413/**
414 * @}
415 */
416
417/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
418 * @{
419 */
420
421/**
422 * @brief Helper macro to get DAC channel number in decimal format
423 * from literals LL_DAC_CHANNEL_x.
424 * Example:
425 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
426 * will return decimal number "1".
427 * @note The input can be a value from functions where a channel
428 * number is returned.
429 * @param __CHANNEL__ This parameter can be one of the following values:
430 * @arg @ref LL_DAC_CHANNEL_1
431 * @arg @ref LL_DAC_CHANNEL_2 (1)
432 *
433 * (1) On this STM32 serie, parameter not available on all devices.
434 * Refer to device datasheet for channels availability.
435 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
436 */
437#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
438 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
439
440/**
441 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
442 * from number in decimal format.
443 * Example:
444 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
445 * will return a data equivalent to "LL_DAC_CHANNEL_1".
446 * @note If the input parameter does not correspond to a DAC channel,
447 * this macro returns value '0'.
448 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
449 * @retval Returned value can be one of the following values:
450 * @arg @ref LL_DAC_CHANNEL_1
451 * @arg @ref LL_DAC_CHANNEL_2 (1)
452 *
453 * (1) On this STM32 serie, parameter not available on all devices.
454 * Refer to device datasheet for channels availability.
455 */
456#if defined(DAC_CHANNEL2_SUPPORT)
457#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
458 (((__DECIMAL_NB__) == 1UL) \
459 ? ( \
460 LL_DAC_CHANNEL_1 \
461 ) \
462 : \
463 (((__DECIMAL_NB__) == 2UL) \
464 ? ( \
465 LL_DAC_CHANNEL_2 \
466 ) \
467 : \
468 ( \
469 0UL \
470 ) \
471 ) \
472 )
473#else
474#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
475 (((__DECIMAL_NB__) == 1UL) \
476 ? ( \
477 LL_DAC_CHANNEL_1 \
478 ) \
479 : \
480 ( \
481 0UL \
482 ) \
483 )
484#endif /* DAC_CHANNEL2_SUPPORT */
485
486/**
487 * @brief Helper macro to define the DAC conversion data full-scale digital
488 * value corresponding to the selected DAC resolution.
489 * @note DAC conversion data full-scale corresponds to voltage range
490 * determined by analog voltage references Vref+ and Vref-
491 * (refer to reference manual).
492 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
493 * @arg @ref LL_DAC_RESOLUTION_12B
494 * @arg @ref LL_DAC_RESOLUTION_8B
495 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
496 */
497#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
498 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
499
500/**
501 * @brief Helper macro to calculate the DAC conversion data (unit: digital
502 * value) corresponding to a voltage (unit: mVolt).
503 * @note This helper macro is intended to provide input data in voltage
504 * rather than digital value,
505 * to be used with LL DAC functions such as
506 * @ref LL_DAC_ConvertData12RightAligned().
507 * @note Analog reference voltage (Vref+) must be either known from
508 * user board environment or can be calculated using ADC measurement
509 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
510 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
511 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
512 * (unit: mVolt).
513 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
514 * @arg @ref LL_DAC_RESOLUTION_12B
515 * @arg @ref LL_DAC_RESOLUTION_8B
516 * @retval DAC conversion data (unit: digital value)
517 */
518#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
519 __DAC_VOLTAGE__,\
520 __DAC_RESOLUTION__) \
521((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
522 / (__VREFANALOG_VOLTAGE__) \
523)
524
525/**
526 * @}
527 */
528
529/**
530 * @}
531 */
532
533
534/* Exported functions --------------------------------------------------------*/
535/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
536 * @{
537 */
538/**
539 * @brief Set the conversion trigger source for the selected DAC channel.
540 * @note For conversion trigger source to be effective, DAC trigger
541 * must be enabled using function @ref LL_DAC_EnableTrigger().
542 * @note To set conversion trigger source, DAC channel must be disabled.
543 * Otherwise, the setting is discarded.
544 * @note Availability of parameters of trigger sources from timer
545 * depends on timers availability on the selected device.
546 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
547 * CR TSEL2 LL_DAC_SetTriggerSource
548 * @param DACx DAC instance
549 * @param DAC_Channel This parameter can be one of the following values:
550 * @arg @ref LL_DAC_CHANNEL_1
551 * @arg @ref LL_DAC_CHANNEL_2 (1)
552 *
553 * (1) On this STM32 serie, parameter not available on all devices.
554 * Refer to device datasheet for channels availability.
555 * @param TriggerSource This parameter can be one of the following values:
556 * @arg @ref LL_DAC_TRIG_SOFTWARE
557 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
558 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
559 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
560 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
561 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
562 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
563 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
564 * @retval None
565 */
566__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
567{
568 MODIFY_REG(DACx->CR,
569 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
570 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
571}
572
573/**
574 * @brief Get the conversion trigger source for the selected DAC channel.
575 * @note For conversion trigger source to be effective, DAC trigger
576 * must be enabled using function @ref LL_DAC_EnableTrigger().
577 * @note Availability of parameters of trigger sources from timer
578 * depends on timers availability on the selected device.
579 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
580 * CR TSEL2 LL_DAC_GetTriggerSource
581 * @param DACx DAC instance
582 * @param DAC_Channel This parameter can be one of the following values:
583 * @arg @ref LL_DAC_CHANNEL_1
584 * @arg @ref LL_DAC_CHANNEL_2 (1)
585 *
586 * (1) On this STM32 serie, parameter not available on all devices.
587 * Refer to device datasheet for channels availability.
588 * @retval Returned value can be one of the following values:
589 * @arg @ref LL_DAC_TRIG_SOFTWARE
590 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
591 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
592 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
593 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
594 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
595 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
596 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
597 */
598__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
599{
600 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
601 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
602 );
603}
604
605/**
606 * @brief Set the waveform automatic generation mode
607 * for the selected DAC channel.
608 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
609 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
610 * @param DACx DAC instance
611 * @param DAC_Channel This parameter can be one of the following values:
612 * @arg @ref LL_DAC_CHANNEL_1
613 * @arg @ref LL_DAC_CHANNEL_2 (1)
614 *
615 * (1) On this STM32 serie, parameter not available on all devices.
616 * Refer to device datasheet for channels availability.
617 * @param WaveAutoGeneration This parameter can be one of the following values:
618 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
619 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
620 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
621 * @retval None
622 */
623__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
624{
625 MODIFY_REG(DACx->CR,
626 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
627 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
628}
629
630/**
631 * @brief Get the waveform automatic generation mode
632 * for the selected DAC channel.
633 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
634 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
635 * @param DACx DAC instance
636 * @param DAC_Channel This parameter can be one of the following values:
637 * @arg @ref LL_DAC_CHANNEL_1
638 * @arg @ref LL_DAC_CHANNEL_2 (1)
639 *
640 * (1) On this STM32 serie, parameter not available on all devices.
641 * Refer to device datasheet for channels availability.
642 * @retval Returned value can be one of the following values:
643 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
644 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
645 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
646 */
647__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
648{
649 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
650 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
651 );
652}
653
654/**
655 * @brief Set the noise waveform generation for the selected DAC channel:
656 * Noise mode and parameters LFSR (linear feedback shift register).
657 * @note For wave generation to be effective, DAC channel
658 * wave generation mode must be enabled using
659 * function @ref LL_DAC_SetWaveAutoGeneration().
660 * @note This setting can be set when the selected DAC channel is disabled
661 * (otherwise, the setting operation is ignored).
662 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
663 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
664 * @param DACx DAC instance
665 * @param DAC_Channel This parameter can be one of the following values:
666 * @arg @ref LL_DAC_CHANNEL_1
667 * @arg @ref LL_DAC_CHANNEL_2 (1)
668 *
669 * (1) On this STM32 serie, parameter not available on all devices.
670 * Refer to device datasheet for channels availability.
671 * @param NoiseLFSRMask This parameter can be one of the following values:
672 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
673 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
674 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
675 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
676 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
677 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
678 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
679 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
680 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
681 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
682 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
683 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
684 * @retval None
685 */
686__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
687{
688 MODIFY_REG(DACx->CR,
689 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
690 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
691}
692
693/**
694 * @brief Get the noise waveform generation for the selected DAC channel:
695 * Noise mode and parameters LFSR (linear feedback shift register).
696 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
697 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
698 * @param DACx DAC instance
699 * @param DAC_Channel This parameter can be one of the following values:
700 * @arg @ref LL_DAC_CHANNEL_1
701 * @arg @ref LL_DAC_CHANNEL_2 (1)
702 *
703 * (1) On this STM32 serie, parameter not available on all devices.
704 * Refer to device datasheet for channels availability.
705 * @retval Returned value can be one of the following values:
706 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
707 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
708 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
709 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
710 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
711 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
712 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
713 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
714 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
715 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
716 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
717 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
718 */
719__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
720{
721 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
722 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
723 );
724}
725
726/**
727 * @brief Set the triangle waveform generation for the selected DAC channel:
728 * triangle mode and amplitude.
729 * @note For wave generation to be effective, DAC channel
730 * wave generation mode must be enabled using
731 * function @ref LL_DAC_SetWaveAutoGeneration().
732 * @note This setting can be set when the selected DAC channel is disabled
733 * (otherwise, the setting operation is ignored).
734 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
735 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
736 * @param DACx DAC instance
737 * @param DAC_Channel This parameter can be one of the following values:
738 * @arg @ref LL_DAC_CHANNEL_1
739 * @arg @ref LL_DAC_CHANNEL_2 (1)
740 *
741 * (1) On this STM32 serie, parameter not available on all devices.
742 * Refer to device datasheet for channels availability.
743 * @param TriangleAmplitude This parameter can be one of the following values:
744 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
745 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
746 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
747 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
748 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
749 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
750 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
751 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
752 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
753 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
754 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
755 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
756 * @retval None
757 */
758__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
759 uint32_t TriangleAmplitude)
760{
761 MODIFY_REG(DACx->CR,
762 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
763 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
764}
765
766/**
767 * @brief Get the triangle waveform generation for the selected DAC channel:
768 * triangle mode and amplitude.
769 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
770 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
771 * @param DACx DAC instance
772 * @param DAC_Channel This parameter can be one of the following values:
773 * @arg @ref LL_DAC_CHANNEL_1
774 * @arg @ref LL_DAC_CHANNEL_2 (1)
775 *
776 * (1) On this STM32 serie, parameter not available on all devices.
777 * Refer to device datasheet for channels availability.
778 * @retval Returned value can be one of the following values:
779 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
780 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
781 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
782 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
783 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
784 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
785 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
786 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
787 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
788 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
789 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
790 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
791 */
792__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
793{
794 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
795 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
796 );
797}
798
799/**
800 * @brief Set the output buffer for the selected DAC channel.
801 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
802 * CR BOFF2 LL_DAC_SetOutputBuffer
803 * @param DACx DAC instance
804 * @param DAC_Channel This parameter can be one of the following values:
805 * @arg @ref LL_DAC_CHANNEL_1
806 * @arg @ref LL_DAC_CHANNEL_2 (1)
807 *
808 * (1) On this STM32 serie, parameter not available on all devices.
809 * Refer to device datasheet for channels availability.
810 * @param OutputBuffer This parameter can be one of the following values:
811 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
812 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
813 * @retval None
814 */
815__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
816{
817 MODIFY_REG(DACx->CR,
818 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
819 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
820}
821
822/**
823 * @brief Get the output buffer state for the selected DAC channel.
824 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
825 * CR BOFF2 LL_DAC_GetOutputBuffer
826 * @param DACx DAC instance
827 * @param DAC_Channel This parameter can be one of the following values:
828 * @arg @ref LL_DAC_CHANNEL_1
829 * @arg @ref LL_DAC_CHANNEL_2 (1)
830 *
831 * (1) On this STM32 serie, parameter not available on all devices.
832 * Refer to device datasheet for channels availability.
833 * @retval Returned value can be one of the following values:
834 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
835 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
836 */
837__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
838{
839 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
840 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
841 );
842}
843
844/**
845 * @}
846 */
847
848/** @defgroup DAC_LL_EF_DMA_Management DMA Management
849 * @{
850 */
851
852/**
853 * @brief Enable DAC DMA transfer request of the selected channel.
854 * @note To configure DMA source address (peripheral address),
855 * use function @ref LL_DAC_DMA_GetRegAddr().
856 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
857 * CR DMAEN2 LL_DAC_EnableDMAReq
858 * @param DACx DAC instance
859 * @param DAC_Channel This parameter can be one of the following values:
860 * @arg @ref LL_DAC_CHANNEL_1
861 * @arg @ref LL_DAC_CHANNEL_2 (1)
862 *
863 * (1) On this STM32 serie, parameter not available on all devices.
864 * Refer to device datasheet for channels availability.
865 * @retval None
866 */
867__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
868{
869 SET_BIT(DACx->CR,
870 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
871}
872
873/**
874 * @brief Disable DAC DMA transfer request of the selected channel.
875 * @note To configure DMA source address (peripheral address),
876 * use function @ref LL_DAC_DMA_GetRegAddr().
877 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
878 * CR DMAEN2 LL_DAC_DisableDMAReq
879 * @param DACx DAC instance
880 * @param DAC_Channel This parameter can be one of the following values:
881 * @arg @ref LL_DAC_CHANNEL_1
882 * @arg @ref LL_DAC_CHANNEL_2 (1)
883 *
884 * (1) On this STM32 serie, parameter not available on all devices.
885 * Refer to device datasheet for channels availability.
886 * @retval None
887 */
888__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
889{
890 CLEAR_BIT(DACx->CR,
891 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
892}
893
894/**
895 * @brief Get DAC DMA transfer request state of the selected channel.
896 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
897 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
898 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
899 * @param DACx DAC instance
900 * @param DAC_Channel This parameter can be one of the following values:
901 * @arg @ref LL_DAC_CHANNEL_1
902 * @arg @ref LL_DAC_CHANNEL_2 (1)
903 *
904 * (1) On this STM32 serie, parameter not available on all devices.
905 * Refer to device datasheet for channels availability.
906 * @retval State of bit (1 or 0).
907 */
908__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
909{
910 return ((READ_BIT(DACx->CR,
911 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
912 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
913}
914
915/**
916 * @brief Function to help to configure DMA transfer to DAC: retrieve the
917 * DAC register address from DAC instance and a list of DAC registers
918 * intended to be used (most commonly) with DMA transfer.
919 * @note These DAC registers are data holding registers:
920 * when DAC conversion is requested, DAC generates a DMA transfer
921 * request to have data available in DAC data holding registers.
922 * @note This macro is intended to be used with LL DMA driver, refer to
923 * function "LL_DMA_ConfigAddresses()".
924 * Example:
925 * LL_DMA_ConfigAddresses(DMA1,
926 * LL_DMA_CHANNEL_1,
927 * (uint32_t)&< array or variable >,
928 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
929 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
930 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
931 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
932 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
933 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
934 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
935 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
936 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
937 * @param DACx DAC instance
938 * @param DAC_Channel This parameter can be one of the following values:
939 * @arg @ref LL_DAC_CHANNEL_1
940 * @arg @ref LL_DAC_CHANNEL_2 (1)
941 *
942 * (1) On this STM32 serie, parameter not available on all devices.
943 * Refer to device datasheet for channels availability.
944 * @param Register This parameter can be one of the following values:
945 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
946 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
947 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
948 * @retval DAC register address
949 */
950__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
951{
952 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
953 /* DAC channel selected. */
954 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
955 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
956}
957/**
958 * @}
959 */
960
961/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
962 * @{
963 */
964
965/**
966 * @brief Enable DAC selected channel.
967 * @rmtoll CR EN1 LL_DAC_Enable\n
968 * CR EN2 LL_DAC_Enable
969 * @note After enable from off state, DAC channel requires a delay
970 * for output voltage to reach accuracy +/- 1 LSB.
971 * Refer to device datasheet, parameter "tWAKEUP".
972 * @param DACx DAC instance
973 * @param DAC_Channel This parameter can be one of the following values:
974 * @arg @ref LL_DAC_CHANNEL_1
975 * @arg @ref LL_DAC_CHANNEL_2 (1)
976 *
977 * (1) On this STM32 serie, parameter not available on all devices.
978 * Refer to device datasheet for channels availability.
979 * @retval None
980 */
981__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
982{
983 SET_BIT(DACx->CR,
984 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
985}
986
987/**
988 * @brief Disable DAC selected channel.
989 * @rmtoll CR EN1 LL_DAC_Disable\n
990 * CR EN2 LL_DAC_Disable
991 * @param DACx DAC instance
992 * @param DAC_Channel This parameter can be one of the following values:
993 * @arg @ref LL_DAC_CHANNEL_1
994 * @arg @ref LL_DAC_CHANNEL_2 (1)
995 *
996 * (1) On this STM32 serie, parameter not available on all devices.
997 * Refer to device datasheet for channels availability.
998 * @retval None
999 */
1000__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1001{
1002 CLEAR_BIT(DACx->CR,
1003 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1004}
1005
1006/**
1007 * @brief Get DAC enable state of the selected channel.
1008 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1009 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1010 * CR EN2 LL_DAC_IsEnabled
1011 * @param DACx DAC instance
1012 * @param DAC_Channel This parameter can be one of the following values:
1013 * @arg @ref LL_DAC_CHANNEL_1
1014 * @arg @ref LL_DAC_CHANNEL_2 (1)
1015 *
1016 * (1) On this STM32 serie, parameter not available on all devices.
1017 * Refer to device datasheet for channels availability.
1018 * @retval State of bit (1 or 0).
1019 */
1020__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1021{
1022 return ((READ_BIT(DACx->CR,
1023 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1024 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1025}
1026
1027/**
1028 * @brief Enable DAC trigger of the selected channel.
1029 * @note - If DAC trigger is disabled, DAC conversion is performed
1030 * automatically once the data holding register is updated,
1031 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1032 * @ref LL_DAC_ConvertData12RightAligned(), ...
1033 * - If DAC trigger is enabled, DAC conversion is performed
1034 * only when a hardware of software trigger event is occurring.
1035 * Select trigger source using
1036 * function @ref LL_DAC_SetTriggerSource().
1037 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1038 * CR TEN2 LL_DAC_EnableTrigger
1039 * @param DACx DAC instance
1040 * @param DAC_Channel This parameter can be one of the following values:
1041 * @arg @ref LL_DAC_CHANNEL_1
1042 * @arg @ref LL_DAC_CHANNEL_2 (1)
1043 *
1044 * (1) On this STM32 serie, parameter not available on all devices.
1045 * Refer to device datasheet for channels availability.
1046 * @retval None
1047 */
1048__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1049{
1050 SET_BIT(DACx->CR,
1051 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1052}
1053
1054/**
1055 * @brief Disable DAC trigger of the selected channel.
1056 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1057 * CR TEN2 LL_DAC_DisableTrigger
1058 * @param DACx DAC instance
1059 * @param DAC_Channel This parameter can be one of the following values:
1060 * @arg @ref LL_DAC_CHANNEL_1
1061 * @arg @ref LL_DAC_CHANNEL_2 (1)
1062 *
1063 * (1) On this STM32 serie, parameter not available on all devices.
1064 * Refer to device datasheet for channels availability.
1065 * @retval None
1066 */
1067__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1068{
1069 CLEAR_BIT(DACx->CR,
1070 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1071}
1072
1073/**
1074 * @brief Get DAC trigger state of the selected channel.
1075 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1076 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1077 * CR TEN2 LL_DAC_IsTriggerEnabled
1078 * @param DACx DAC instance
1079 * @param DAC_Channel This parameter can be one of the following values:
1080 * @arg @ref LL_DAC_CHANNEL_1
1081 * @arg @ref LL_DAC_CHANNEL_2 (1)
1082 *
1083 * (1) On this STM32 serie, parameter not available on all devices.
1084 * Refer to device datasheet for channels availability.
1085 * @retval State of bit (1 or 0).
1086 */
1087__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1088{
1089 return ((READ_BIT(DACx->CR,
1090 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1091 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1092}
1093
1094/**
1095 * @brief Trig DAC conversion by software for the selected DAC channel.
1096 * @note Preliminarily, DAC trigger must be set to software trigger
1097 * using function
1098 * @ref LL_DAC_Init()
1099 * @ref LL_DAC_SetTriggerSource()
1100 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1101 * and DAC trigger must be enabled using
1102 * function @ref LL_DAC_EnableTrigger().
1103 * @note For devices featuring DAC with 2 channels: this function
1104 * can perform a SW start of both DAC channels simultaneously.
1105 * Two channels can be selected as parameter.
1106 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1107 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1108 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1109 * @param DACx DAC instance
1110 * @param DAC_Channel This parameter can a combination of the following values:
1111 * @arg @ref LL_DAC_CHANNEL_1
1112 * @arg @ref LL_DAC_CHANNEL_2 (1)
1113 *
1114 * (1) On this STM32 serie, parameter not available on all devices.
1115 * Refer to device datasheet for channels availability.
1116 * @retval None
1117 */
1118__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1119{
1120 SET_BIT(DACx->SWTRIGR,
1121 (DAC_Channel & DAC_SWTR_CHX_MASK));
1122}
1123
1124/**
1125 * @brief Set the data to be loaded in the data holding register
1126 * in format 12 bits left alignment (LSB aligned on bit 0),
1127 * for the selected DAC channel.
1128 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1129 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1130 * @param DACx DAC instance
1131 * @param DAC_Channel This parameter can be one of the following values:
1132 * @arg @ref LL_DAC_CHANNEL_1
1133 * @arg @ref LL_DAC_CHANNEL_2 (1)
1134 *
1135 * (1) On this STM32 serie, parameter not available on all devices.
1136 * Refer to device datasheet for channels availability.
1137 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1138 * @retval None
1139 */
1140__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1141{
1142 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1143 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1144
1145 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1146}
1147
1148/**
1149 * @brief Set the data to be loaded in the data holding register
1150 * in format 12 bits left alignment (MSB aligned on bit 15),
1151 * for the selected DAC channel.
1152 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1153 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1154 * @param DACx DAC instance
1155 * @param DAC_Channel This parameter can be one of the following values:
1156 * @arg @ref LL_DAC_CHANNEL_1
1157 * @arg @ref LL_DAC_CHANNEL_2 (1)
1158 *
1159 * (1) On this STM32 serie, parameter not available on all devices.
1160 * Refer to device datasheet for channels availability.
1161 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1162 * @retval None
1163 */
1164__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1165{
1166 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1167 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1168
1169 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1170}
1171
1172/**
1173 * @brief Set the data to be loaded in the data holding register
1174 * in format 8 bits left alignment (LSB aligned on bit 0),
1175 * for the selected DAC channel.
1176 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1177 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1178 * @param DACx DAC instance
1179 * @param DAC_Channel This parameter can be one of the following values:
1180 * @arg @ref LL_DAC_CHANNEL_1
1181 * @arg @ref LL_DAC_CHANNEL_2 (1)
1182 *
1183 * (1) On this STM32 serie, parameter not available on all devices.
1184 * Refer to device datasheet for channels availability.
1185 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1186 * @retval None
1187 */
1188__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1189{
1190 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1191 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1192
1193 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1194}
1195
1196#if defined(DAC_CHANNEL2_SUPPORT)
1197/**
1198 * @brief Set the data to be loaded in the data holding register
1199 * in format 12 bits left alignment (LSB aligned on bit 0),
1200 * for both DAC channels.
1201 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1202 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1203 * @param DACx DAC instance
1204 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1205 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1206 * @retval None
1207 */
1208__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1209 uint32_t DataChannel2)
1210{
1211 MODIFY_REG(DACx->DHR12RD,
1212 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1213 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1214}
1215
1216/**
1217 * @brief Set the data to be loaded in the data holding register
1218 * in format 12 bits left alignment (MSB aligned on bit 15),
1219 * for both DAC channels.
1220 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1221 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1222 * @param DACx DAC instance
1223 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1224 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1225 * @retval None
1226 */
1227__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1228 uint32_t DataChannel2)
1229{
1230 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1231 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1232 /* the 4 LSB must be taken into account for the shift value. */
1233 MODIFY_REG(DACx->DHR12LD,
1234 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1235 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1236}
1237
1238/**
1239 * @brief Set the data to be loaded in the data holding register
1240 * in format 8 bits left alignment (LSB aligned on bit 0),
1241 * for both DAC channels.
1242 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1243 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1244 * @param DACx DAC instance
1245 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1246 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1247 * @retval None
1248 */
1249__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1250 uint32_t DataChannel2)
1251{
1252 MODIFY_REG(DACx->DHR8RD,
1253 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1254 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1255}
1256#endif /* DAC_CHANNEL2_SUPPORT */
1257
1258/**
1259 * @brief Retrieve output data currently generated for the selected DAC channel.
1260 * @note Whatever alignment and resolution settings
1261 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1262 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1263 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1264 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1265 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1266 * @param DACx DAC instance
1267 * @param DAC_Channel This parameter can be one of the following values:
1268 * @arg @ref LL_DAC_CHANNEL_1
1269 * @arg @ref LL_DAC_CHANNEL_2 (1)
1270 *
1271 * (1) On this STM32 serie, parameter not available on all devices.
1272 * Refer to device datasheet for channels availability.
1273 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1274 */
1275__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1276{
1277 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1278 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1279
1280 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1281}
1282
1283/**
1284 * @}
1285 */
1286
1287/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1288 * @{
1289 */
1290
1291
1292/**
1293 * @brief Get DAC underrun flag for DAC channel 1
1294 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1295 * @param DACx DAC instance
1296 * @retval State of bit (1 or 0).
1297 */
1298__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1299{
1300 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1301}
1302
1303#if defined(DAC_CHANNEL2_SUPPORT)
1304/**
1305 * @brief Get DAC underrun flag for DAC channel 2
1306 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1307 * @param DACx DAC instance
1308 * @retval State of bit (1 or 0).
1309 */
1310__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1311{
1312 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1313}
1314#endif /* DAC_CHANNEL2_SUPPORT */
1315
1316/**
1317 * @brief Clear DAC underrun flag for DAC channel 1
1318 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1319 * @param DACx DAC instance
1320 * @retval None
1321 */
1322__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1323{
1324 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1325}
1326
1327#if defined(DAC_CHANNEL2_SUPPORT)
1328/**
1329 * @brief Clear DAC underrun flag for DAC channel 2
1330 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1331 * @param DACx DAC instance
1332 * @retval None
1333 */
1334__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1335{
1336 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1337}
1338#endif /* DAC_CHANNEL2_SUPPORT */
1339
1340/**
1341 * @}
1342 */
1343
1344/** @defgroup DAC_LL_EF_IT_Management IT management
1345 * @{
1346 */
1347
1348/**
1349 * @brief Enable DMA underrun interrupt for DAC channel 1
1350 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1351 * @param DACx DAC instance
1352 * @retval None
1353 */
1354__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1355{
1356 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1357}
1358
1359#if defined(DAC_CHANNEL2_SUPPORT)
1360/**
1361 * @brief Enable DMA underrun interrupt for DAC channel 2
1362 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1363 * @param DACx DAC instance
1364 * @retval None
1365 */
1366__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1367{
1368 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1369}
1370#endif /* DAC_CHANNEL2_SUPPORT */
1371
1372/**
1373 * @brief Disable DMA underrun interrupt for DAC channel 1
1374 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1375 * @param DACx DAC instance
1376 * @retval None
1377 */
1378__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1379{
1380 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1381}
1382
1383#if defined(DAC_CHANNEL2_SUPPORT)
1384/**
1385 * @brief Disable DMA underrun interrupt for DAC channel 2
1386 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1387 * @param DACx DAC instance
1388 * @retval None
1389 */
1390__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1391{
1392 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1393}
1394#endif /* DAC_CHANNEL2_SUPPORT */
1395
1396/**
1397 * @brief Get DMA underrun interrupt for DAC channel 1
1398 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1399 * @param DACx DAC instance
1400 * @retval State of bit (1 or 0).
1401 */
1402__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1403{
1404 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1405}
1406
1407#if defined(DAC_CHANNEL2_SUPPORT)
1408/**
1409 * @brief Get DMA underrun interrupt for DAC channel 2
1410 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1411 * @param DACx DAC instance
1412 * @retval State of bit (1 or 0).
1413 */
1414__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1415{
1416 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1417}
1418#endif /* DAC_CHANNEL2_SUPPORT */
1419
1420/**
1421 * @}
1422 */
1423
1424#if defined(USE_FULL_LL_DRIVER)
1425/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1426 * @{
1427 */
1428
1429ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1430ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
1431void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1432
1433/**
1434 * @}
1435 */
1436#endif /* USE_FULL_LL_DRIVER */
1437
1438/**
1439 * @}
1440 */
1441
1442/**
1443 * @}
1444 */
1445
1446#endif /* DAC */
1447
1448/**
1449 * @}
1450 */
1451
1452#ifdef __cplusplus
1453}
1454#endif
1455
1456#endif /* STM32F4xx_LL_DAC_H */
1457
1458/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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