source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h

Last change on this file was 1, checked in by AlexLir, 4 years ago
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef __STM32F4xx_LL_DMA_H
22#define __STM32F4xx_LL_DMA_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f4xx.h"
30
31/** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35#if defined (DMA1) || defined (DMA2)
36
37/** @defgroup DMA_LL DMA
38 * @{
39 */
40
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43/** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
47static const uint8_t STREAM_OFFSET_TAB[] =
48{
49 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
56 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
57};
58
59/**
60 * @}
61 */
62
63/* Private constants ---------------------------------------------------------*/
64/** @defgroup DMA_LL_Private_Constants DMA Private Constants
65 * @{
66 */
67/**
68 * @}
69 */
70
71
72/* Private macros ------------------------------------------------------------*/
73/* Exported types ------------------------------------------------------------*/
74#if defined(USE_FULL_LL_DRIVER)
75/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
76 * @{
77 */
78typedef struct
79{
80 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
81 or as Source base address in case of memory to memory transfer direction.
82
83 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
84
85 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
86 or as Destination base address in case of memory to memory transfer direction.
87
88 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
89
90 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
91 from memory to memory or from peripheral to memory.
92 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
93
94 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
95
96 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
97 This parameter can be a value of @ref DMA_LL_EC_MODE
98 @note The circular buffer mode cannot be used if the memory to memory
99 data transfer direction is configured on the selected Stream
100
101 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
102
103 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
104 is incremented or not.
105 This parameter can be a value of @ref DMA_LL_EC_PERIPH
106
107 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
108
109 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
110 is incremented or not.
111 This parameter can be a value of @ref DMA_LL_EC_MEMORY
112
113 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
114
115 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
116 in case of memory to memory transfer direction.
117 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
118
119 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
120
121 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
122 in case of memory to memory transfer direction.
123 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
124
125 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
126
127 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
128 The data unit is equal to the source buffer configuration set in PeripheralSize
129 or MemorySize parameters depending in the transfer direction.
130 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
131
132 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
133
134 uint32_t Channel; /*!< Specifies the peripheral channel.
135 This parameter can be a value of @ref DMA_LL_EC_CHANNEL
136
137 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
138
139 uint32_t Priority; /*!< Specifies the channel priority level.
140 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
141
142 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
143
144 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
145 This parameter can be a value of @ref DMA_LL_FIFOMODE
146 @note The Direct mode (FIFO mode disabled) cannot be used if the
147 memory-to-memory data transfer is configured on the selected stream
148
149 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
150
151 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
152 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
153
154 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
155
156 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
157 It specifies the amount of data to be transferred in a single non interruptible
158 transaction.
159 This parameter can be a value of @ref DMA_LL_EC_MBURST
160 @note The burst mode is possible only if the address Increment mode is enabled.
161
162 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
163
164 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
165 It specifies the amount of data to be transferred in a single non interruptible
166 transaction.
167 This parameter can be a value of @ref DMA_LL_EC_PBURST
168 @note The burst mode is possible only if the address Increment mode is enabled.
169
170 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
171
172} LL_DMA_InitTypeDef;
173/**
174 * @}
175 */
176#endif /*USE_FULL_LL_DRIVER*/
177/* Exported constants --------------------------------------------------------*/
178/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
179 * @{
180 */
181
182/** @defgroup DMA_LL_EC_STREAM STREAM
183 * @{
184 */
185#define LL_DMA_STREAM_0 0x00000000U
186#define LL_DMA_STREAM_1 0x00000001U
187#define LL_DMA_STREAM_2 0x00000002U
188#define LL_DMA_STREAM_3 0x00000003U
189#define LL_DMA_STREAM_4 0x00000004U
190#define LL_DMA_STREAM_5 0x00000005U
191#define LL_DMA_STREAM_6 0x00000006U
192#define LL_DMA_STREAM_7 0x00000007U
193#define LL_DMA_STREAM_ALL 0xFFFF0000U
194/**
195 * @}
196 */
197
198/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
199 * @{
200 */
201#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
202#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
203#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
204/**
205 * @}
206 */
207
208/** @defgroup DMA_LL_EC_MODE MODE
209 * @{
210 */
211#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
212#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
213#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
214/**
215 * @}
216 */
217
218/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
219 * @{
220 */
221#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
222#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
223/**
224 * @}
225 */
226
227/** @defgroup DMA_LL_EC_PERIPH PERIPH
228 * @{
229 */
230#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
231#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
232/**
233 * @}
234 */
235
236/** @defgroup DMA_LL_EC_MEMORY MEMORY
237 * @{
238 */
239#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
240#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
241/**
242 * @}
243 */
244
245/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
246 * @{
247 */
248#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
249#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
250#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
251/**
252 * @}
253 */
254
255/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
256 * @{
257 */
258#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
259#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
260#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
261/**
262 * @}
263 */
264
265/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
266 * @{
267 */
268#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
269#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
270/**
271 * @}
272 */
273
274/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
275 * @{
276 */
277#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
278#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
279#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
280#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
281/**
282 * @}
283 */
284
285/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
286 * @{
287 */
288#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
289#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
290#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
291#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
292#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
293#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
294#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
295#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
296#if defined (DMA_SxCR_CHSEL_3)
297#define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */
298#define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */
299#define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */
300#define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */
301#define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */
302#define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */
303#define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */
304#define LL_DMA_CHANNEL_15 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel15 of DMA Instance */
305#endif /* DMA_SxCR_CHSEL_3 */
306/**
307 * @}
308 */
309
310/** @defgroup DMA_LL_EC_MBURST MBURST
311 * @{
312 */
313#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
314#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
315#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
316#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
317/**
318 * @}
319 */
320
321/** @defgroup DMA_LL_EC_PBURST PBURST
322 * @{
323 */
324#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
325#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
326#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
327#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
328/**
329 * @}
330 */
331
332/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
333 * @{
334 */
335#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
336#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
337/**
338 * @}
339 */
340
341/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
342 * @{
343 */
344#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
345#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
346#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
347#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
348#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
349#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
350/**
351 * @}
352 */
353
354/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
355 * @{
356 */
357#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
358#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
359#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
360#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
361/**
362 * @}
363 */
364
365/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
366 * @{
367 */
368#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
369#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
370/**
371 * @}
372 */
373
374/**
375 * @}
376 */
377
378/* Exported macro ------------------------------------------------------------*/
379/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
380 * @{
381 */
382
383/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
384 * @{
385 */
386/**
387 * @brief Write a value in DMA register
388 * @param __INSTANCE__ DMA Instance
389 * @param __REG__ Register to be written
390 * @param __VALUE__ Value to be written in the register
391 * @retval None
392 */
393#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
394
395/**
396 * @brief Read a value in DMA register
397 * @param __INSTANCE__ DMA Instance
398 * @param __REG__ Register to be read
399 * @retval Register value
400 */
401#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
402/**
403 * @}
404 */
405
406/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
407 * @{
408 */
409/**
410 * @brief Convert DMAx_Streamy into DMAx
411 * @param __STREAM_INSTANCE__ DMAx_Streamy
412 * @retval DMAx
413 */
414#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
415(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
416
417/**
418 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
419 * @param __STREAM_INSTANCE__ DMAx_Streamy
420 * @retval LL_DMA_CHANNEL_y
421 */
422#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
423(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
424 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
425 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
426 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
427 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
428 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
429 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
430 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
431 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
432 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
433 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
434 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
435 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
436 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
437 LL_DMA_STREAM_7)
438
439/**
440 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
441 * @param __DMA_INSTANCE__ DMAx
442 * @param __STREAM__ LL_DMA_STREAM_y
443 * @retval DMAx_Streamy
444 */
445#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
446((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
449 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
450 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
461 DMA2_Stream7)
462
463/**
464 * @}
465 */
466
467/**
468 * @}
469 */
470
471
472/* Exported functions --------------------------------------------------------*/
473 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
474 * @{
475 */
476
477/** @defgroup DMA_LL_EF_Configuration Configuration
478 * @{
479 */
480/**
481 * @brief Enable DMA stream.
482 * @rmtoll CR EN LL_DMA_EnableStream
483 * @param DMAx DMAx Instance
484 * @param Stream This parameter can be one of the following values:
485 * @arg @ref LL_DMA_STREAM_0
486 * @arg @ref LL_DMA_STREAM_1
487 * @arg @ref LL_DMA_STREAM_2
488 * @arg @ref LL_DMA_STREAM_3
489 * @arg @ref LL_DMA_STREAM_4
490 * @arg @ref LL_DMA_STREAM_5
491 * @arg @ref LL_DMA_STREAM_6
492 * @arg @ref LL_DMA_STREAM_7
493 * @retval None
494 */
495__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
496{
497 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
498}
499
500/**
501 * @brief Disable DMA stream.
502 * @rmtoll CR EN LL_DMA_DisableStream
503 * @param DMAx DMAx Instance
504 * @param Stream This parameter can be one of the following values:
505 * @arg @ref LL_DMA_STREAM_0
506 * @arg @ref LL_DMA_STREAM_1
507 * @arg @ref LL_DMA_STREAM_2
508 * @arg @ref LL_DMA_STREAM_3
509 * @arg @ref LL_DMA_STREAM_4
510 * @arg @ref LL_DMA_STREAM_5
511 * @arg @ref LL_DMA_STREAM_6
512 * @arg @ref LL_DMA_STREAM_7
513 * @retval None
514 */
515__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
516{
517 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
518}
519
520/**
521 * @brief Check if DMA stream is enabled or disabled.
522 * @rmtoll CR EN LL_DMA_IsEnabledStream
523 * @param DMAx DMAx Instance
524 * @param Stream This parameter can be one of the following values:
525 * @arg @ref LL_DMA_STREAM_0
526 * @arg @ref LL_DMA_STREAM_1
527 * @arg @ref LL_DMA_STREAM_2
528 * @arg @ref LL_DMA_STREAM_3
529 * @arg @ref LL_DMA_STREAM_4
530 * @arg @ref LL_DMA_STREAM_5
531 * @arg @ref LL_DMA_STREAM_6
532 * @arg @ref LL_DMA_STREAM_7
533 * @retval State of bit (1 or 0).
534 */
535__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
536{
537 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
538}
539
540/**
541 * @brief Configure all parameters linked to DMA transfer.
542 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
543 * CR CIRC LL_DMA_ConfigTransfer\n
544 * CR PINC LL_DMA_ConfigTransfer\n
545 * CR MINC LL_DMA_ConfigTransfer\n
546 * CR PSIZE LL_DMA_ConfigTransfer\n
547 * CR MSIZE LL_DMA_ConfigTransfer\n
548 * CR PL LL_DMA_ConfigTransfer\n
549 * CR PFCTRL LL_DMA_ConfigTransfer
550 * @param DMAx DMAx Instance
551 * @param Stream This parameter can be one of the following values:
552 * @arg @ref LL_DMA_STREAM_0
553 * @arg @ref LL_DMA_STREAM_1
554 * @arg @ref LL_DMA_STREAM_2
555 * @arg @ref LL_DMA_STREAM_3
556 * @arg @ref LL_DMA_STREAM_4
557 * @arg @ref LL_DMA_STREAM_5
558 * @arg @ref LL_DMA_STREAM_6
559 * @arg @ref LL_DMA_STREAM_7
560 * @param Configuration This parameter must be a combination of all the following values:
561 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
562 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
563 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
564 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
565 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
566 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
567 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
568 *@retval None
569 */
570__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
571{
572 MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
573 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
574 Configuration);
575}
576
577/**
578 * @brief Set Data transfer direction (read from peripheral or from memory).
579 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
580 * @param DMAx DMAx Instance
581 * @param Stream This parameter can be one of the following values:
582 * @arg @ref LL_DMA_STREAM_0
583 * @arg @ref LL_DMA_STREAM_1
584 * @arg @ref LL_DMA_STREAM_2
585 * @arg @ref LL_DMA_STREAM_3
586 * @arg @ref LL_DMA_STREAM_4
587 * @arg @ref LL_DMA_STREAM_5
588 * @arg @ref LL_DMA_STREAM_6
589 * @arg @ref LL_DMA_STREAM_7
590 * @param Direction This parameter can be one of the following values:
591 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
592 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
593 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
594 * @retval None
595 */
596__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
597{
598 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
599}
600
601/**
602 * @brief Get Data transfer direction (read from peripheral or from memory).
603 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
604 * @param DMAx DMAx Instance
605 * @param Stream This parameter can be one of the following values:
606 * @arg @ref LL_DMA_STREAM_0
607 * @arg @ref LL_DMA_STREAM_1
608 * @arg @ref LL_DMA_STREAM_2
609 * @arg @ref LL_DMA_STREAM_3
610 * @arg @ref LL_DMA_STREAM_4
611 * @arg @ref LL_DMA_STREAM_5
612 * @arg @ref LL_DMA_STREAM_6
613 * @arg @ref LL_DMA_STREAM_7
614 * @retval Returned value can be one of the following values:
615 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
616 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
617 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
618 */
619__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
620{
621 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
622}
623
624/**
625 * @brief Set DMA mode normal, circular or peripheral flow control.
626 * @rmtoll CR CIRC LL_DMA_SetMode\n
627 * CR PFCTRL LL_DMA_SetMode
628 * @param DMAx DMAx Instance
629 * @param Stream This parameter can be one of the following values:
630 * @arg @ref LL_DMA_STREAM_0
631 * @arg @ref LL_DMA_STREAM_1
632 * @arg @ref LL_DMA_STREAM_2
633 * @arg @ref LL_DMA_STREAM_3
634 * @arg @ref LL_DMA_STREAM_4
635 * @arg @ref LL_DMA_STREAM_5
636 * @arg @ref LL_DMA_STREAM_6
637 * @arg @ref LL_DMA_STREAM_7
638 * @param Mode This parameter can be one of the following values:
639 * @arg @ref LL_DMA_MODE_NORMAL
640 * @arg @ref LL_DMA_MODE_CIRCULAR
641 * @arg @ref LL_DMA_MODE_PFCTRL
642 * @retval None
643 */
644__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
645{
646 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
647}
648
649/**
650 * @brief Get DMA mode normal, circular or peripheral flow control.
651 * @rmtoll CR CIRC LL_DMA_GetMode\n
652 * CR PFCTRL LL_DMA_GetMode
653 * @param DMAx DMAx Instance
654 * @param Stream This parameter can be one of the following values:
655 * @arg @ref LL_DMA_STREAM_0
656 * @arg @ref LL_DMA_STREAM_1
657 * @arg @ref LL_DMA_STREAM_2
658 * @arg @ref LL_DMA_STREAM_3
659 * @arg @ref LL_DMA_STREAM_4
660 * @arg @ref LL_DMA_STREAM_5
661 * @arg @ref LL_DMA_STREAM_6
662 * @arg @ref LL_DMA_STREAM_7
663 * @retval Returned value can be one of the following values:
664 * @arg @ref LL_DMA_MODE_NORMAL
665 * @arg @ref LL_DMA_MODE_CIRCULAR
666 * @arg @ref LL_DMA_MODE_PFCTRL
667 */
668__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
669{
670 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
671}
672
673/**
674 * @brief Set Peripheral increment mode.
675 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
676 * @param DMAx DMAx Instance
677 * @param Stream This parameter can be one of the following values:
678 * @arg @ref LL_DMA_STREAM_0
679 * @arg @ref LL_DMA_STREAM_1
680 * @arg @ref LL_DMA_STREAM_2
681 * @arg @ref LL_DMA_STREAM_3
682 * @arg @ref LL_DMA_STREAM_4
683 * @arg @ref LL_DMA_STREAM_5
684 * @arg @ref LL_DMA_STREAM_6
685 * @arg @ref LL_DMA_STREAM_7
686 * @param IncrementMode This parameter can be one of the following values:
687 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
688 * @arg @ref LL_DMA_PERIPH_INCREMENT
689 * @retval None
690 */
691__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
692{
693 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
694}
695
696/**
697 * @brief Get Peripheral increment mode.
698 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
699 * @param DMAx DMAx Instance
700 * @param Stream This parameter can be one of the following values:
701 * @arg @ref LL_DMA_STREAM_0
702 * @arg @ref LL_DMA_STREAM_1
703 * @arg @ref LL_DMA_STREAM_2
704 * @arg @ref LL_DMA_STREAM_3
705 * @arg @ref LL_DMA_STREAM_4
706 * @arg @ref LL_DMA_STREAM_5
707 * @arg @ref LL_DMA_STREAM_6
708 * @arg @ref LL_DMA_STREAM_7
709 * @retval Returned value can be one of the following values:
710 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
711 * @arg @ref LL_DMA_PERIPH_INCREMENT
712 */
713__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
714{
715 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
716}
717
718/**
719 * @brief Set Memory increment mode.
720 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
721 * @param DMAx DMAx Instance
722 * @param Stream This parameter can be one of the following values:
723 * @arg @ref LL_DMA_STREAM_0
724 * @arg @ref LL_DMA_STREAM_1
725 * @arg @ref LL_DMA_STREAM_2
726 * @arg @ref LL_DMA_STREAM_3
727 * @arg @ref LL_DMA_STREAM_4
728 * @arg @ref LL_DMA_STREAM_5
729 * @arg @ref LL_DMA_STREAM_6
730 * @arg @ref LL_DMA_STREAM_7
731 * @param IncrementMode This parameter can be one of the following values:
732 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
733 * @arg @ref LL_DMA_MEMORY_INCREMENT
734 * @retval None
735 */
736__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
737{
738 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
739}
740
741/**
742 * @brief Get Memory increment mode.
743 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
744 * @param DMAx DMAx Instance
745 * @param Stream This parameter can be one of the following values:
746 * @arg @ref LL_DMA_STREAM_0
747 * @arg @ref LL_DMA_STREAM_1
748 * @arg @ref LL_DMA_STREAM_2
749 * @arg @ref LL_DMA_STREAM_3
750 * @arg @ref LL_DMA_STREAM_4
751 * @arg @ref LL_DMA_STREAM_5
752 * @arg @ref LL_DMA_STREAM_6
753 * @arg @ref LL_DMA_STREAM_7
754 * @retval Returned value can be one of the following values:
755 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
756 * @arg @ref LL_DMA_MEMORY_INCREMENT
757 */
758__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
759{
760 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
761}
762
763/**
764 * @brief Set Peripheral size.
765 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
766 * @param DMAx DMAx Instance
767 * @param Stream This parameter can be one of the following values:
768 * @arg @ref LL_DMA_STREAM_0
769 * @arg @ref LL_DMA_STREAM_1
770 * @arg @ref LL_DMA_STREAM_2
771 * @arg @ref LL_DMA_STREAM_3
772 * @arg @ref LL_DMA_STREAM_4
773 * @arg @ref LL_DMA_STREAM_5
774 * @arg @ref LL_DMA_STREAM_6
775 * @arg @ref LL_DMA_STREAM_7
776 * @param Size This parameter can be one of the following values:
777 * @arg @ref LL_DMA_PDATAALIGN_BYTE
778 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
779 * @arg @ref LL_DMA_PDATAALIGN_WORD
780 * @retval None
781 */
782__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
783{
784 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
785}
786
787/**
788 * @brief Get Peripheral size.
789 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
790 * @param DMAx DMAx Instance
791 * @param Stream This parameter can be one of the following values:
792 * @arg @ref LL_DMA_STREAM_0
793 * @arg @ref LL_DMA_STREAM_1
794 * @arg @ref LL_DMA_STREAM_2
795 * @arg @ref LL_DMA_STREAM_3
796 * @arg @ref LL_DMA_STREAM_4
797 * @arg @ref LL_DMA_STREAM_5
798 * @arg @ref LL_DMA_STREAM_6
799 * @arg @ref LL_DMA_STREAM_7
800 * @retval Returned value can be one of the following values:
801 * @arg @ref LL_DMA_PDATAALIGN_BYTE
802 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
803 * @arg @ref LL_DMA_PDATAALIGN_WORD
804 */
805__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
806{
807 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
808}
809
810/**
811 * @brief Set Memory size.
812 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
813 * @param DMAx DMAx Instance
814 * @param Stream This parameter can be one of the following values:
815 * @arg @ref LL_DMA_STREAM_0
816 * @arg @ref LL_DMA_STREAM_1
817 * @arg @ref LL_DMA_STREAM_2
818 * @arg @ref LL_DMA_STREAM_3
819 * @arg @ref LL_DMA_STREAM_4
820 * @arg @ref LL_DMA_STREAM_5
821 * @arg @ref LL_DMA_STREAM_6
822 * @arg @ref LL_DMA_STREAM_7
823 * @param Size This parameter can be one of the following values:
824 * @arg @ref LL_DMA_MDATAALIGN_BYTE
825 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
826 * @arg @ref LL_DMA_MDATAALIGN_WORD
827 * @retval None
828 */
829__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
830{
831 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
832}
833
834/**
835 * @brief Get Memory size.
836 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
837 * @param DMAx DMAx Instance
838 * @param Stream This parameter can be one of the following values:
839 * @arg @ref LL_DMA_STREAM_0
840 * @arg @ref LL_DMA_STREAM_1
841 * @arg @ref LL_DMA_STREAM_2
842 * @arg @ref LL_DMA_STREAM_3
843 * @arg @ref LL_DMA_STREAM_4
844 * @arg @ref LL_DMA_STREAM_5
845 * @arg @ref LL_DMA_STREAM_6
846 * @arg @ref LL_DMA_STREAM_7
847 * @retval Returned value can be one of the following values:
848 * @arg @ref LL_DMA_MDATAALIGN_BYTE
849 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
850 * @arg @ref LL_DMA_MDATAALIGN_WORD
851 */
852__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
853{
854 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
855}
856
857/**
858 * @brief Set Peripheral increment offset size.
859 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
860 * @param DMAx DMAx Instance
861 * @param Stream This parameter can be one of the following values:
862 * @arg @ref LL_DMA_STREAM_0
863 * @arg @ref LL_DMA_STREAM_1
864 * @arg @ref LL_DMA_STREAM_2
865 * @arg @ref LL_DMA_STREAM_3
866 * @arg @ref LL_DMA_STREAM_4
867 * @arg @ref LL_DMA_STREAM_5
868 * @arg @ref LL_DMA_STREAM_6
869 * @arg @ref LL_DMA_STREAM_7
870 * @param OffsetSize This parameter can be one of the following values:
871 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
872 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
873 * @retval None
874 */
875__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
876{
877 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
878}
879
880/**
881 * @brief Get Peripheral increment offset size.
882 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
883 * @param DMAx DMAx Instance
884 * @param Stream This parameter can be one of the following values:
885 * @arg @ref LL_DMA_STREAM_0
886 * @arg @ref LL_DMA_STREAM_1
887 * @arg @ref LL_DMA_STREAM_2
888 * @arg @ref LL_DMA_STREAM_3
889 * @arg @ref LL_DMA_STREAM_4
890 * @arg @ref LL_DMA_STREAM_5
891 * @arg @ref LL_DMA_STREAM_6
892 * @arg @ref LL_DMA_STREAM_7
893 * @retval Returned value can be one of the following values:
894 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
895 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
896 */
897__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
898{
899 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
900}
901
902/**
903 * @brief Set Stream priority level.
904 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
905 * @param DMAx DMAx Instance
906 * @param Stream This parameter can be one of the following values:
907 * @arg @ref LL_DMA_STREAM_0
908 * @arg @ref LL_DMA_STREAM_1
909 * @arg @ref LL_DMA_STREAM_2
910 * @arg @ref LL_DMA_STREAM_3
911 * @arg @ref LL_DMA_STREAM_4
912 * @arg @ref LL_DMA_STREAM_5
913 * @arg @ref LL_DMA_STREAM_6
914 * @arg @ref LL_DMA_STREAM_7
915 * @param Priority This parameter can be one of the following values:
916 * @arg @ref LL_DMA_PRIORITY_LOW
917 * @arg @ref LL_DMA_PRIORITY_MEDIUM
918 * @arg @ref LL_DMA_PRIORITY_HIGH
919 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
920 * @retval None
921 */
922__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
923{
924 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
925}
926
927/**
928 * @brief Get Stream priority level.
929 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
930 * @param DMAx DMAx Instance
931 * @param Stream This parameter can be one of the following values:
932 * @arg @ref LL_DMA_STREAM_0
933 * @arg @ref LL_DMA_STREAM_1
934 * @arg @ref LL_DMA_STREAM_2
935 * @arg @ref LL_DMA_STREAM_3
936 * @arg @ref LL_DMA_STREAM_4
937 * @arg @ref LL_DMA_STREAM_5
938 * @arg @ref LL_DMA_STREAM_6
939 * @arg @ref LL_DMA_STREAM_7
940 * @retval Returned value can be one of the following values:
941 * @arg @ref LL_DMA_PRIORITY_LOW
942 * @arg @ref LL_DMA_PRIORITY_MEDIUM
943 * @arg @ref LL_DMA_PRIORITY_HIGH
944 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
945 */
946__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
947{
948 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
949}
950
951/**
952 * @brief Set Number of data to transfer.
953 * @rmtoll NDTR NDT LL_DMA_SetDataLength
954 * @note This action has no effect if
955 * stream is enabled.
956 * @param DMAx DMAx Instance
957 * @param Stream This parameter can be one of the following values:
958 * @arg @ref LL_DMA_STREAM_0
959 * @arg @ref LL_DMA_STREAM_1
960 * @arg @ref LL_DMA_STREAM_2
961 * @arg @ref LL_DMA_STREAM_3
962 * @arg @ref LL_DMA_STREAM_4
963 * @arg @ref LL_DMA_STREAM_5
964 * @arg @ref LL_DMA_STREAM_6
965 * @arg @ref LL_DMA_STREAM_7
966 * @param NbData Between 0 to 0xFFFFFFFF
967 * @retval None
968 */
969__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
970{
971 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
972}
973
974/**
975 * @brief Get Number of data to transfer.
976 * @rmtoll NDTR NDT LL_DMA_GetDataLength
977 * @note Once the stream is enabled, the return value indicate the
978 * remaining bytes to be transmitted.
979 * @param DMAx DMAx Instance
980 * @param Stream This parameter can be one of the following values:
981 * @arg @ref LL_DMA_STREAM_0
982 * @arg @ref LL_DMA_STREAM_1
983 * @arg @ref LL_DMA_STREAM_2
984 * @arg @ref LL_DMA_STREAM_3
985 * @arg @ref LL_DMA_STREAM_4
986 * @arg @ref LL_DMA_STREAM_5
987 * @arg @ref LL_DMA_STREAM_6
988 * @arg @ref LL_DMA_STREAM_7
989 * @retval Between 0 to 0xFFFFFFFF
990 */
991__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
992{
993 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
994}
995
996/**
997 * @brief Select Channel number associated to the Stream.
998 * @rmtoll CR CHSEL LL_DMA_SetChannelSelection
999 * @param DMAx DMAx Instance
1000 * @param Stream This parameter can be one of the following values:
1001 * @arg @ref LL_DMA_STREAM_0
1002 * @arg @ref LL_DMA_STREAM_1
1003 * @arg @ref LL_DMA_STREAM_2
1004 * @arg @ref LL_DMA_STREAM_3
1005 * @arg @ref LL_DMA_STREAM_4
1006 * @arg @ref LL_DMA_STREAM_5
1007 * @arg @ref LL_DMA_STREAM_6
1008 * @arg @ref LL_DMA_STREAM_7
1009 * @param Channel This parameter can be one of the following values:
1010 * @arg @ref LL_DMA_CHANNEL_0
1011 * @arg @ref LL_DMA_CHANNEL_1
1012 * @arg @ref LL_DMA_CHANNEL_2
1013 * @arg @ref LL_DMA_CHANNEL_3
1014 * @arg @ref LL_DMA_CHANNEL_4
1015 * @arg @ref LL_DMA_CHANNEL_5
1016 * @arg @ref LL_DMA_CHANNEL_6
1017 * @arg @ref LL_DMA_CHANNEL_7
1018 * @retval None
1019 */
1020__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
1021{
1022 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
1023}
1024
1025/**
1026 * @brief Get the Channel number associated to the Stream.
1027 * @rmtoll CR CHSEL LL_DMA_GetChannelSelection
1028 * @param DMAx DMAx Instance
1029 * @param Stream This parameter can be one of the following values:
1030 * @arg @ref LL_DMA_STREAM_0
1031 * @arg @ref LL_DMA_STREAM_1
1032 * @arg @ref LL_DMA_STREAM_2
1033 * @arg @ref LL_DMA_STREAM_3
1034 * @arg @ref LL_DMA_STREAM_4
1035 * @arg @ref LL_DMA_STREAM_5
1036 * @arg @ref LL_DMA_STREAM_6
1037 * @arg @ref LL_DMA_STREAM_7
1038 * @retval Returned value can be one of the following values:
1039 * @arg @ref LL_DMA_CHANNEL_0
1040 * @arg @ref LL_DMA_CHANNEL_1
1041 * @arg @ref LL_DMA_CHANNEL_2
1042 * @arg @ref LL_DMA_CHANNEL_3
1043 * @arg @ref LL_DMA_CHANNEL_4
1044 * @arg @ref LL_DMA_CHANNEL_5
1045 * @arg @ref LL_DMA_CHANNEL_6
1046 * @arg @ref LL_DMA_CHANNEL_7
1047 */
1048__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
1049{
1050 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
1051}
1052
1053/**
1054 * @brief Set Memory burst transfer configuration.
1055 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1056 * @param DMAx DMAx Instance
1057 * @param Stream This parameter can be one of the following values:
1058 * @arg @ref LL_DMA_STREAM_0
1059 * @arg @ref LL_DMA_STREAM_1
1060 * @arg @ref LL_DMA_STREAM_2
1061 * @arg @ref LL_DMA_STREAM_3
1062 * @arg @ref LL_DMA_STREAM_4
1063 * @arg @ref LL_DMA_STREAM_5
1064 * @arg @ref LL_DMA_STREAM_6
1065 * @arg @ref LL_DMA_STREAM_7
1066 * @param Mburst This parameter can be one of the following values:
1067 * @arg @ref LL_DMA_MBURST_SINGLE
1068 * @arg @ref LL_DMA_MBURST_INC4
1069 * @arg @ref LL_DMA_MBURST_INC8
1070 * @arg @ref LL_DMA_MBURST_INC16
1071 * @retval None
1072 */
1073__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1074{
1075 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
1076}
1077
1078/**
1079 * @brief Get Memory burst transfer configuration.
1080 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1081 * @param DMAx DMAx Instance
1082 * @param Stream This parameter can be one of the following values:
1083 * @arg @ref LL_DMA_STREAM_0
1084 * @arg @ref LL_DMA_STREAM_1
1085 * @arg @ref LL_DMA_STREAM_2
1086 * @arg @ref LL_DMA_STREAM_3
1087 * @arg @ref LL_DMA_STREAM_4
1088 * @arg @ref LL_DMA_STREAM_5
1089 * @arg @ref LL_DMA_STREAM_6
1090 * @arg @ref LL_DMA_STREAM_7
1091 * @retval Returned value can be one of the following values:
1092 * @arg @ref LL_DMA_MBURST_SINGLE
1093 * @arg @ref LL_DMA_MBURST_INC4
1094 * @arg @ref LL_DMA_MBURST_INC8
1095 * @arg @ref LL_DMA_MBURST_INC16
1096 */
1097__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1098{
1099 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
1100}
1101
1102/**
1103 * @brief Set Peripheral burst transfer configuration.
1104 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1105 * @param DMAx DMAx Instance
1106 * @param Stream This parameter can be one of the following values:
1107 * @arg @ref LL_DMA_STREAM_0
1108 * @arg @ref LL_DMA_STREAM_1
1109 * @arg @ref LL_DMA_STREAM_2
1110 * @arg @ref LL_DMA_STREAM_3
1111 * @arg @ref LL_DMA_STREAM_4
1112 * @arg @ref LL_DMA_STREAM_5
1113 * @arg @ref LL_DMA_STREAM_6
1114 * @arg @ref LL_DMA_STREAM_7
1115 * @param Pburst This parameter can be one of the following values:
1116 * @arg @ref LL_DMA_PBURST_SINGLE
1117 * @arg @ref LL_DMA_PBURST_INC4
1118 * @arg @ref LL_DMA_PBURST_INC8
1119 * @arg @ref LL_DMA_PBURST_INC16
1120 * @retval None
1121 */
1122__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1123{
1124 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
1125}
1126
1127/**
1128 * @brief Get Peripheral burst transfer configuration.
1129 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1130 * @param DMAx DMAx Instance
1131 * @param Stream This parameter can be one of the following values:
1132 * @arg @ref LL_DMA_STREAM_0
1133 * @arg @ref LL_DMA_STREAM_1
1134 * @arg @ref LL_DMA_STREAM_2
1135 * @arg @ref LL_DMA_STREAM_3
1136 * @arg @ref LL_DMA_STREAM_4
1137 * @arg @ref LL_DMA_STREAM_5
1138 * @arg @ref LL_DMA_STREAM_6
1139 * @arg @ref LL_DMA_STREAM_7
1140 * @retval Returned value can be one of the following values:
1141 * @arg @ref LL_DMA_PBURST_SINGLE
1142 * @arg @ref LL_DMA_PBURST_INC4
1143 * @arg @ref LL_DMA_PBURST_INC8
1144 * @arg @ref LL_DMA_PBURST_INC16
1145 */
1146__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1147{
1148 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
1149}
1150
1151/**
1152 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1153 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1154 * @param DMAx DMAx Instance
1155 * @param Stream This parameter can be one of the following values:
1156 * @arg @ref LL_DMA_STREAM_0
1157 * @arg @ref LL_DMA_STREAM_1
1158 * @arg @ref LL_DMA_STREAM_2
1159 * @arg @ref LL_DMA_STREAM_3
1160 * @arg @ref LL_DMA_STREAM_4
1161 * @arg @ref LL_DMA_STREAM_5
1162 * @arg @ref LL_DMA_STREAM_6
1163 * @arg @ref LL_DMA_STREAM_7
1164 * @param CurrentMemory This parameter can be one of the following values:
1165 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1166 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1167 * @retval None
1168 */
1169__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1170{
1171 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
1172}
1173
1174/**
1175 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1176 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1177 * @param DMAx DMAx Instance
1178 * @param Stream This parameter can be one of the following values:
1179 * @arg @ref LL_DMA_STREAM_0
1180 * @arg @ref LL_DMA_STREAM_1
1181 * @arg @ref LL_DMA_STREAM_2
1182 * @arg @ref LL_DMA_STREAM_3
1183 * @arg @ref LL_DMA_STREAM_4
1184 * @arg @ref LL_DMA_STREAM_5
1185 * @arg @ref LL_DMA_STREAM_6
1186 * @arg @ref LL_DMA_STREAM_7
1187 * @retval Returned value can be one of the following values:
1188 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1189 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1190 */
1191__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
1192{
1193 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
1194}
1195
1196/**
1197 * @brief Enable the double buffer mode.
1198 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1199 * @param DMAx DMAx Instance
1200 * @param Stream This parameter can be one of the following values:
1201 * @arg @ref LL_DMA_STREAM_0
1202 * @arg @ref LL_DMA_STREAM_1
1203 * @arg @ref LL_DMA_STREAM_2
1204 * @arg @ref LL_DMA_STREAM_3
1205 * @arg @ref LL_DMA_STREAM_4
1206 * @arg @ref LL_DMA_STREAM_5
1207 * @arg @ref LL_DMA_STREAM_6
1208 * @arg @ref LL_DMA_STREAM_7
1209 * @retval None
1210 */
1211__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1212{
1213 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1214}
1215
1216/**
1217 * @brief Disable the double buffer mode.
1218 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1219 * @param DMAx DMAx Instance
1220 * @param Stream This parameter can be one of the following values:
1221 * @arg @ref LL_DMA_STREAM_0
1222 * @arg @ref LL_DMA_STREAM_1
1223 * @arg @ref LL_DMA_STREAM_2
1224 * @arg @ref LL_DMA_STREAM_3
1225 * @arg @ref LL_DMA_STREAM_4
1226 * @arg @ref LL_DMA_STREAM_5
1227 * @arg @ref LL_DMA_STREAM_6
1228 * @arg @ref LL_DMA_STREAM_7
1229 * @retval None
1230 */
1231__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1232{
1233 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1234}
1235
1236/**
1237 * @brief Get FIFO status.
1238 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1239 * @param DMAx DMAx Instance
1240 * @param Stream This parameter can be one of the following values:
1241 * @arg @ref LL_DMA_STREAM_0
1242 * @arg @ref LL_DMA_STREAM_1
1243 * @arg @ref LL_DMA_STREAM_2
1244 * @arg @ref LL_DMA_STREAM_3
1245 * @arg @ref LL_DMA_STREAM_4
1246 * @arg @ref LL_DMA_STREAM_5
1247 * @arg @ref LL_DMA_STREAM_6
1248 * @arg @ref LL_DMA_STREAM_7
1249 * @retval Returned value can be one of the following values:
1250 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1251 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1252 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1253 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1254 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1255 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1256 */
1257__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
1258{
1259 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
1260}
1261
1262/**
1263 * @brief Disable Fifo mode.
1264 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1265 * @param DMAx DMAx Instance
1266 * @param Stream This parameter can be one of the following values:
1267 * @arg @ref LL_DMA_STREAM_0
1268 * @arg @ref LL_DMA_STREAM_1
1269 * @arg @ref LL_DMA_STREAM_2
1270 * @arg @ref LL_DMA_STREAM_3
1271 * @arg @ref LL_DMA_STREAM_4
1272 * @arg @ref LL_DMA_STREAM_5
1273 * @arg @ref LL_DMA_STREAM_6
1274 * @arg @ref LL_DMA_STREAM_7
1275 * @retval None
1276 */
1277__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1278{
1279 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1280}
1281
1282/**
1283 * @brief Enable Fifo mode.
1284 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1285 * @param DMAx DMAx Instance
1286 * @param Stream This parameter can be one of the following values:
1287 * @arg @ref LL_DMA_STREAM_0
1288 * @arg @ref LL_DMA_STREAM_1
1289 * @arg @ref LL_DMA_STREAM_2
1290 * @arg @ref LL_DMA_STREAM_3
1291 * @arg @ref LL_DMA_STREAM_4
1292 * @arg @ref LL_DMA_STREAM_5
1293 * @arg @ref LL_DMA_STREAM_6
1294 * @arg @ref LL_DMA_STREAM_7
1295 * @retval None
1296 */
1297__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1298{
1299 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1300}
1301
1302/**
1303 * @brief Select FIFO threshold.
1304 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1305 * @param DMAx DMAx Instance
1306 * @param Stream This parameter can be one of the following values:
1307 * @arg @ref LL_DMA_STREAM_0
1308 * @arg @ref LL_DMA_STREAM_1
1309 * @arg @ref LL_DMA_STREAM_2
1310 * @arg @ref LL_DMA_STREAM_3
1311 * @arg @ref LL_DMA_STREAM_4
1312 * @arg @ref LL_DMA_STREAM_5
1313 * @arg @ref LL_DMA_STREAM_6
1314 * @arg @ref LL_DMA_STREAM_7
1315 * @param Threshold This parameter can be one of the following values:
1316 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1317 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1318 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1319 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1320 * @retval None
1321 */
1322__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1323{
1324 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
1325}
1326
1327/**
1328 * @brief Get FIFO threshold.
1329 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1330 * @param DMAx DMAx Instance
1331 * @param Stream This parameter can be one of the following values:
1332 * @arg @ref LL_DMA_STREAM_0
1333 * @arg @ref LL_DMA_STREAM_1
1334 * @arg @ref LL_DMA_STREAM_2
1335 * @arg @ref LL_DMA_STREAM_3
1336 * @arg @ref LL_DMA_STREAM_4
1337 * @arg @ref LL_DMA_STREAM_5
1338 * @arg @ref LL_DMA_STREAM_6
1339 * @arg @ref LL_DMA_STREAM_7
1340 * @retval Returned value can be one of the following values:
1341 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1342 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1343 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1344 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1345 */
1346__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
1347{
1348 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
1349}
1350
1351/**
1352 * @brief Configure the FIFO .
1353 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1354 * FCR DMDIS LL_DMA_ConfigFifo
1355 * @param DMAx DMAx Instance
1356 * @param Stream This parameter can be one of the following values:
1357 * @arg @ref LL_DMA_STREAM_0
1358 * @arg @ref LL_DMA_STREAM_1
1359 * @arg @ref LL_DMA_STREAM_2
1360 * @arg @ref LL_DMA_STREAM_3
1361 * @arg @ref LL_DMA_STREAM_4
1362 * @arg @ref LL_DMA_STREAM_5
1363 * @arg @ref LL_DMA_STREAM_6
1364 * @arg @ref LL_DMA_STREAM_7
1365 * @param FifoMode This parameter can be one of the following values:
1366 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1367 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1368 * @param FifoThreshold This parameter can be one of the following values:
1369 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1370 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1371 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1372 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1373 * @retval None
1374 */
1375__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1376{
1377 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
1378}
1379
1380/**
1381 * @brief Configure the Source and Destination addresses.
1382 * @note This API must not be called when the DMA stream is enabled.
1383 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1384 * PAR PA LL_DMA_ConfigAddresses
1385 * @param DMAx DMAx Instance
1386 * @param Stream This parameter can be one of the following values:
1387 * @arg @ref LL_DMA_STREAM_0
1388 * @arg @ref LL_DMA_STREAM_1
1389 * @arg @ref LL_DMA_STREAM_2
1390 * @arg @ref LL_DMA_STREAM_3
1391 * @arg @ref LL_DMA_STREAM_4
1392 * @arg @ref LL_DMA_STREAM_5
1393 * @arg @ref LL_DMA_STREAM_6
1394 * @arg @ref LL_DMA_STREAM_7
1395 * @param SrcAddress Between 0 to 0xFFFFFFFF
1396 * @param DstAddress Between 0 to 0xFFFFFFFF
1397 * @param Direction This parameter can be one of the following values:
1398 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1399 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1400 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1401 * @retval None
1402 */
1403__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1404{
1405 /* Direction Memory to Periph */
1406 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1407 {
1408 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
1409 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
1410 }
1411 /* Direction Periph to Memory and Memory to Memory */
1412 else
1413 {
1414 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
1415 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
1416 }
1417}
1418
1419/**
1420 * @brief Set the Memory address.
1421 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1422 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1423 * @note This API must not be called when the DMA channel is enabled.
1424 * @param DMAx DMAx Instance
1425 * @param Stream This parameter can be one of the following values:
1426 * @arg @ref LL_DMA_STREAM_0
1427 * @arg @ref LL_DMA_STREAM_1
1428 * @arg @ref LL_DMA_STREAM_2
1429 * @arg @ref LL_DMA_STREAM_3
1430 * @arg @ref LL_DMA_STREAM_4
1431 * @arg @ref LL_DMA_STREAM_5
1432 * @arg @ref LL_DMA_STREAM_6
1433 * @arg @ref LL_DMA_STREAM_7
1434 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1435 * @retval None
1436 */
1437__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1438{
1439 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1440}
1441
1442/**
1443 * @brief Set the Peripheral address.
1444 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1445 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1446 * @note This API must not be called when the DMA channel is enabled.
1447 * @param DMAx DMAx Instance
1448 * @param Stream This parameter can be one of the following values:
1449 * @arg @ref LL_DMA_STREAM_0
1450 * @arg @ref LL_DMA_STREAM_1
1451 * @arg @ref LL_DMA_STREAM_2
1452 * @arg @ref LL_DMA_STREAM_3
1453 * @arg @ref LL_DMA_STREAM_4
1454 * @arg @ref LL_DMA_STREAM_5
1455 * @arg @ref LL_DMA_STREAM_6
1456 * @arg @ref LL_DMA_STREAM_7
1457 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1458 * @retval None
1459 */
1460__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
1461{
1462 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
1463}
1464
1465/**
1466 * @brief Get the Memory address.
1467 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1468 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1469 * @param DMAx DMAx Instance
1470 * @param Stream This parameter can be one of the following values:
1471 * @arg @ref LL_DMA_STREAM_0
1472 * @arg @ref LL_DMA_STREAM_1
1473 * @arg @ref LL_DMA_STREAM_2
1474 * @arg @ref LL_DMA_STREAM_3
1475 * @arg @ref LL_DMA_STREAM_4
1476 * @arg @ref LL_DMA_STREAM_5
1477 * @arg @ref LL_DMA_STREAM_6
1478 * @arg @ref LL_DMA_STREAM_7
1479 * @retval Between 0 to 0xFFFFFFFF
1480 */
1481__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1482{
1483 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1484}
1485
1486/**
1487 * @brief Get the Peripheral address.
1488 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1489 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1490 * @param DMAx DMAx Instance
1491 * @param Stream This parameter can be one of the following values:
1492 * @arg @ref LL_DMA_STREAM_0
1493 * @arg @ref LL_DMA_STREAM_1
1494 * @arg @ref LL_DMA_STREAM_2
1495 * @arg @ref LL_DMA_STREAM_3
1496 * @arg @ref LL_DMA_STREAM_4
1497 * @arg @ref LL_DMA_STREAM_5
1498 * @arg @ref LL_DMA_STREAM_6
1499 * @arg @ref LL_DMA_STREAM_7
1500 * @retval Between 0 to 0xFFFFFFFF
1501 */
1502__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1503{
1504 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1505}
1506
1507/**
1508 * @brief Set the Memory to Memory Source address.
1509 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1510 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1511 * @note This API must not be called when the DMA channel is enabled.
1512 * @param DMAx DMAx Instance
1513 * @param Stream This parameter can be one of the following values:
1514 * @arg @ref LL_DMA_STREAM_0
1515 * @arg @ref LL_DMA_STREAM_1
1516 * @arg @ref LL_DMA_STREAM_2
1517 * @arg @ref LL_DMA_STREAM_3
1518 * @arg @ref LL_DMA_STREAM_4
1519 * @arg @ref LL_DMA_STREAM_5
1520 * @arg @ref LL_DMA_STREAM_6
1521 * @arg @ref LL_DMA_STREAM_7
1522 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1523 * @retval None
1524 */
1525__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1526{
1527 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
1528}
1529
1530/**
1531 * @brief Set the Memory to Memory Destination address.
1532 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1533 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1534 * @note This API must not be called when the DMA channel is enabled.
1535 * @param DMAx DMAx Instance
1536 * @param Stream This parameter can be one of the following values:
1537 * @arg @ref LL_DMA_STREAM_0
1538 * @arg @ref LL_DMA_STREAM_1
1539 * @arg @ref LL_DMA_STREAM_2
1540 * @arg @ref LL_DMA_STREAM_3
1541 * @arg @ref LL_DMA_STREAM_4
1542 * @arg @ref LL_DMA_STREAM_5
1543 * @arg @ref LL_DMA_STREAM_6
1544 * @arg @ref LL_DMA_STREAM_7
1545 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1546 * @retval None
1547 */
1548__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1549 {
1550 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1551 }
1552
1553/**
1554 * @brief Get the Memory to Memory Source address.
1555 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1556 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1557 * @param DMAx DMAx Instance
1558 * @param Stream This parameter can be one of the following values:
1559 * @arg @ref LL_DMA_STREAM_0
1560 * @arg @ref LL_DMA_STREAM_1
1561 * @arg @ref LL_DMA_STREAM_2
1562 * @arg @ref LL_DMA_STREAM_3
1563 * @arg @ref LL_DMA_STREAM_4
1564 * @arg @ref LL_DMA_STREAM_5
1565 * @arg @ref LL_DMA_STREAM_6
1566 * @arg @ref LL_DMA_STREAM_7
1567 * @retval Between 0 to 0xFFFFFFFF
1568 */
1569__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1570 {
1571 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1572 }
1573
1574/**
1575 * @brief Get the Memory to Memory Destination address.
1576 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1577 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1578 * @param DMAx DMAx Instance
1579 * @param Stream This parameter can be one of the following values:
1580 * @arg @ref LL_DMA_STREAM_0
1581 * @arg @ref LL_DMA_STREAM_1
1582 * @arg @ref LL_DMA_STREAM_2
1583 * @arg @ref LL_DMA_STREAM_3
1584 * @arg @ref LL_DMA_STREAM_4
1585 * @arg @ref LL_DMA_STREAM_5
1586 * @arg @ref LL_DMA_STREAM_6
1587 * @arg @ref LL_DMA_STREAM_7
1588 * @retval Between 0 to 0xFFFFFFFF
1589 */
1590__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1591{
1592 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1593}
1594
1595/**
1596 * @brief Set Memory 1 address (used in case of Double buffer mode).
1597 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1598 * @param DMAx DMAx Instance
1599 * @param Stream This parameter can be one of the following values:
1600 * @arg @ref LL_DMA_STREAM_0
1601 * @arg @ref LL_DMA_STREAM_1
1602 * @arg @ref LL_DMA_STREAM_2
1603 * @arg @ref LL_DMA_STREAM_3
1604 * @arg @ref LL_DMA_STREAM_4
1605 * @arg @ref LL_DMA_STREAM_5
1606 * @arg @ref LL_DMA_STREAM_6
1607 * @arg @ref LL_DMA_STREAM_7
1608 * @param Address Between 0 to 0xFFFFFFFF
1609 * @retval None
1610 */
1611__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1612{
1613 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
1614}
1615
1616/**
1617 * @brief Get Memory 1 address (used in case of Double buffer mode).
1618 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
1619 * @param DMAx DMAx Instance
1620 * @param Stream This parameter can be one of the following values:
1621 * @arg @ref LL_DMA_STREAM_0
1622 * @arg @ref LL_DMA_STREAM_1
1623 * @arg @ref LL_DMA_STREAM_2
1624 * @arg @ref LL_DMA_STREAM_3
1625 * @arg @ref LL_DMA_STREAM_4
1626 * @arg @ref LL_DMA_STREAM_5
1627 * @arg @ref LL_DMA_STREAM_6
1628 * @arg @ref LL_DMA_STREAM_7
1629 * @retval Between 0 to 0xFFFFFFFF
1630 */
1631__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
1632{
1633 return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
1634}
1635
1636/**
1637 * @}
1638 */
1639
1640/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1641 * @{
1642 */
1643
1644/**
1645 * @brief Get Stream 0 half transfer flag.
1646 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
1647 * @param DMAx DMAx Instance
1648 * @retval State of bit (1 or 0).
1649 */
1650__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
1651{
1652 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
1653}
1654
1655/**
1656 * @brief Get Stream 1 half transfer flag.
1657 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
1658 * @param DMAx DMAx Instance
1659 * @retval State of bit (1 or 0).
1660 */
1661__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1662{
1663 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
1664}
1665
1666/**
1667 * @brief Get Stream 2 half transfer flag.
1668 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
1669 * @param DMAx DMAx Instance
1670 * @retval State of bit (1 or 0).
1671 */
1672__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1673{
1674 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
1675}
1676
1677/**
1678 * @brief Get Stream 3 half transfer flag.
1679 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
1680 * @param DMAx DMAx Instance
1681 * @retval State of bit (1 or 0).
1682 */
1683__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1684{
1685 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
1686}
1687
1688/**
1689 * @brief Get Stream 4 half transfer flag.
1690 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
1691 * @param DMAx DMAx Instance
1692 * @retval State of bit (1 or 0).
1693 */
1694__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1695{
1696 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
1697}
1698
1699/**
1700 * @brief Get Stream 5 half transfer flag.
1701 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
1702 * @param DMAx DMAx Instance
1703 * @retval State of bit (1 or 0).
1704 */
1705__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1706{
1707 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
1708}
1709
1710/**
1711 * @brief Get Stream 6 half transfer flag.
1712 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
1713 * @param DMAx DMAx Instance
1714 * @retval State of bit (1 or 0).
1715 */
1716__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1717{
1718 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
1719}
1720
1721/**
1722 * @brief Get Stream 7 half transfer flag.
1723 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
1724 * @param DMAx DMAx Instance
1725 * @retval State of bit (1 or 0).
1726 */
1727__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1728{
1729 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
1730}
1731
1732/**
1733 * @brief Get Stream 0 transfer complete flag.
1734 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
1735 * @param DMAx DMAx Instance
1736 * @retval State of bit (1 or 0).
1737 */
1738__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
1739{
1740 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
1741}
1742
1743/**
1744 * @brief Get Stream 1 transfer complete flag.
1745 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
1746 * @param DMAx DMAx Instance
1747 * @retval State of bit (1 or 0).
1748 */
1749__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1750{
1751 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
1752}
1753
1754/**
1755 * @brief Get Stream 2 transfer complete flag.
1756 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
1757 * @param DMAx DMAx Instance
1758 * @retval State of bit (1 or 0).
1759 */
1760__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1761{
1762 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
1763}
1764
1765/**
1766 * @brief Get Stream 3 transfer complete flag.
1767 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
1768 * @param DMAx DMAx Instance
1769 * @retval State of bit (1 or 0).
1770 */
1771__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1772{
1773 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
1774}
1775
1776/**
1777 * @brief Get Stream 4 transfer complete flag.
1778 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
1779 * @param DMAx DMAx Instance
1780 * @retval State of bit (1 or 0).
1781 */
1782__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1783{
1784 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
1785}
1786
1787/**
1788 * @brief Get Stream 5 transfer complete flag.
1789 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
1790 * @param DMAx DMAx Instance
1791 * @retval State of bit (1 or 0).
1792 */
1793__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1794{
1795 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
1796}
1797
1798/**
1799 * @brief Get Stream 6 transfer complete flag.
1800 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
1801 * @param DMAx DMAx Instance
1802 * @retval State of bit (1 or 0).
1803 */
1804__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1805{
1806 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
1807}
1808
1809/**
1810 * @brief Get Stream 7 transfer complete flag.
1811 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
1812 * @param DMAx DMAx Instance
1813 * @retval State of bit (1 or 0).
1814 */
1815__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1816{
1817 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
1818}
1819
1820/**
1821 * @brief Get Stream 0 transfer error flag.
1822 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
1823 * @param DMAx DMAx Instance
1824 * @retval State of bit (1 or 0).
1825 */
1826__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
1827{
1828 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
1829}
1830
1831/**
1832 * @brief Get Stream 1 transfer error flag.
1833 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
1834 * @param DMAx DMAx Instance
1835 * @retval State of bit (1 or 0).
1836 */
1837__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1838{
1839 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
1840}
1841
1842/**
1843 * @brief Get Stream 2 transfer error flag.
1844 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
1845 * @param DMAx DMAx Instance
1846 * @retval State of bit (1 or 0).
1847 */
1848__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1849{
1850 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
1851}
1852
1853/**
1854 * @brief Get Stream 3 transfer error flag.
1855 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
1856 * @param DMAx DMAx Instance
1857 * @retval State of bit (1 or 0).
1858 */
1859__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1860{
1861 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
1862}
1863
1864/**
1865 * @brief Get Stream 4 transfer error flag.
1866 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
1867 * @param DMAx DMAx Instance
1868 * @retval State of bit (1 or 0).
1869 */
1870__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1871{
1872 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
1873}
1874
1875/**
1876 * @brief Get Stream 5 transfer error flag.
1877 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
1878 * @param DMAx DMAx Instance
1879 * @retval State of bit (1 or 0).
1880 */
1881__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1882{
1883 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
1884}
1885
1886/**
1887 * @brief Get Stream 6 transfer error flag.
1888 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
1889 * @param DMAx DMAx Instance
1890 * @retval State of bit (1 or 0).
1891 */
1892__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1893{
1894 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
1895}
1896
1897/**
1898 * @brief Get Stream 7 transfer error flag.
1899 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
1900 * @param DMAx DMAx Instance
1901 * @retval State of bit (1 or 0).
1902 */
1903__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1904{
1905 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
1906}
1907
1908/**
1909 * @brief Get Stream 0 direct mode error flag.
1910 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
1911 * @param DMAx DMAx Instance
1912 * @retval State of bit (1 or 0).
1913 */
1914__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
1915{
1916 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
1917}
1918
1919/**
1920 * @brief Get Stream 1 direct mode error flag.
1921 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
1922 * @param DMAx DMAx Instance
1923 * @retval State of bit (1 or 0).
1924 */
1925__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
1926{
1927 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
1928}
1929
1930/**
1931 * @brief Get Stream 2 direct mode error flag.
1932 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
1933 * @param DMAx DMAx Instance
1934 * @retval State of bit (1 or 0).
1935 */
1936__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
1937{
1938 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
1939}
1940
1941/**
1942 * @brief Get Stream 3 direct mode error flag.
1943 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
1944 * @param DMAx DMAx Instance
1945 * @retval State of bit (1 or 0).
1946 */
1947__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
1948{
1949 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
1950}
1951
1952/**
1953 * @brief Get Stream 4 direct mode error flag.
1954 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
1955 * @param DMAx DMAx Instance
1956 * @retval State of bit (1 or 0).
1957 */
1958__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
1959{
1960 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
1961}
1962
1963/**
1964 * @brief Get Stream 5 direct mode error flag.
1965 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
1966 * @param DMAx DMAx Instance
1967 * @retval State of bit (1 or 0).
1968 */
1969__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
1970{
1971 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
1972}
1973
1974/**
1975 * @brief Get Stream 6 direct mode error flag.
1976 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
1977 * @param DMAx DMAx Instance
1978 * @retval State of bit (1 or 0).
1979 */
1980__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
1981{
1982 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
1983}
1984
1985/**
1986 * @brief Get Stream 7 direct mode error flag.
1987 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
1988 * @param DMAx DMAx Instance
1989 * @retval State of bit (1 or 0).
1990 */
1991__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
1992{
1993 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
1994}
1995
1996/**
1997 * @brief Get Stream 0 FIFO error flag.
1998 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
1999 * @param DMAx DMAx Instance
2000 * @retval State of bit (1 or 0).
2001 */
2002__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
2003{
2004 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
2005}
2006
2007/**
2008 * @brief Get Stream 1 FIFO error flag.
2009 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2010 * @param DMAx DMAx Instance
2011 * @retval State of bit (1 or 0).
2012 */
2013__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
2014{
2015 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
2016}
2017
2018/**
2019 * @brief Get Stream 2 FIFO error flag.
2020 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2021 * @param DMAx DMAx Instance
2022 * @retval State of bit (1 or 0).
2023 */
2024__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
2025{
2026 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
2027}
2028
2029/**
2030 * @brief Get Stream 3 FIFO error flag.
2031 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2032 * @param DMAx DMAx Instance
2033 * @retval State of bit (1 or 0).
2034 */
2035__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
2036{
2037 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
2038}
2039
2040/**
2041 * @brief Get Stream 4 FIFO error flag.
2042 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2043 * @param DMAx DMAx Instance
2044 * @retval State of bit (1 or 0).
2045 */
2046__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
2047{
2048 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
2049}
2050
2051/**
2052 * @brief Get Stream 5 FIFO error flag.
2053 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2054 * @param DMAx DMAx Instance
2055 * @retval State of bit (1 or 0).
2056 */
2057__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
2058{
2059 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
2060}
2061
2062/**
2063 * @brief Get Stream 6 FIFO error flag.
2064 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2065 * @param DMAx DMAx Instance
2066 * @retval State of bit (1 or 0).
2067 */
2068__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
2069{
2070 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
2071}
2072
2073/**
2074 * @brief Get Stream 7 FIFO error flag.
2075 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2076 * @param DMAx DMAx Instance
2077 * @retval State of bit (1 or 0).
2078 */
2079__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
2080{
2081 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
2082}
2083
2084/**
2085 * @brief Clear Stream 0 half transfer flag.
2086 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2087 * @param DMAx DMAx Instance
2088 * @retval None
2089 */
2090__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
2091{
2092 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
2093}
2094
2095/**
2096 * @brief Clear Stream 1 half transfer flag.
2097 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2098 * @param DMAx DMAx Instance
2099 * @retval None
2100 */
2101__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2102{
2103 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
2104}
2105
2106/**
2107 * @brief Clear Stream 2 half transfer flag.
2108 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2109 * @param DMAx DMAx Instance
2110 * @retval None
2111 */
2112__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2113{
2114 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
2115}
2116
2117/**
2118 * @brief Clear Stream 3 half transfer flag.
2119 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2120 * @param DMAx DMAx Instance
2121 * @retval None
2122 */
2123__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2124{
2125 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
2126}
2127
2128/**
2129 * @brief Clear Stream 4 half transfer flag.
2130 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2131 * @param DMAx DMAx Instance
2132 * @retval None
2133 */
2134__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2135{
2136 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
2137}
2138
2139/**
2140 * @brief Clear Stream 5 half transfer flag.
2141 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2142 * @param DMAx DMAx Instance
2143 * @retval None
2144 */
2145__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2146{
2147 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
2148}
2149
2150/**
2151 * @brief Clear Stream 6 half transfer flag.
2152 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2153 * @param DMAx DMAx Instance
2154 * @retval None
2155 */
2156__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2157{
2158 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
2159}
2160
2161/**
2162 * @brief Clear Stream 7 half transfer flag.
2163 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2164 * @param DMAx DMAx Instance
2165 * @retval None
2166 */
2167__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2168{
2169 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
2170}
2171
2172/**
2173 * @brief Clear Stream 0 transfer complete flag.
2174 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2175 * @param DMAx DMAx Instance
2176 * @retval None
2177 */
2178__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
2179{
2180 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
2181}
2182
2183/**
2184 * @brief Clear Stream 1 transfer complete flag.
2185 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2186 * @param DMAx DMAx Instance
2187 * @retval None
2188 */
2189__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2190{
2191 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
2192}
2193
2194/**
2195 * @brief Clear Stream 2 transfer complete flag.
2196 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2197 * @param DMAx DMAx Instance
2198 * @retval None
2199 */
2200__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2201{
2202 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
2203}
2204
2205/**
2206 * @brief Clear Stream 3 transfer complete flag.
2207 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2208 * @param DMAx DMAx Instance
2209 * @retval None
2210 */
2211__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2212{
2213 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
2214}
2215
2216/**
2217 * @brief Clear Stream 4 transfer complete flag.
2218 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2219 * @param DMAx DMAx Instance
2220 * @retval None
2221 */
2222__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2223{
2224 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
2225}
2226
2227/**
2228 * @brief Clear Stream 5 transfer complete flag.
2229 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2230 * @param DMAx DMAx Instance
2231 * @retval None
2232 */
2233__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2234{
2235 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
2236}
2237
2238/**
2239 * @brief Clear Stream 6 transfer complete flag.
2240 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2241 * @param DMAx DMAx Instance
2242 * @retval None
2243 */
2244__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2245{
2246 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
2247}
2248
2249/**
2250 * @brief Clear Stream 7 transfer complete flag.
2251 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2252 * @param DMAx DMAx Instance
2253 * @retval None
2254 */
2255__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2256{
2257 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
2258}
2259
2260/**
2261 * @brief Clear Stream 0 transfer error flag.
2262 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2263 * @param DMAx DMAx Instance
2264 * @retval None
2265 */
2266__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
2267{
2268 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
2269}
2270
2271/**
2272 * @brief Clear Stream 1 transfer error flag.
2273 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2274 * @param DMAx DMAx Instance
2275 * @retval None
2276 */
2277__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2278{
2279 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
2280}
2281
2282/**
2283 * @brief Clear Stream 2 transfer error flag.
2284 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2285 * @param DMAx DMAx Instance
2286 * @retval None
2287 */
2288__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2289{
2290 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
2291}
2292
2293/**
2294 * @brief Clear Stream 3 transfer error flag.
2295 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2296 * @param DMAx DMAx Instance
2297 * @retval None
2298 */
2299__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2300{
2301 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
2302}
2303
2304/**
2305 * @brief Clear Stream 4 transfer error flag.
2306 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2307 * @param DMAx DMAx Instance
2308 * @retval None
2309 */
2310__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2311{
2312 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
2313}
2314
2315/**
2316 * @brief Clear Stream 5 transfer error flag.
2317 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2318 * @param DMAx DMAx Instance
2319 * @retval None
2320 */
2321__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2322{
2323 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
2324}
2325
2326/**
2327 * @brief Clear Stream 6 transfer error flag.
2328 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2329 * @param DMAx DMAx Instance
2330 * @retval None
2331 */
2332__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2333{
2334 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
2335}
2336
2337/**
2338 * @brief Clear Stream 7 transfer error flag.
2339 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2340 * @param DMAx DMAx Instance
2341 * @retval None
2342 */
2343__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2344{
2345 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
2346}
2347
2348/**
2349 * @brief Clear Stream 0 direct mode error flag.
2350 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2351 * @param DMAx DMAx Instance
2352 * @retval None
2353 */
2354__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
2355{
2356 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
2357}
2358
2359/**
2360 * @brief Clear Stream 1 direct mode error flag.
2361 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2362 * @param DMAx DMAx Instance
2363 * @retval None
2364 */
2365__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
2366{
2367 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
2368}
2369
2370/**
2371 * @brief Clear Stream 2 direct mode error flag.
2372 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2373 * @param DMAx DMAx Instance
2374 * @retval None
2375 */
2376__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
2377{
2378 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
2379}
2380
2381/**
2382 * @brief Clear Stream 3 direct mode error flag.
2383 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2384 * @param DMAx DMAx Instance
2385 * @retval None
2386 */
2387__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
2388{
2389 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
2390}
2391
2392/**
2393 * @brief Clear Stream 4 direct mode error flag.
2394 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2395 * @param DMAx DMAx Instance
2396 * @retval None
2397 */
2398__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
2399{
2400 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
2401}
2402
2403/**
2404 * @brief Clear Stream 5 direct mode error flag.
2405 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2406 * @param DMAx DMAx Instance
2407 * @retval None
2408 */
2409__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
2410{
2411 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
2412}
2413
2414/**
2415 * @brief Clear Stream 6 direct mode error flag.
2416 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2417 * @param DMAx DMAx Instance
2418 * @retval None
2419 */
2420__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
2421{
2422 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
2423}
2424
2425/**
2426 * @brief Clear Stream 7 direct mode error flag.
2427 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2428 * @param DMAx DMAx Instance
2429 * @retval None
2430 */
2431__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
2432{
2433 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
2434}
2435
2436/**
2437 * @brief Clear Stream 0 FIFO error flag.
2438 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2439 * @param DMAx DMAx Instance
2440 * @retval None
2441 */
2442__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
2443{
2444 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
2445}
2446
2447/**
2448 * @brief Clear Stream 1 FIFO error flag.
2449 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2450 * @param DMAx DMAx Instance
2451 * @retval None
2452 */
2453__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
2454{
2455 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
2456}
2457
2458/**
2459 * @brief Clear Stream 2 FIFO error flag.
2460 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2461 * @param DMAx DMAx Instance
2462 * @retval None
2463 */
2464__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
2465{
2466 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
2467}
2468
2469/**
2470 * @brief Clear Stream 3 FIFO error flag.
2471 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2472 * @param DMAx DMAx Instance
2473 * @retval None
2474 */
2475__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
2476{
2477 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
2478}
2479
2480/**
2481 * @brief Clear Stream 4 FIFO error flag.
2482 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2483 * @param DMAx DMAx Instance
2484 * @retval None
2485 */
2486__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
2487{
2488 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
2489}
2490
2491/**
2492 * @brief Clear Stream 5 FIFO error flag.
2493 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2494 * @param DMAx DMAx Instance
2495 * @retval None
2496 */
2497__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
2498{
2499 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
2500}
2501
2502/**
2503 * @brief Clear Stream 6 FIFO error flag.
2504 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2505 * @param DMAx DMAx Instance
2506 * @retval None
2507 */
2508__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
2509{
2510 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
2511}
2512
2513/**
2514 * @brief Clear Stream 7 FIFO error flag.
2515 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2516 * @param DMAx DMAx Instance
2517 * @retval None
2518 */
2519__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
2520{
2521 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
2522}
2523
2524/**
2525 * @}
2526 */
2527
2528/** @defgroup DMA_LL_EF_IT_Management IT_Management
2529 * @{
2530 */
2531
2532/**
2533 * @brief Enable Half transfer interrupt.
2534 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2535 * @param DMAx DMAx Instance
2536 * @param Stream This parameter can be one of the following values:
2537 * @arg @ref LL_DMA_STREAM_0
2538 * @arg @ref LL_DMA_STREAM_1
2539 * @arg @ref LL_DMA_STREAM_2
2540 * @arg @ref LL_DMA_STREAM_3
2541 * @arg @ref LL_DMA_STREAM_4
2542 * @arg @ref LL_DMA_STREAM_5
2543 * @arg @ref LL_DMA_STREAM_6
2544 * @arg @ref LL_DMA_STREAM_7
2545 * @retval None
2546 */
2547__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2548{
2549 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2550}
2551
2552/**
2553 * @brief Enable Transfer error interrupt.
2554 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2555 * @param DMAx DMAx Instance
2556 * @param Stream This parameter can be one of the following values:
2557 * @arg @ref LL_DMA_STREAM_0
2558 * @arg @ref LL_DMA_STREAM_1
2559 * @arg @ref LL_DMA_STREAM_2
2560 * @arg @ref LL_DMA_STREAM_3
2561 * @arg @ref LL_DMA_STREAM_4
2562 * @arg @ref LL_DMA_STREAM_5
2563 * @arg @ref LL_DMA_STREAM_6
2564 * @arg @ref LL_DMA_STREAM_7
2565 * @retval None
2566 */
2567__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2568{
2569 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2570}
2571
2572/**
2573 * @brief Enable Transfer complete interrupt.
2574 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2575 * @param DMAx DMAx Instance
2576 * @param Stream This parameter can be one of the following values:
2577 * @arg @ref LL_DMA_STREAM_0
2578 * @arg @ref LL_DMA_STREAM_1
2579 * @arg @ref LL_DMA_STREAM_2
2580 * @arg @ref LL_DMA_STREAM_3
2581 * @arg @ref LL_DMA_STREAM_4
2582 * @arg @ref LL_DMA_STREAM_5
2583 * @arg @ref LL_DMA_STREAM_6
2584 * @arg @ref LL_DMA_STREAM_7
2585 * @retval None
2586 */
2587__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2588{
2589 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2590}
2591
2592/**
2593 * @brief Enable Direct mode error interrupt.
2594 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2595 * @param DMAx DMAx Instance
2596 * @param Stream This parameter can be one of the following values:
2597 * @arg @ref LL_DMA_STREAM_0
2598 * @arg @ref LL_DMA_STREAM_1
2599 * @arg @ref LL_DMA_STREAM_2
2600 * @arg @ref LL_DMA_STREAM_3
2601 * @arg @ref LL_DMA_STREAM_4
2602 * @arg @ref LL_DMA_STREAM_5
2603 * @arg @ref LL_DMA_STREAM_6
2604 * @arg @ref LL_DMA_STREAM_7
2605 * @retval None
2606 */
2607__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2608{
2609 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2610}
2611
2612/**
2613 * @brief Enable FIFO error interrupt.
2614 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
2615 * @param DMAx DMAx Instance
2616 * @param Stream This parameter can be one of the following values:
2617 * @arg @ref LL_DMA_STREAM_0
2618 * @arg @ref LL_DMA_STREAM_1
2619 * @arg @ref LL_DMA_STREAM_2
2620 * @arg @ref LL_DMA_STREAM_3
2621 * @arg @ref LL_DMA_STREAM_4
2622 * @arg @ref LL_DMA_STREAM_5
2623 * @arg @ref LL_DMA_STREAM_6
2624 * @arg @ref LL_DMA_STREAM_7
2625 * @retval None
2626 */
2627__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2628{
2629 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2630}
2631
2632/**
2633 * @brief Disable Half transfer interrupt.
2634 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
2635 * @param DMAx DMAx Instance
2636 * @param Stream This parameter can be one of the following values:
2637 * @arg @ref LL_DMA_STREAM_0
2638 * @arg @ref LL_DMA_STREAM_1
2639 * @arg @ref LL_DMA_STREAM_2
2640 * @arg @ref LL_DMA_STREAM_3
2641 * @arg @ref LL_DMA_STREAM_4
2642 * @arg @ref LL_DMA_STREAM_5
2643 * @arg @ref LL_DMA_STREAM_6
2644 * @arg @ref LL_DMA_STREAM_7
2645 * @retval None
2646 */
2647__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2648{
2649 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2650}
2651
2652/**
2653 * @brief Disable Transfer error interrupt.
2654 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
2655 * @param DMAx DMAx Instance
2656 * @param Stream This parameter can be one of the following values:
2657 * @arg @ref LL_DMA_STREAM_0
2658 * @arg @ref LL_DMA_STREAM_1
2659 * @arg @ref LL_DMA_STREAM_2
2660 * @arg @ref LL_DMA_STREAM_3
2661 * @arg @ref LL_DMA_STREAM_4
2662 * @arg @ref LL_DMA_STREAM_5
2663 * @arg @ref LL_DMA_STREAM_6
2664 * @arg @ref LL_DMA_STREAM_7
2665 * @retval None
2666 */
2667__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2668{
2669 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2670}
2671
2672/**
2673 * @brief Disable Transfer complete interrupt.
2674 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
2675 * @param DMAx DMAx Instance
2676 * @param Stream This parameter can be one of the following values:
2677 * @arg @ref LL_DMA_STREAM_0
2678 * @arg @ref LL_DMA_STREAM_1
2679 * @arg @ref LL_DMA_STREAM_2
2680 * @arg @ref LL_DMA_STREAM_3
2681 * @arg @ref LL_DMA_STREAM_4
2682 * @arg @ref LL_DMA_STREAM_5
2683 * @arg @ref LL_DMA_STREAM_6
2684 * @arg @ref LL_DMA_STREAM_7
2685 * @retval None
2686 */
2687__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2688{
2689 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2690}
2691
2692/**
2693 * @brief Disable Direct mode error interrupt.
2694 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
2695 * @param DMAx DMAx Instance
2696 * @param Stream This parameter can be one of the following values:
2697 * @arg @ref LL_DMA_STREAM_0
2698 * @arg @ref LL_DMA_STREAM_1
2699 * @arg @ref LL_DMA_STREAM_2
2700 * @arg @ref LL_DMA_STREAM_3
2701 * @arg @ref LL_DMA_STREAM_4
2702 * @arg @ref LL_DMA_STREAM_5
2703 * @arg @ref LL_DMA_STREAM_6
2704 * @arg @ref LL_DMA_STREAM_7
2705 * @retval None
2706 */
2707__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2708{
2709 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2710}
2711
2712/**
2713 * @brief Disable FIFO error interrupt.
2714 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
2715 * @param DMAx DMAx Instance
2716 * @param Stream This parameter can be one of the following values:
2717 * @arg @ref LL_DMA_STREAM_0
2718 * @arg @ref LL_DMA_STREAM_1
2719 * @arg @ref LL_DMA_STREAM_2
2720 * @arg @ref LL_DMA_STREAM_3
2721 * @arg @ref LL_DMA_STREAM_4
2722 * @arg @ref LL_DMA_STREAM_5
2723 * @arg @ref LL_DMA_STREAM_6
2724 * @arg @ref LL_DMA_STREAM_7
2725 * @retval None
2726 */
2727__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2728{
2729 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2730}
2731
2732/**
2733 * @brief Check if Half transfer interrup is enabled.
2734 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
2735 * @param DMAx DMAx Instance
2736 * @param Stream This parameter can be one of the following values:
2737 * @arg @ref LL_DMA_STREAM_0
2738 * @arg @ref LL_DMA_STREAM_1
2739 * @arg @ref LL_DMA_STREAM_2
2740 * @arg @ref LL_DMA_STREAM_3
2741 * @arg @ref LL_DMA_STREAM_4
2742 * @arg @ref LL_DMA_STREAM_5
2743 * @arg @ref LL_DMA_STREAM_6
2744 * @arg @ref LL_DMA_STREAM_7
2745 * @retval State of bit (1 or 0).
2746 */
2747__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2748{
2749 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
2750}
2751
2752/**
2753 * @brief Check if Transfer error nterrup is enabled.
2754 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
2755 * @param DMAx DMAx Instance
2756 * @param Stream This parameter can be one of the following values:
2757 * @arg @ref LL_DMA_STREAM_0
2758 * @arg @ref LL_DMA_STREAM_1
2759 * @arg @ref LL_DMA_STREAM_2
2760 * @arg @ref LL_DMA_STREAM_3
2761 * @arg @ref LL_DMA_STREAM_4
2762 * @arg @ref LL_DMA_STREAM_5
2763 * @arg @ref LL_DMA_STREAM_6
2764 * @arg @ref LL_DMA_STREAM_7
2765 * @retval State of bit (1 or 0).
2766 */
2767__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2768{
2769 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
2770}
2771
2772/**
2773 * @brief Check if Transfer complete interrup is enabled.
2774 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
2775 * @param DMAx DMAx Instance
2776 * @param Stream This parameter can be one of the following values:
2777 * @arg @ref LL_DMA_STREAM_0
2778 * @arg @ref LL_DMA_STREAM_1
2779 * @arg @ref LL_DMA_STREAM_2
2780 * @arg @ref LL_DMA_STREAM_3
2781 * @arg @ref LL_DMA_STREAM_4
2782 * @arg @ref LL_DMA_STREAM_5
2783 * @arg @ref LL_DMA_STREAM_6
2784 * @arg @ref LL_DMA_STREAM_7
2785 * @retval State of bit (1 or 0).
2786 */
2787__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2788{
2789 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
2790}
2791
2792/**
2793 * @brief Check if Direct mode error interrupt is enabled.
2794 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
2795 * @param DMAx DMAx Instance
2796 * @param Stream This parameter can be one of the following values:
2797 * @arg @ref LL_DMA_STREAM_0
2798 * @arg @ref LL_DMA_STREAM_1
2799 * @arg @ref LL_DMA_STREAM_2
2800 * @arg @ref LL_DMA_STREAM_3
2801 * @arg @ref LL_DMA_STREAM_4
2802 * @arg @ref LL_DMA_STREAM_5
2803 * @arg @ref LL_DMA_STREAM_6
2804 * @arg @ref LL_DMA_STREAM_7
2805 * @retval State of bit (1 or 0).
2806 */
2807__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2808{
2809 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
2810}
2811
2812/**
2813 * @brief Check if FIFO error interrup is enabled.
2814 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
2815 * @param DMAx DMAx Instance
2816 * @param Stream This parameter can be one of the following values:
2817 * @arg @ref LL_DMA_STREAM_0
2818 * @arg @ref LL_DMA_STREAM_1
2819 * @arg @ref LL_DMA_STREAM_2
2820 * @arg @ref LL_DMA_STREAM_3
2821 * @arg @ref LL_DMA_STREAM_4
2822 * @arg @ref LL_DMA_STREAM_5
2823 * @arg @ref LL_DMA_STREAM_6
2824 * @arg @ref LL_DMA_STREAM_7
2825 * @retval State of bit (1 or 0).
2826 */
2827__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2828{
2829 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
2830}
2831
2832/**
2833 * @}
2834 */
2835
2836#if defined(USE_FULL_LL_DRIVER)
2837/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2838 * @{
2839 */
2840
2841uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
2842uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
2843void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2844
2845/**
2846 * @}
2847 */
2848#endif /* USE_FULL_LL_DRIVER */
2849
2850/**
2851 * @}
2852 */
2853
2854/**
2855 * @}
2856 */
2857
2858#endif /* DMA1 || DMA2 */
2859
2860/**
2861 * @}
2862 */
2863
2864#ifdef __cplusplus
2865}
2866#endif
2867
2868#endif /* __STM32F4xx_LL_DMA_H */
2869
2870/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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