source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h

Last change on this file was 1, checked in by AlexLir, 4 years ago
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @brief Header file of DMA2D LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef STM32F4xx_LL_DMA2D_H
22#define STM32F4xx_LL_DMA2D_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f4xx.h"
30
31/** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35#if defined (DMA2D)
36
37/** @defgroup DMA2D_LL DMA2D
38 * @{
39 */
40
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43/* Private constants ---------------------------------------------------------*/
44/* Private macros ------------------------------------------------------------*/
45#if defined(USE_FULL_LL_DRIVER)
46/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
47 * @{
48 */
49
50/**
51 * @}
52 */
53#endif /*USE_FULL_LL_DRIVER*/
54
55/* Exported types ------------------------------------------------------------*/
56#if defined(USE_FULL_LL_DRIVER)
57/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
58 * @{
59 */
60
61/**
62 * @brief LL DMA2D Init Structure Definition
63 */
64typedef struct
65{
66 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
67 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
68
69 This parameter can be modified afterwards,
70 using unitary function @ref LL_DMA2D_SetMode(). */
71
72 uint32_t ColorMode; /*!< Specifies the color format of the output image.
73 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
74
75 This parameter can be modified afterwards using,
76 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
77
78 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
79 - This parameter must be a number between:
80 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
81 - This parameter must be a number between:
82 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
83 - This parameter must be a number between:
84 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
85 - This parameter must be a number between:
86 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
87 - This parameter must be a number between:
88 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
89
90 This parameter can be modified afterwards,
91 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
92 function @ref LL_DMA2D_ConfigOutputColor(). */
93
94 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
95 - This parameter must be a number between:
96 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
97 - This parameter must be a number between:
98 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
99 - This parameter must be a number between:
100 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
101 - This parameter must be a number between:
102 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
103 - This parameter must be a number between:
104 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
105
106 This parameter can be modified afterwards
107 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
108 function @ref LL_DMA2D_ConfigOutputColor(). */
109
110 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
111 - This parameter must be a number between:
112 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
113 - This parameter must be a number between:
114 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
115 - This parameter must be a number between:
116 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
117 - This parameter must be a number between:
118 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
119 - This parameter must be a number between:
120 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
121
122 This parameter can be modified afterwards
123 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
124 function @ref LL_DMA2D_ConfigOutputColor(). */
125
126 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
127 - This parameter must be a number between:
128 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
129 - This parameter must be a number between:
130 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
131 - This parameter must be a number between:
132 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
133 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
134
135 This parameter can be modified afterwards using,
136 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
137 function @ref LL_DMA2D_ConfigOutputColor(). */
138
139 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
140 - This parameter must be a number between:
141 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
142
143 This parameter can be modified afterwards,
144 using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
145
146
147
148 uint32_t LineOffset; /*!< Specifies the output line offset value.
149 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
150
151 This parameter can be modified afterwards,
152 using unitary function @ref LL_DMA2D_SetLineOffset(). */
153
154 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
155 - This parameter must be a number between:
156 Min_Data = 0x0000 and Max_Data = 0xFFFF.
157
158 This parameter can be modified afterwards,
159 using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
160
161 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
162 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
163
164 This parameter can be modified afterwards using,
165 unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
166
167
168} LL_DMA2D_InitTypeDef;
169
170/**
171 * @brief LL DMA2D Layer Configuration Structure Definition
172 */
173typedef struct
174{
175 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
176 - This parameter must be a number between:
177 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
178
179 This parameter can be modified afterwards using unitary functions
180 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
181 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
182
183 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
184 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
185
186 This parameter can be modified afterwards using unitary functions
187 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
188 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
189
190 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
191 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
192
193 This parameter can be modified afterwards using unitary functions
194 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
195 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
196
197 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
198 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
199
200 This parameter can be modified afterwards using unitary functions
201 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
202 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
203
204 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
205 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
206
207 This parameter can be modified afterwards using unitary functions
208 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
209 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
210
211 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
212 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
213
214 This parameter can be modified afterwards using unitary functions
215 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
216 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
217
218 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
219 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
220
221 This parameter can be modified afterwards using unitary functions
222 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
223 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
224
225 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
226 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
227
228 This parameter can be modified afterwards using unitary functions
229 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
230 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
231
232 uint32_t Green; /*!< Specifies the foreground or background Green color value.
233 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
234
235 This parameter can be modified afterwards using unitary functions
236 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
237 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
238
239 uint32_t Red; /*!< Specifies the foreground or background Red color value.
240 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
241
242 This parameter can be modified afterwards using unitary functions
243 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
244 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
245
246 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
247 - This parameter must be a number between:
248 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
249
250 This parameter can be modified afterwards using unitary functions
251 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
252 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
253
254
255
256} LL_DMA2D_LayerCfgTypeDef;
257
258/**
259 * @brief LL DMA2D Output Color Structure Definition
260 */
261typedef struct
262{
263 uint32_t ColorMode; /*!< Specifies the color format of the output image.
264 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
265
266 This parameter can be modified afterwards using
267 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
268
269 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
270 - This parameter must be a number between:
271 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
272 - This parameter must be a number between:
273 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
274 - This parameter must be a number between:
275 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
276 - This parameter must be a number between:
277 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
278 - This parameter must be a number between:
279 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
280
281 This parameter can be modified afterwards using,
282 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
283 function @ref LL_DMA2D_ConfigOutputColor(). */
284
285 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
286 - This parameter must be a number between:
287 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
288 - This parameter must be a number between
289 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
290 - This parameter must be a number between:
291 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
292 - This parameter must be a number between:
293 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
294 - This parameter must be a number between:
295 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
296
297 This parameter can be modified afterwards,
298 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
299 function @ref LL_DMA2D_ConfigOutputColor(). */
300
301 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
302 - This parameter must be a number between:
303 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
304 - This parameter must be a number between:
305 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
306 - This parameter must be a number between:
307 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
308 - This parameter must be a number between:
309 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
310 - This parameter must be a number between:
311 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
312
313 This parameter can be modified afterwards,
314 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
315 function @ref LL_DMA2D_ConfigOutputColor(). */
316
317 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
318 - This parameter must be a number between:
319 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
320 - This parameter must be a number between:
321 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
322 - This parameter must be a number between:
323 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
324 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
325
326 This parameter can be modified afterwards,
327 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
328 function @ref LL_DMA2D_ConfigOutputColor(). */
329
330} LL_DMA2D_ColorTypeDef;
331
332/**
333 * @}
334 */
335#endif /* USE_FULL_LL_DRIVER */
336
337/* Exported constants --------------------------------------------------------*/
338/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
339 * @{
340 */
341
342/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
343 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
344 * @{
345 */
346#define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
347#define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
348#define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
349#define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
350#define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
351#define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
352/**
353 * @}
354 */
355
356/** @defgroup DMA2D_LL_EC_IT IT Defines
357 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
358 * @{
359 */
360#define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
361#define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
362#define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
363#define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
364#define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
365#define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
366/**
367 * @}
368 */
369
370/** @defgroup DMA2D_LL_EC_MODE Mode
371 * @{
372 */
373#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
374#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
375#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
376#define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
377/**
378 * @}
379 */
380
381/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
382 * @{
383 */
384#define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
385#define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
386#define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
387#define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
388#define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
389/**
390 * @}
391 */
392
393/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
394 * @{
395 */
396#define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
397#define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
398#define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
399#define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
400#define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
401#define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
402#define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
403#define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
404#define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
405#define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
406#define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
407/**
408 * @}
409 */
410
411/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
412 * @{
413 */
414#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
415#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
416 programmed alpha value */
417#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
418 programmed alpha value with,
419 original alpha channel value */
420/**
421 * @}
422 */
423
424
425
426
427/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
428 * @{
429 */
430#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
431#define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
432/**
433 * @}
434 */
435
436
437/**
438 * @}
439 */
440
441/* Exported macro ------------------------------------------------------------*/
442/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
443 * @{
444 */
445
446/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
447 * @{
448 */
449
450/**
451 * @brief Write a value in DMA2D register.
452 * @param __INSTANCE__ DMA2D Instance
453 * @param __REG__ Register to be written
454 * @param __VALUE__ Value to be written in the register
455 * @retval None
456 */
457#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
458
459/**
460 * @brief Read a value in DMA2D register.
461 * @param __INSTANCE__ DMA2D Instance
462 * @param __REG__ Register to be read
463 * @retval Register value
464 */
465#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
466/**
467 * @}
468 */
469
470/**
471 * @}
472 */
473
474/* Exported functions --------------------------------------------------------*/
475/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
476 * @{
477 */
478
479/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
480 * @{
481 */
482
483/**
484 * @brief Start a DMA2D transfer.
485 * @rmtoll CR START LL_DMA2D_Start
486 * @param DMA2Dx DMA2D Instance
487 * @retval None
488 */
489__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
490{
491 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
492}
493
494/**
495 * @brief Indicate if a DMA2D transfer is ongoing.
496 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
497 * @param DMA2Dx DMA2D Instance
498 * @retval State of bit (1 or 0).
499 */
500__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
501{
502 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
503}
504
505/**
506 * @brief Suspend DMA2D transfer.
507 * @note This API can be used to suspend automatic foreground or background CLUT loading.
508 * @rmtoll CR SUSP LL_DMA2D_Suspend
509 * @param DMA2Dx DMA2D Instance
510 * @retval None
511 */
512__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
513{
514 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
515}
516
517/**
518 * @brief Resume DMA2D transfer.
519 * @note This API can be used to resume automatic foreground or background CLUT loading.
520 * @rmtoll CR SUSP LL_DMA2D_Resume
521 * @param DMA2Dx DMA2D Instance
522 * @retval None
523 */
524__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
525{
526 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
527}
528
529/**
530 * @brief Indicate if DMA2D transfer is suspended.
531 * @note This API can be used to indicate whether or not automatic foreground or
532 * background CLUT loading is suspended.
533 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
534 * @param DMA2Dx DMA2D Instance
535 * @retval State of bit (1 or 0).
536 */
537__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
538{
539 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
540}
541
542/**
543 * @brief Abort DMA2D transfer.
544 * @note This API can be used to abort automatic foreground or background CLUT loading.
545 * @rmtoll CR ABORT LL_DMA2D_Abort
546 * @param DMA2Dx DMA2D Instance
547 * @retval None
548 */
549__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
550{
551 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
552}
553
554/**
555 * @brief Indicate if DMA2D transfer is aborted.
556 * @note This API can be used to indicate whether or not automatic foreground or
557 * background CLUT loading is aborted.
558 * @rmtoll CR ABORT LL_DMA2D_IsAborted
559 * @param DMA2Dx DMA2D Instance
560 * @retval State of bit (1 or 0).
561 */
562__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
563{
564 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
565}
566
567/**
568 * @brief Set DMA2D mode.
569 * @rmtoll CR MODE LL_DMA2D_SetMode
570 * @param DMA2Dx DMA2D Instance
571 * @param Mode This parameter can be one of the following values:
572 * @arg @ref LL_DMA2D_MODE_M2M
573 * @arg @ref LL_DMA2D_MODE_M2M_PFC
574 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
575 * @arg @ref LL_DMA2D_MODE_R2M
576 * @retval None
577 */
578__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
579{
580 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
581}
582
583/**
584 * @brief Return DMA2D mode
585 * @rmtoll CR MODE LL_DMA2D_GetMode
586 * @param DMA2Dx DMA2D Instance
587 * @retval Returned value can be one of the following values:
588 * @arg @ref LL_DMA2D_MODE_M2M
589 * @arg @ref LL_DMA2D_MODE_M2M_PFC
590 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
591 * @arg @ref LL_DMA2D_MODE_R2M
592 */
593__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
594{
595 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
596}
597
598/**
599 * @brief Set DMA2D output color mode.
600 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
601 * @param DMA2Dx DMA2D Instance
602 * @param ColorMode This parameter can be one of the following values:
603 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
604 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
605 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
606 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
607 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
608 * @retval None
609 */
610__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
611{
612 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
613}
614
615/**
616 * @brief Return DMA2D output color mode.
617 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
618 * @param DMA2Dx DMA2D Instance
619 * @retval Returned value can be one of the following values:
620 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
621 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
622 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
623 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
624 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
625 */
626__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
627{
628 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
629}
630
631
632
633
634/**
635 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
636 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
637 * @param DMA2Dx DMA2D Instance
638 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
639 * @retval None
640 */
641__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
642{
643 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
644}
645
646/**
647 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
648 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
649 * @param DMA2Dx DMA2D Instance
650 * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
651 */
652__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
653{
654 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
655}
656
657/**
658 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
659 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
660 * @param DMA2Dx DMA2D Instance
661 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
662 * @retval None
663 */
664__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
665{
666 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
667}
668
669/**
670 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
671 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
672 * @param DMA2Dx DMA2D Instance
673 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
674 */
675__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
676{
677 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
678}
679
680/**
681 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
682 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
683 * @param DMA2Dx DMA2D Instance
684 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
685 * @retval None
686 */
687__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
688{
689 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
690}
691
692/**
693 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
694 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
695 * @param DMA2Dx DMA2D Instance
696 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
697 */
698__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
699{
700 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
701}
702
703/**
704 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
705 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
706 * @param DMA2Dx DMA2D Instance
707 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
708 * @retval None
709 */
710__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
711{
712 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
713}
714
715/**
716 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
717 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
718 * @param DMA2Dx DMA2D Instance
719 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
720 */
721__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
722{
723 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
724}
725
726/**
727 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
728 * @note Output color format depends on output color mode, ARGB8888, RGB888,
729 * RGB565, ARGB1555 or ARGB4444.
730 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
731 * with respect to color mode is not done by the user code.
732 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
733 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
734 * OCOLR RED LL_DMA2D_SetOutputColor\n
735 * OCOLR ALPHA LL_DMA2D_SetOutputColor
736 * @param DMA2Dx DMA2D Instance
737 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
738 * @retval None
739 */
740__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
741{
742 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
743 OutputColor);
744}
745
746/**
747 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
748 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
749 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
750 * as set by @ref LL_DMA2D_SetOutputColorMode.
751 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
752 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
753 * OCOLR RED LL_DMA2D_GetOutputColor\n
754 * OCOLR ALPHA LL_DMA2D_GetOutputColor
755 * @param DMA2Dx DMA2D Instance
756 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
757 */
758__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
759{
760 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
761 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
762}
763
764/**
765 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
766 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
767 * @param DMA2Dx DMA2D Instance
768 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
769 * @retval None
770 */
771__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
772{
773 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
774}
775
776/**
777 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
778 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
779 * @param DMA2Dx DMA2D Instance
780 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
781 */
782__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
783{
784 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
785}
786
787/**
788 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
789 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
790 * @param DMA2Dx DMA2D Instance
791 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
792 * @retval None
793 */
794__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
795{
796 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
797}
798
799/**
800 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
801 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
802 * @param DMA2Dx DMA2D Instance
803 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
804 */
805__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
806{
807 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
808}
809
810/**
811 * @brief Enable DMA2D dead time functionality.
812 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
813 * @param DMA2Dx DMA2D Instance
814 * @retval None
815 */
816__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
817{
818 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
819}
820
821/**
822 * @brief Disable DMA2D dead time functionality.
823 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
824 * @param DMA2Dx DMA2D Instance
825 * @retval None
826 */
827__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
828{
829 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
830}
831
832/**
833 * @brief Indicate if DMA2D dead time functionality is enabled.
834 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
835 * @param DMA2Dx DMA2D Instance
836 * @retval State of bit (1 or 0).
837 */
838__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
839{
840 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
841}
842
843/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
844 * @{
845 */
846
847/**
848 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
849 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
850 * @param DMA2Dx DMA2D Instance
851 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
852 * @retval None
853 */
854__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
855{
856 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
857}
858
859/**
860 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
861 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
862 * @param DMA2Dx DMA2D Instance
863 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
864 */
865__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
866{
867 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
868}
869
870/**
871 * @brief Enable DMA2D foreground CLUT loading.
872 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
873 * @param DMA2Dx DMA2D Instance
874 * @retval None
875 */
876__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
877{
878 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
879}
880
881/**
882 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
883 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
884 * @param DMA2Dx DMA2D Instance
885 * @retval State of bit (1 or 0).
886 */
887__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
888{
889 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
890}
891
892/**
893 * @brief Set DMA2D foreground color mode.
894 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
895 * @param DMA2Dx DMA2D Instance
896 * @param ColorMode This parameter can be one of the following values:
897 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
898 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
899 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
900 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
901 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
902 * @arg @ref LL_DMA2D_INPUT_MODE_L8
903 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
904 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
905 * @arg @ref LL_DMA2D_INPUT_MODE_L4
906 * @arg @ref LL_DMA2D_INPUT_MODE_A8
907 * @arg @ref LL_DMA2D_INPUT_MODE_A4
908 * @retval None
909 */
910__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
911{
912 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
913}
914
915/**
916 * @brief Return DMA2D foreground color mode.
917 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
918 * @param DMA2Dx DMA2D Instance
919 * @retval Returned value can be one of the following values:
920 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
921 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
922 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
923 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
924 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
925 * @arg @ref LL_DMA2D_INPUT_MODE_L8
926 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
927 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
928 * @arg @ref LL_DMA2D_INPUT_MODE_L4
929 * @arg @ref LL_DMA2D_INPUT_MODE_A8
930 * @arg @ref LL_DMA2D_INPUT_MODE_A4
931 */
932__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
933{
934 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
935}
936
937/**
938 * @brief Set DMA2D foreground alpha mode.
939 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
940 * @param DMA2Dx DMA2D Instance
941 * @param AphaMode This parameter can be one of the following values:
942 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
943 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
944 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
945 * @retval None
946 */
947__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
948{
949 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
950}
951
952/**
953 * @brief Return DMA2D foreground alpha mode.
954 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
955 * @param DMA2Dx DMA2D Instance
956 * @retval Returned value can be one of the following values:
957 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
958 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
959 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
960 */
961__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
962{
963 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
964}
965
966/**
967 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
968 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
969 * @param DMA2Dx DMA2D Instance
970 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
971 * @retval None
972 */
973__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
974{
975 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
976}
977
978/**
979 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
980 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
981 * @param DMA2Dx DMA2D Instance
982 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
983 */
984__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
985{
986 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
987}
988
989
990/**
991 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
992 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
993 * @param DMA2Dx DMA2D Instance
994 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
995 * @retval None
996 */
997__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
998{
999 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1000}
1001
1002/**
1003 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1004 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
1005 * @param DMA2Dx DMA2D Instance
1006 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
1007 */
1008__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1009{
1010 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1011}
1012
1013/**
1014 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
1015 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
1016 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
1017 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
1018 * @param DMA2Dx DMA2D Instance
1019 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1020 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1021 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1022 * @retval None
1023 */
1024__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1025{
1026 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1027 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1028}
1029
1030/**
1031 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1032 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
1033 * @param DMA2Dx DMA2D Instance
1034 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1035 * @retval None
1036 */
1037__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1038{
1039 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1040}
1041
1042/**
1043 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1044 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
1045 * @param DMA2Dx DMA2D Instance
1046 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1047 */
1048__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1049{
1050 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1051}
1052
1053/**
1054 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1055 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
1056 * @param DMA2Dx DMA2D Instance
1057 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1058 * @retval None
1059 */
1060__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1061{
1062 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1063}
1064
1065/**
1066 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1067 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1068 * @param DMA2Dx DMA2D Instance
1069 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1070 */
1071__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1072{
1073 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1074}
1075
1076/**
1077 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1078 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1079 * @param DMA2Dx DMA2D Instance
1080 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1081 * @retval None
1082 */
1083__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1084{
1085 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1086}
1087
1088/**
1089 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1090 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1091 * @param DMA2Dx DMA2D Instance
1092 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1093 */
1094__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1095{
1096 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1097}
1098
1099/**
1100 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1101 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1102 * @param DMA2Dx DMA2D Instance
1103 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1104 * @retval None
1105 */
1106__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1107{
1108 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1109}
1110
1111/**
1112 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1113 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1114 * @param DMA2Dx DMA2D Instance
1115 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1116 */
1117__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1118{
1119 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1120}
1121
1122/**
1123 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1124 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1125 * @param DMA2Dx DMA2D Instance
1126 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1127 * @retval None
1128 */
1129__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1130{
1131 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1132}
1133
1134/**
1135 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1136 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1137 * @param DMA2Dx DMA2D Instance
1138 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1139 */
1140__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1141{
1142 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1143}
1144
1145/**
1146 * @brief Set DMA2D foreground CLUT color mode.
1147 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1148 * @param DMA2Dx DMA2D Instance
1149 * @param CLUTColorMode This parameter can be one of the following values:
1150 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1151 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1152 * @retval None
1153 */
1154__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1155{
1156 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1157}
1158
1159/**
1160 * @brief Return DMA2D foreground CLUT color mode.
1161 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1162 * @param DMA2Dx DMA2D Instance
1163 * @retval Returned value can be one of the following values:
1164 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1165 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1166 */
1167__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1168{
1169 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1170}
1171
1172/**
1173 * @}
1174 */
1175
1176/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1177 * @{
1178 */
1179
1180/**
1181 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1182 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1183 * @param DMA2Dx DMA2D Instance
1184 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1185 * @retval None
1186 */
1187__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1188{
1189 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1190}
1191
1192/**
1193 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1194 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1195 * @param DMA2Dx DMA2D Instance
1196 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1197 */
1198__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1199{
1200 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1201}
1202
1203/**
1204 * @brief Enable DMA2D background CLUT loading.
1205 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1206 * @param DMA2Dx DMA2D Instance
1207 * @retval None
1208 */
1209__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1210{
1211 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1212}
1213
1214/**
1215 * @brief Indicate if DMA2D background CLUT loading is enabled.
1216 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1217 * @param DMA2Dx DMA2D Instance
1218 * @retval State of bit (1 or 0).
1219 */
1220__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1221{
1222 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1223}
1224
1225/**
1226 * @brief Set DMA2D background color mode.
1227 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1228 * @param DMA2Dx DMA2D Instance
1229 * @param ColorMode This parameter can be one of the following values:
1230 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1231 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1232 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1233 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1234 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1235 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1236 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1237 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1238 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1239 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1240 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1241 * @retval None
1242 */
1243__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1244{
1245 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1246}
1247
1248/**
1249 * @brief Return DMA2D background color mode.
1250 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1251 * @param DMA2Dx DMA2D Instance
1252 * @retval Returned value can be one of the following values:
1253 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1254 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1255 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1256 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1257 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1258 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1259 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1260 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1261 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1262 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1263 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1264 */
1265__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1266{
1267 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1268}
1269
1270/**
1271 * @brief Set DMA2D background alpha mode.
1272 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1273 * @param DMA2Dx DMA2D Instance
1274 * @param AphaMode This parameter can be one of the following values:
1275 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1276 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1277 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1278 * @retval None
1279 */
1280__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1281{
1282 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1283}
1284
1285/**
1286 * @brief Return DMA2D background alpha mode.
1287 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1288 * @param DMA2Dx DMA2D Instance
1289 * @retval Returned value can be one of the following values:
1290 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1291 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1292 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1293 */
1294__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1295{
1296 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1297}
1298
1299/**
1300 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1301 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1302 * @param DMA2Dx DMA2D Instance
1303 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1304 * @retval None
1305 */
1306__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1307{
1308 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1309}
1310
1311/**
1312 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1313 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1314 * @param DMA2Dx DMA2D Instance
1315 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1316 */
1317__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1318{
1319 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1320}
1321
1322
1323/**
1324 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1325 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1326 * @param DMA2Dx DMA2D Instance
1327 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1328 * @retval None
1329 */
1330__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1331{
1332 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1333}
1334
1335/**
1336 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1337 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1338 * @param DMA2Dx DMA2D Instance
1339 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1340 */
1341__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1342{
1343 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1344}
1345
1346/**
1347 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1348 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1349 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1350 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1351 * @param DMA2Dx DMA2D Instance
1352 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1353 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1354 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1355 * @retval None
1356 */
1357__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1358{
1359 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1360 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1361}
1362
1363/**
1364 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1365 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1366 * @param DMA2Dx DMA2D Instance
1367 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1368 * @retval None
1369 */
1370__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1371{
1372 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1373}
1374
1375/**
1376 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1377 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1378 * @param DMA2Dx DMA2D Instance
1379 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1380 */
1381__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1382{
1383 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1384}
1385
1386/**
1387 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1388 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1389 * @param DMA2Dx DMA2D Instance
1390 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1391 * @retval None
1392 */
1393__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1394{
1395 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1396}
1397
1398/**
1399 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1400 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1401 * @param DMA2Dx DMA2D Instance
1402 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1403 */
1404__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1405{
1406 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1407}
1408
1409/**
1410 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1411 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1412 * @param DMA2Dx DMA2D Instance
1413 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1414 * @retval None
1415 */
1416__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1417{
1418 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1419}
1420
1421/**
1422 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1423 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1424 * @param DMA2Dx DMA2D Instance
1425 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1426 */
1427__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1428{
1429 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1430}
1431
1432/**
1433 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1434 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1435 * @param DMA2Dx DMA2D Instance
1436 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1437 * @retval None
1438 */
1439__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1440{
1441 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1442}
1443
1444/**
1445 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1446 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1447 * @param DMA2Dx DMA2D Instance
1448 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1449 */
1450__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1451{
1452 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1453}
1454
1455/**
1456 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1457 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1458 * @param DMA2Dx DMA2D Instance
1459 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1460 * @retval None
1461 */
1462__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1463{
1464 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1465}
1466
1467/**
1468 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1469 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1470 * @param DMA2Dx DMA2D Instance
1471 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1472 */
1473__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1474{
1475 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1476}
1477
1478/**
1479 * @brief Set DMA2D background CLUT color mode.
1480 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1481 * @param DMA2Dx DMA2D Instance
1482 * @param CLUTColorMode This parameter can be one of the following values:
1483 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1484 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1485 * @retval None
1486 */
1487__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1488{
1489 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1490}
1491
1492/**
1493 * @brief Return DMA2D background CLUT color mode.
1494 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1495 * @param DMA2Dx DMA2D Instance
1496 * @retval Returned value can be one of the following values:
1497 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1498 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1499 */
1500__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1501{
1502 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1503}
1504
1505/**
1506 * @}
1507 */
1508
1509/**
1510 * @}
1511 */
1512
1513
1514/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1515 * @{
1516 */
1517
1518/**
1519 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1520 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1521 * @param DMA2Dx DMA2D Instance
1522 * @retval State of bit (1 or 0).
1523 */
1524__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
1525{
1526 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1527}
1528
1529/**
1530 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1531 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1532 * @param DMA2Dx DMA2D Instance
1533 * @retval State of bit (1 or 0).
1534 */
1535__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1536{
1537 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1538}
1539
1540/**
1541 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1542 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1543 * @param DMA2Dx DMA2D Instance
1544 * @retval State of bit (1 or 0).
1545 */
1546__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1547{
1548 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1549}
1550
1551/**
1552 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1553 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1554 * @param DMA2Dx DMA2D Instance
1555 * @retval State of bit (1 or 0).
1556 */
1557__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
1558{
1559 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1560}
1561
1562/**
1563 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1564 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1565 * @param DMA2Dx DMA2D Instance
1566 * @retval State of bit (1 or 0).
1567 */
1568__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
1569{
1570 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1571}
1572
1573/**
1574 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1575 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1576 * @param DMA2Dx DMA2D Instance
1577 * @retval State of bit (1 or 0).
1578 */
1579__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
1580{
1581 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1582}
1583
1584/**
1585 * @brief Clear DMA2D Configuration Error Interrupt Flag
1586 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1587 * @param DMA2Dx DMA2D Instance
1588 * @retval None
1589 */
1590__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1591{
1592 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1593}
1594
1595/**
1596 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1597 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1598 * @param DMA2Dx DMA2D Instance
1599 * @retval None
1600 */
1601__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1602{
1603 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1604}
1605
1606/**
1607 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1608 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1609 * @param DMA2Dx DMA2D Instance
1610 * @retval None
1611 */
1612__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1613{
1614 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1615}
1616
1617/**
1618 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1619 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1620 * @param DMA2Dx DMA2D Instance
1621 * @retval None
1622 */
1623__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1624{
1625 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1626}
1627
1628/**
1629 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1630 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1631 * @param DMA2Dx DMA2D Instance
1632 * @retval None
1633 */
1634__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1635{
1636 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1637}
1638
1639/**
1640 * @brief Clear DMA2D Transfer Error Interrupt Flag
1641 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1642 * @param DMA2Dx DMA2D Instance
1643 * @retval None
1644 */
1645__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1646{
1647 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1648}
1649
1650/**
1651 * @}
1652 */
1653
1654/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1655 * @{
1656 */
1657
1658/**
1659 * @brief Enable Configuration Error Interrupt
1660 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1661 * @param DMA2Dx DMA2D Instance
1662 * @retval None
1663 */
1664__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1665{
1666 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1667}
1668
1669/**
1670 * @brief Enable CLUT Transfer Complete Interrupt
1671 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
1672 * @param DMA2Dx DMA2D Instance
1673 * @retval None
1674 */
1675__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1676{
1677 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1678}
1679
1680/**
1681 * @brief Enable CLUT Access Error Interrupt
1682 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
1683 * @param DMA2Dx DMA2D Instance
1684 * @retval None
1685 */
1686__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1687{
1688 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1689}
1690
1691/**
1692 * @brief Enable Transfer Watermark Interrupt
1693 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
1694 * @param DMA2Dx DMA2D Instance
1695 * @retval None
1696 */
1697__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
1698{
1699 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1700}
1701
1702/**
1703 * @brief Enable Transfer Complete Interrupt
1704 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
1705 * @param DMA2Dx DMA2D Instance
1706 * @retval None
1707 */
1708__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
1709{
1710 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1711}
1712
1713/**
1714 * @brief Enable Transfer Error Interrupt
1715 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
1716 * @param DMA2Dx DMA2D Instance
1717 * @retval None
1718 */
1719__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
1720{
1721 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1722}
1723
1724/**
1725 * @brief Disable Configuration Error Interrupt
1726 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
1727 * @param DMA2Dx DMA2D Instance
1728 * @retval None
1729 */
1730__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
1731{
1732 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1733}
1734
1735/**
1736 * @brief Disable CLUT Transfer Complete Interrupt
1737 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
1738 * @param DMA2Dx DMA2D Instance
1739 * @retval None
1740 */
1741__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1742{
1743 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1744}
1745
1746/**
1747 * @brief Disable CLUT Access Error Interrupt
1748 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
1749 * @param DMA2Dx DMA2D Instance
1750 * @retval None
1751 */
1752__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1753{
1754 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1755}
1756
1757/**
1758 * @brief Disable Transfer Watermark Interrupt
1759 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
1760 * @param DMA2Dx DMA2D Instance
1761 * @retval None
1762 */
1763__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
1764{
1765 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1766}
1767
1768/**
1769 * @brief Disable Transfer Complete Interrupt
1770 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
1771 * @param DMA2Dx DMA2D Instance
1772 * @retval None
1773 */
1774__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
1775{
1776 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1777}
1778
1779/**
1780 * @brief Disable Transfer Error Interrupt
1781 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
1782 * @param DMA2Dx DMA2D Instance
1783 * @retval None
1784 */
1785__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
1786{
1787 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1788}
1789
1790/**
1791 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
1792 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
1793 * @param DMA2Dx DMA2D Instance
1794 * @retval State of bit (1 or 0).
1795 */
1796__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
1797{
1798 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
1799}
1800
1801/**
1802 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
1803 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
1804 * @param DMA2Dx DMA2D Instance
1805 * @retval State of bit (1 or 0).
1806 */
1807__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
1808{
1809 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
1810}
1811
1812/**
1813 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
1814 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
1815 * @param DMA2Dx DMA2D Instance
1816 * @retval State of bit (1 or 0).
1817 */
1818__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
1819{
1820 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
1821}
1822
1823/**
1824 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
1825 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
1826 * @param DMA2Dx DMA2D Instance
1827 * @retval State of bit (1 or 0).
1828 */
1829__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
1830{
1831 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
1832}
1833
1834/**
1835 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
1836 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
1837 * @param DMA2Dx DMA2D Instance
1838 * @retval State of bit (1 or 0).
1839 */
1840__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
1841{
1842 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
1843}
1844
1845/**
1846 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
1847 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
1848 * @param DMA2Dx DMA2D Instance
1849 * @retval State of bit (1 or 0).
1850 */
1851__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
1852{
1853 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
1854}
1855
1856
1857
1858/**
1859 * @}
1860 */
1861
1862#if defined(USE_FULL_LL_DRIVER)
1863/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
1864 * @{
1865 */
1866
1867ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
1868ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
1869void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
1870void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
1871void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
1872void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
1873uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
1874uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
1875uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
1876uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
1877void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
1878
1879/**
1880 * @}
1881 */
1882#endif /* USE_FULL_LL_DRIVER */
1883
1884/**
1885 * @}
1886 */
1887
1888/**
1889 * @}
1890 */
1891
1892#endif /* defined (DMA2D) */
1893
1894/**
1895 * @}
1896 */
1897
1898#ifdef __cplusplus
1899}
1900#endif
1901
1902#endif /* STM32F4xx_LL_DMA2D_H */
1903
1904/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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