Context Navigation

stm32f4xx_ll_fmc.h

Last change on this file was 1, checked in by AlexLir, 3 years ago

File size: 60.3 KB

Line
1	/**
2	******************************************************************************
3	* @file stm32f4xx_ll_fmc.h
4	* @author MCD Application Team
5	* @brief Header file of FMC HAL module.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19
20	/* Define to prevent recursive inclusion -------------------------------------*/
21	#ifndef __STM32F4xx_LL_FMC_H
22	#define __STM32F4xx_LL_FMC_H
23
24	#ifdef __cplusplus
25	extern "C" {
26	#endif
27
28	/* Includes ------------------------------------------------------------------*/
29	#include "stm32f4xx_hal_def.h"
30
31	/** @addtogroup STM32F4xx_HAL_Driver
32	* @{
33	*/
34
35	/** @addtogroup FMC_LL
36	* @{
37	*/
38	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
39	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
40	/* Private types -------------------------------------------------------------*/
41	/** @defgroup FMC_LL_Private_Types FMC Private Types
42	* @{
43	*/
44
45	/**
46	* @brief FMC NORSRAM Configuration Structure definition
47	*/
48	typedef struct
49	{
50	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
51	This parameter can be a value of @ref FMC_NORSRAM_Bank */
52
53	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
54	multiplexed on the data bus or not.
55	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
56
57	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
58	the corresponding memory device.
59	This parameter can be a value of @ref FMC_Memory_Type */
60
61	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
62	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
63
64	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
65	valid only with synchronous burst Flash memories.
66	This parameter can be a value of @ref FMC_Burst_Access_Mode */
67
68	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
69	the Flash memory in burst mode.
70	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
71
72	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
73	memory, valid only when accessing Flash memories in burst mode.
74	This parameter can be a value of @ref FMC_Wrap_Mode
75	This mode is not available for the STM32F446/467/479xx devices */
76
77	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
78	clock cycle before the wait state or during the wait state,
79	valid only when accessing memories in burst mode.
80	This parameter can be a value of @ref FMC_Wait_Timing */
81
82	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
83	This parameter can be a value of @ref FMC_Write_Operation */
84
85	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
86	signal, valid for Flash memory access in burst mode.
87	This parameter can be a value of @ref FMC_Wait_Signal */
88
89	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
90	This parameter can be a value of @ref FMC_Extended_Mode */
91
92	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
93	valid only with asynchronous Flash memories.
94	This parameter can be a value of @ref FMC_AsynchronousWait */
95
96	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
97	This parameter can be a value of @ref FMC_Write_Burst */
98
99	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
100	This parameter is only enabled through the FMC_BCR1 register, and don't care
101	through FMC_BCR2..4 registers.
102	This parameter can be a value of @ref FMC_Continous_Clock */
103
104	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
105	This parameter is only enabled through the FMC_BCR1 register, and don't care
106	through FMC_BCR2..4 registers.
107	This parameter can be a value of @ref FMC_Write_FIFO
108	This mode is available only for the STM32F446/469/479xx devices */
109
110	uint32_t PageSize; /*!< Specifies the memory page size.
111	This parameter can be a value of @ref FMC_Page_Size */
112	}FMC_NORSRAM_InitTypeDef;
113
114	/**
115	* @brief FMC NORSRAM Timing parameters structure definition
116	*/
117	typedef struct
118	{
119	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
120	the duration of the address setup time.
121	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
122	@note This parameter is not used with synchronous NOR Flash memories. */
123
124	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
125	the duration of the address hold time.
126	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
127	@note This parameter is not used with synchronous NOR Flash memories. */
128
129	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
130	the duration of the data setup time.
131	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
132	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
133	NOR Flash memories. */
134
135	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
136	the duration of the bus turnaround.
137	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
138	@note This parameter is only used for multiplexed NOR Flash memories. */
139
140	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
141	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
142	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
143	accesses. */
144
145	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
146	to the memory before getting the first data.
147	The parameter value depends on the memory type as shown below:
148	- It must be set to 0 in case of a CRAM
149	- It is don't care in asynchronous NOR, SRAM or ROM accesses
150	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
151	with synchronous burst mode enable */
152
153	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
154	This parameter can be a value of @ref FMC_Access_Mode */
155	}FMC_NORSRAM_TimingTypeDef;
156
157	/**
158	* @brief FMC NAND Configuration Structure definition
159	*/
160	typedef struct
161	{
162	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
163	This parameter can be a value of @ref FMC_NAND_Bank */
164
165	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
166	This parameter can be any value of @ref FMC_Wait_feature */
167
168	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
169	This parameter can be any value of @ref FMC_NAND_Data_Width */
170
171	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
172	This parameter can be any value of @ref FMC_ECC */
173
174	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
175	This parameter can be any value of @ref FMC_ECC_Page_Size */
176
177	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
178	delay between CLE low and RE low.
179	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
180
181	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
182	delay between ALE low and RE low.
183	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
184	}FMC_NAND_InitTypeDef;
185
186	/**
187	* @brief FMC NAND/PCCARD Timing parameters structure definition
188	*/
189	typedef struct
190	{
191	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
192	the command assertion for NAND-Flash read or write access
193	to common/Attribute or I/O memory space (depending on
194	the memory space timing to be configured).
195	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
196
197	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
198	command for NAND-Flash read or write access to
199	common/Attribute or I/O memory space (depending on the
200	memory space timing to be configured).
201	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
202
203	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
204	(and data for write access) after the command de-assertion
205	for NAND-Flash read or write access to common/Attribute
206	or I/O memory space (depending on the memory space timing
207	to be configured).
208	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
209
210	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
211	data bus is kept in HiZ after the start of a NAND-Flash
212	write access to common/Attribute or I/O memory space (depending
213	on the memory space timing to be configured).
214	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
215	}FMC_NAND_PCC_TimingTypeDef;
216
217	/**
218	* @brief FMC NAND Configuration Structure definition
219	*/
220	typedef struct
221	{
222	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
223	This parameter can be any value of @ref FMC_Wait_feature */
224
225	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
226	delay between CLE low and RE low.
227	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
228
229	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
230	delay between ALE low and RE low.
231	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
232	}FMC_PCCARD_InitTypeDef;
233
234	/**
235	* @brief FMC SDRAM Configuration Structure definition
236	*/
237	typedef struct
238	{
239	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
240	This parameter can be a value of @ref FMC_SDRAM_Bank */
241
242	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
243	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
244
245	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
246	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
247
248	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
249	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
250
251	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
252	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
253
254	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
255	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
256
257	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
258	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
259
260	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
261	to disable the clock before changing frequency.
262	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
263
264	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
265	commands during the CAS latency and stores data in the Read FIFO.
266	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
267
268	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
269	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
270	}FMC_SDRAM_InitTypeDef;
271
272	/**
273	* @brief FMC SDRAM Timing parameters structure definition
274	*/
275	typedef struct
276	{
277	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
278	an active or Refresh command in number of memory clock cycles.
279	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
280
281	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
282	issuing the Activate command in number of memory clock cycles.
283	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
284
285	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
286	cycles.
287	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
288
289	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
290	and the delay between two consecutive Refresh commands in number of
291	memory clock cycles.
292	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
293
294	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
295	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
296
297	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
298	in number of memory clock cycles.
299	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
300
301	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
302	command in number of memory clock cycles.
303	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
304	}FMC_SDRAM_TimingTypeDef;
305
306	/**
307	* @brief SDRAM command parameters structure definition
308	*/
309	typedef struct
310	{
311	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
312	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
313
314	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
315	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
316
317	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
318	in auto refresh mode.
319	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
320	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
321	}FMC_SDRAM_CommandTypeDef;
322	/**
323	* @}
324	*/
325
326	/* Private constants ---------------------------------------------------------*/
327	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
328	* @{
329	*/
330
331	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
332	* @{
333	*/
334	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
335	* @{
336	*/
337	#define FMC_NORSRAM_BANK1 0x00000000U
338	#define FMC_NORSRAM_BANK2 0x00000002U
339	#define FMC_NORSRAM_BANK3 0x00000004U
340	#define FMC_NORSRAM_BANK4 0x00000006U
341	/**
342	* @}
343	*/
344
345	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
346	* @{
347	*/
348	#define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
349	#define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
350	/**
351	* @}
352	*/
353
354	/** @defgroup FMC_Memory_Type FMC Memory Type
355	* @{
356	*/
357	#define FMC_MEMORY_TYPE_SRAM 0x00000000U
358	#define FMC_MEMORY_TYPE_PSRAM 0x00000004U
359	#define FMC_MEMORY_TYPE_NOR 0x00000008U
360	/**
361	* @}
362	*/
363
364	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
365	* @{
366	*/
367	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
368	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
369	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
370	/**
371	* @}
372	*/
373
374	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
375	* @{
376	*/
377	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
378	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
379	/**
380	* @}
381	*/
382
383	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
384	* @{
385	*/
386	#define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
387	#define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
388	/**
389	* @}
390	*/
391
392	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
393	* @{
394	*/
395	#define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
396	#define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
397	/**
398	* @}
399	*/
400
401	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
402	* @{
403	*/
404	/** @note This mode is not available for the STM32F446/469/479xx devices
405	*/
406	#define FMC_WRAP_MODE_DISABLE 0x00000000U
407	#define FMC_WRAP_MODE_ENABLE 0x00000400U
408	/**
409	* @}
410	*/
411
412	/** @defgroup FMC_Wait_Timing FMC Wait Timing
413	* @{
414	*/
415	#define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U
416	#define FMC_WAIT_TIMING_DURING_WS 0x00000800U
417	/**
418	* @}
419	*/
420
421	/** @defgroup FMC_Write_Operation FMC Write Operation
422	* @{
423	*/
424	#define FMC_WRITE_OPERATION_DISABLE 0x00000000U
425	#define FMC_WRITE_OPERATION_ENABLE 0x00001000U
426	/**
427	* @}
428	*/
429
430	/** @defgroup FMC_Wait_Signal FMC Wait Signal
431	* @{
432	*/
433	#define FMC_WAIT_SIGNAL_DISABLE 0x00000000U
434	#define FMC_WAIT_SIGNAL_ENABLE 0x00002000U
435	/**
436	* @}
437	*/
438
439	/** @defgroup FMC_Extended_Mode FMC Extended Mode
440	* @{
441	*/
442	#define FMC_EXTENDED_MODE_DISABLE 0x00000000U
443	#define FMC_EXTENDED_MODE_ENABLE 0x00004000U
444	/**
445	* @}
446	*/
447
448	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
449	* @{
450	*/
451	#define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
452	#define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
453	/**
454	* @}
455	*/
456
457	/** @defgroup FMC_Page_Size FMC Page Size
458	* @{
459	*/
460	#define FMC_PAGE_SIZE_NONE 0x00000000U
461	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
462	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
463	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
464	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
465	/**
466	* @}
467	*/
468
469	/** @defgroup FMC_Write_FIFO FMC Write FIFO
470	* @note These values are available only for the STM32F446/469/479xx devices.
471	* @{
472	*/
473	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
474	#define FMC_WRITE_FIFO_ENABLE 0x00000000U
475	/**
476	* @}
477	*/
478
479	/** @defgroup FMC_Write_Burst FMC Write Burst
480	* @{
481	*/
482	#define FMC_WRITE_BURST_DISABLE 0x00000000U
483	#define FMC_WRITE_BURST_ENABLE 0x00080000U
484	/**
485	* @}
486	*/
487
488	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
489	* @{
490	*/
491	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
492	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
493	/**
494	* @}
495	*/
496
497	/** @defgroup FMC_Access_Mode FMC Access Mode
498	* @{
499	*/
500	#define FMC_ACCESS_MODE_A 0x00000000U
501	#define FMC_ACCESS_MODE_B 0x10000000U
502	#define FMC_ACCESS_MODE_C 0x20000000U
503	#define FMC_ACCESS_MODE_D 0x30000000U
504	/**
505	* @}
506	*/
507
508	/**
509	* @}
510	*/
511
512	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
513	* @{
514	*/
515	/** @defgroup FMC_NAND_Bank FMC NAND Bank
516	* @{
517	*/
518	#define FMC_NAND_BANK2 0x00000010U
519	#define FMC_NAND_BANK3 0x00000100U
520	/**
521	* @}
522	*/
523
524	/** @defgroup FMC_Wait_feature FMC Wait feature
525	* @{
526	*/
527	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
528	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
529	/**
530	* @}
531	*/
532
533	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
534	* @{
535	*/
536	#define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
537	#define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U
538	/**
539	* @}
540	*/
541
542	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
543	* @{
544	*/
545	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
546	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
547	/**
548	* @}
549	*/
550
551	/** @defgroup FMC_ECC FMC ECC
552	* @{
553	*/
554	#define FMC_NAND_ECC_DISABLE 0x00000000U
555	#define FMC_NAND_ECC_ENABLE 0x00000040U
556	/**
557	* @}
558	*/
559
560	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
561	* @{
562	*/
563	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
564	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
565	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
566	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
567	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
568	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
569	/**
570	* @}
571	*/
572
573	/**
574	* @}
575	*/
576
577	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
578	* @{
579	*/
580	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
581	* @{
582	*/
583	#define FMC_SDRAM_BANK1 0x00000000U
584	#define FMC_SDRAM_BANK2 0x00000001U
585	/**
586	* @}
587	*/
588
589	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
590	* @{
591	*/
592	#define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U
593	#define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U
594	#define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U
595	#define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U
596	/**
597	* @}
598	*/
599
600	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
601	* @{
602	*/
603	#define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U
604	#define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U
605	#define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U
606	/**
607	* @}
608	*/
609
610	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
611	* @{
612	*/
613	#define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U
614	#define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U
615	#define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U
616	/**
617	* @}
618	*/
619
620	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
621	* @{
622	*/
623	#define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U
624	#define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U
625	/**
626	* @}
627	*/
628
629	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
630	* @{
631	*/
632	#define FMC_SDRAM_CAS_LATENCY_1 0x00000080U
633	#define FMC_SDRAM_CAS_LATENCY_2 0x00000100U
634	#define FMC_SDRAM_CAS_LATENCY_3 0x00000180U
635	/**
636	* @}
637	*/
638
639	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
640	* @{
641	*/
642	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U
643	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U
644
645	/**
646	* @}
647	*/
648
649	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
650	* @{
651	*/
652	#define FMC_SDRAM_CLOCK_DISABLE 0x00000000U
653	#define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U
654	#define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U
655	/**
656	* @}
657	*/
658
659	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
660	* @{
661	*/
662	#define FMC_SDRAM_RBURST_DISABLE 0x00000000U
663	#define FMC_SDRAM_RBURST_ENABLE 0x00001000U
664	/**
665	* @}
666	*/
667
668	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
669	* @{
670	*/
671	#define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U
672	#define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U
673	#define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U
674	/**
675	* @}
676	*/
677
678	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
679	* @{
680	*/
681	#define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U
682	#define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U
683	#define FMC_SDRAM_CMD_PALL 0x00000002U
684	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U
685	#define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U
686	#define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U
687	#define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U
688	/**
689	* @}
690	*/
691
692	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
693	* @{
694	*/
695	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
696	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
697	#define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U
698	/**
699	* @}
700	*/
701
702	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
703	* @{
704	*/
705	#define FMC_SDRAM_NORMAL_MODE 0x00000000U
706	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
707	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
708	/**
709	* @}
710	*/
711
712	/**
713	* @}
714	*/
715
716	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
717	* @{
718	*/
719	#define FMC_IT_RISING_EDGE 0x00000008U
720	#define FMC_IT_LEVEL 0x00000010U
721	#define FMC_IT_FALLING_EDGE 0x00000020U
722	#define FMC_IT_REFRESH_ERROR 0x00004000U
723	/**
724	* @}
725	*/
726
727	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
728	* @{
729	*/
730	#define FMC_FLAG_RISING_EDGE 0x00000001U
731	#define FMC_FLAG_LEVEL 0x00000002U
732	#define FMC_FLAG_FALLING_EDGE 0x00000004U
733	#define FMC_FLAG_FEMPT 0x00000040U
734	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
735	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
736	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
737	/**
738	* @}
739	*/
740
741	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
742	* @{
743	*/
744	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
745	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
746	#else
747	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
748	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
749	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
750	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
751	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
752	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
753
754
755	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
756	#define FMC_NAND_DEVICE FMC_Bank3
757	#else
758	#define FMC_NAND_DEVICE FMC_Bank2_3
759	#define FMC_PCCARD_DEVICE FMC_Bank4
760	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
761	#define FMC_NORSRAM_DEVICE FMC_Bank1
762	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
763	#define FMC_SDRAM_DEVICE FMC_Bank5_6
764	/**
765	* @}
766	*/
767
768	/**
769	* @}
770	*/
771
772	/* Private macro -------------------------------------------------------------*/
773	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
774	* @{
775	*/
776
777	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
778	* @brief macros to handle NOR device enable/disable and read/write operations
779	* @{
780	*/
781	/**
782	* @brief Enable the NORSRAM device access.
783	* @param __INSTANCE__ FMC_NORSRAM Instance
784	* @param __BANK__ FMC_NORSRAM Bank
785	* @retval None
786	*/
787	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
788
789	/**
790	* @brief Disable the NORSRAM device access.
791	* @param __INSTANCE__ FMC_NORSRAM Instance
792	* @param __BANK__ FMC_NORSRAM Bank
793	* @retval None
794	*/
795	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
796	/**
797	* @}
798	*/
799
800	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
801	* @brief macros to handle NAND device enable/disable
802	* @{
803	*/
804	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
805	/**
806	* @brief Enable the NAND device access.
807	* @param __INSTANCE__ FMC_NAND Instance
808	* @param __BANK__ FMC_NAND Bank
809	* @retval None
810	*/
811	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
812
813	/**
814	* @brief Disable the NAND device access.
815	* @param __INSTANCE__ FMC_NAND Instance
816	* @param __BANK__ FMC_NAND Bank
817	* @retval None
818	*/
819	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
820	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
821	/**
822	* @brief Enable the NAND device access.
823	* @param __INSTANCE__ FMC_NAND Instance
824	* @param __BANK__ FMC_NAND Bank
825	* @retval None
826	*/
827	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
828	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
829
830	/**
831	* @brief Disable the NAND device access.
832	* @param __INSTANCE__ FMC_NAND Instance
833	* @param __BANK__ FMC_NAND Bank
834	* @retval None
835	*/
836	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
837	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
838
839	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
840	/**
841	* @}
842	*/
843	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
844	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
845	* @brief macros to handle SRAM read/write operations
846	* @{
847	*/
848	/**
849	* @brief Enable the PCCARD device access.
850	* @param __INSTANCE__ FMC_PCCARD Instance
851	* @retval None
852	*/
853	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
854
855	/**
856	* @brief Disable the PCCARD device access.
857	* @param __INSTANCE__ FMC_PCCARD Instance
858	* @retval None
859	*/
860	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
861	/**
862	* @}
863	*/
864	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
865
866	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
867	* @brief macros to handle FMC flags and interrupts
868	* @{
869	*/
870	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
871	/**
872	* @brief Enable the NAND device interrupt.
873	* @param __INSTANCE__ FMC_NAND instance
874	* @param __BANK__ FMC_NAND Bank
875	* @param __INTERRUPT__ FMC_NAND interrupt
876	* This parameter can be any combination of the following values:
877	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
878	* @arg FMC_IT_LEVEL: Interrupt level.
879	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
880	* @retval None
881	*/
882	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
883
884	/**
885	* @brief Disable the NAND device interrupt.
886	* @param __INSTANCE__ FMC_NAND Instance
887	* @param __BANK__ FMC_NAND Bank
888	* @param __INTERRUPT__ FMC_NAND interrupt
889	* This parameter can be any combination of the following values:
890	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
891	* @arg FMC_IT_LEVEL: Interrupt level.
892	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
893	* @retval None
894	*/
895	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
896
897	/**
898	* @brief Get flag status of the NAND device.
899	* @param __INSTANCE__ FMC_NAND Instance
900	* @param __BANK__ FMC_NAND Bank
901	* @param __FLAG__ FMC_NAND flag
902	* This parameter can be any combination of the following values:
903	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
904	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
905	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
906	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
907	* @retval The state of FLAG (SET or RESET).
908	*/
909	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
910	/**
911	* @brief Clear flag status of the NAND device.
912	* @param __INSTANCE__ FMC_NAND Instance
913	* @param __BANK__ FMC_NAND Bank
914	* @param __FLAG__ FMC_NAND flag
915	* This parameter can be any combination of the following values:
916	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
917	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
918	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
919	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
920	* @retval None
921	*/
922	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
923	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
924	/**
925	* @brief Enable the NAND device interrupt.
926	* @param __INSTANCE__ FMC_NAND instance
927	* @param __BANK__ FMC_NAND Bank
928	* @param __INTERRUPT__ FMC_NAND interrupt
929	* This parameter can be any combination of the following values:
930	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
931	* @arg FMC_IT_LEVEL: Interrupt level.
932	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
933	* @retval None
934	*/
935	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
936	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
937
938	/**
939	* @brief Disable the NAND device interrupt.
940	* @param __INSTANCE__ FMC_NAND Instance
941	* @param __BANK__ FMC_NAND Bank
942	* @param __INTERRUPT__ FMC_NAND interrupt
943	* This parameter can be any combination of the following values:
944	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
945	* @arg FMC_IT_LEVEL: Interrupt level.
946	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
947	* @retval None
948	*/
949	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
950	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
951
952	/**
953	* @brief Get flag status of the NAND device.
954	* @param __INSTANCE__ FMC_NAND Instance
955	* @param __BANK__ FMC_NAND Bank
956	* @param __FLAG__ FMC_NAND flag
957	* This parameter can be any combination of the following values:
958	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
959	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
960	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
961	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
962	* @retval The state of FLAG (SET or RESET).
963	*/
964	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
965	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
966	/**
967	* @brief Clear flag status of the NAND device.
968	* @param __INSTANCE__ FMC_NAND Instance
969	* @param __BANK__ FMC_NAND Bank
970	* @param __FLAG__ FMC_NAND flag
971	* This parameter can be any combination of the following values:
972	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
973	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
974	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
975	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
976	* @retval None
977	*/
978	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
979	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
980	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
981
982	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
983	/**
984	* @brief Enable the PCCARD device interrupt.
985	* @param __INSTANCE__ FMC_PCCARD instance
986	* @param __INTERRUPT__ FMC_PCCARD interrupt
987	* This parameter can be any combination of the following values:
988	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
989	* @arg FMC_IT_LEVEL: Interrupt level.
990	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
991	* @retval None
992	*/
993	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
994
995	/**
996	* @brief Disable the PCCARD device interrupt.
997	* @param __INSTANCE__ FMC_PCCARD instance
998	* @param __INTERRUPT__ FMC_PCCARD interrupt
999	* This parameter can be any combination of the following values:
1000	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1001	* @arg FMC_IT_LEVEL: Interrupt level.
1002	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1003	* @retval None
1004	*/
1005	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
1006
1007	/**
1008	* @brief Get flag status of the PCCARD device.
1009	* @param __INSTANCE__ FMC_PCCARD instance
1010	* @param __FLAG__ FMC_PCCARD flag
1011	* This parameter can be any combination of the following values:
1012	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1013	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1014	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1015	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
1016	* @retval The state of FLAG (SET or RESET).
1017	*/
1018	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
1019
1020	/**
1021	* @brief Clear flag status of the PCCARD device.
1022	* @param __INSTANCE__ FMC_PCCARD instance
1023	* @param __FLAG__ FMC_PCCARD flag
1024	* This parameter can be any combination of the following values:
1025	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1026	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1027	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1028	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
1029	* @retval None
1030	*/
1031	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
1032	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
1033
1034	/**
1035	* @brief Enable the SDRAM device interrupt.
1036	* @param __INSTANCE__ FMC_SDRAM instance
1037	* @param __INTERRUPT__ FMC_SDRAM interrupt
1038	* This parameter can be any combination of the following values:
1039	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1040	* @retval None
1041	*/
1042	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
1043
1044	/**
1045	* @brief Disable the SDRAM device interrupt.
1046	* @param __INSTANCE__ FMC_SDRAM instance
1047	* @param __INTERRUPT__ FMC_SDRAM interrupt
1048	* This parameter can be any combination of the following values:
1049	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1050	* @retval None
1051	*/
1052	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1053
1054	/**
1055	* @brief Get flag status of the SDRAM device.
1056	* @param __INSTANCE__ FMC_SDRAM instance
1057	* @param __FLAG__ FMC_SDRAM flag
1058	* This parameter can be any combination of the following values:
1059	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
1060	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
1061	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
1062	* @retval The state of FLAG (SET or RESET).
1063	*/
1064	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1065
1066	/**
1067	* @brief Clear flag status of the SDRAM device.
1068	* @param __INSTANCE__ FMC_SDRAM instance
1069	* @param __FLAG__ FMC_SDRAM flag
1070	* This parameter can be any combination of the following values:
1071	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
1072	* @retval None
1073	*/
1074	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
1075	/**
1076	* @}
1077	*/
1078
1079	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
1080	* @{
1081	*/
1082	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
1083	((BANK) == FMC_NORSRAM_BANK2) \|\| \
1084	((BANK) == FMC_NORSRAM_BANK3) \|\| \
1085	((BANK) == FMC_NORSRAM_BANK4))
1086
1087	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
1088	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
1089
1090	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
1091	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
1092	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
1093
1094	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
1095	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
1096	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
1097
1098	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
1099	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
1100	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
1101	((__MODE__) == FMC_ACCESS_MODE_D))
1102
1103	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
1104	((BANK) == FMC_NAND_BANK3))
1105
1106	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
1107	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
1108
1109	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
1110	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
1111
1112	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
1113	((STATE) == FMC_NAND_ECC_ENABLE))
1114
1115	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
1116	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
1117	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
1118	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
1119	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
1120	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
1121
1122	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
1123
1124	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
1125
1126	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
1127
1128	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
1129
1130	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
1131
1132	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
1133
1134	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
1135
1136	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
1137
1138	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
1139
1140	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
1141
1142	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
1143	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
1144
1145	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
1146	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
1147
1148	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
1149	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
1150	((__MODE__) == FMC_WRAP_MODE_ENABLE))
1151	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
1152
1153	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
1154	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
1155
1156	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
1157	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
1158
1159	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
1160	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
1161
1162	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
1163	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
1164
1165	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
1166	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
1167
1168	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
1169	((__BURST__) == FMC_WRITE_BURST_ENABLE))
1170
1171	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
1172	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
1173
1174	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
1175
1176	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
1177
1178	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
1179
1180	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
1181
1182	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
1183
1184	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
1185
1186	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
1187	((BANK) == FMC_SDRAM_BANK2))
1188
1189	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
1190	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
1191	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
1192	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
1193
1194	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
1195	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
1196	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
1197
1198	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
1199	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
1200	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
1201
1202	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
1203	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
1204
1205
1206	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
1207	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
1208	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
1209
1210	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
1211	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
1212	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
1213
1214	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
1215	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
1216
1217
1218	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
1219	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
1220	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
1221
1222	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1223
1224	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1225
1226	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
1227
1228	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1229
1230	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
1231
1232	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1233
1234	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1235
1236	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
1237	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
1238	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
1239	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
1240	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
1241	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
1242	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
1243
1244	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
1245	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
1246	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
1247
1248	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
1249
1250	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
1251
1252	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
1253
1254	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
1255
1256	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
1257	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
1258
1259	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
1260	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
1261	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
1262	((SIZE) == FMC_PAGE_SIZE_512) \|\| \
1263	((SIZE) == FMC_PAGE_SIZE_1024))
1264
1265	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
1266	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
1267	((FIFO) == FMC_WRITE_FIFO_ENABLE))
1268	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
1269
1270	/**
1271	* @}
1272	*/
1273
1274	/**
1275	* @}
1276	*/
1277
1278	/* Private functions ---------------------------------------------------------*/
1279	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
1280	* @{
1281	*/
1282
1283	/** @defgroup FMC_LL_NORSRAM NOR SRAM
1284	* @{
1285	*/
1286	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
1287	* @{
1288	*/
1289	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
1290	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
1291	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
1292	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
1293	/**
1294	* @}
1295	*/
1296
1297	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
1298	* @{
1299	*/
1300	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1301	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1302	/**
1303	* @}
1304	*/
1305	/**
1306	* @}
1307	*/
1308
1309	/** @defgroup FMC_LL_NAND NAND
1310	* @{
1311	*/
1312	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
1313	* @{
1314	*/
1315	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
1316	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
1317	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
1318	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1319	/**
1320	* @}
1321	*/
1322
1323	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
1324	* @{
1325	*/
1326	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1327	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1328	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
1329
1330	/**
1331	* @}
1332	*/
1333	/**
1334	* @}
1335	*/
1336	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
1337	/** @defgroup FMC_LL_PCCARD PCCARD
1338	* @{
1339	*/
1340	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
1341	* @{
1342	*/
1343	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
1344	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
1345	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
1346	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
1347	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
1348	/**
1349	* @}
1350	*/
1351	/**
1352	* @}
1353	*/
1354	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
1355
1356	/** @defgroup FMC_LL_SDRAM SDRAM
1357	* @{
1358	*/
1359	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
1360	* @{
1361	*/
1362	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
1363	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
1364	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1365	/**
1366	* @}
1367	*/
1368
1369	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
1370	* @{
1371	*/
1372	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1373	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1374	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
1375	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1376	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
1377	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1378	/**
1379	* @}
1380	*/
1381	/**
1382	* @}
1383	*/
1384
1385	/**
1386	* @}
1387	*/
1388
1389	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
1390	/**
1391	* @}
1392	*/
1393
1394	/**
1395	* @}
1396	*/
1397	#ifdef __cplusplus
1398	}
1399	#endif
1400
1401	#endif /* __STM32F4xx_LL_FMC_H */
1402
1403	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h

Download in other formats: