source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h

Last change on this file was 1, checked in by AlexLir, 4 years ago
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fmpi2c.h
4 * @author MCD Application Team
5 * @brief Header file of FMPI2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef STM32F4xx_LL_FMPI2C_H
22#define STM32F4xx_LL_FMPI2C_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28#if defined(FMPI2C_CR1_PE)
29/* Includes ------------------------------------------------------------------*/
30#include "stm32f4xx.h"
31
32/** @addtogroup STM32F4xx_LL_Driver
33 * @{
34 */
35
36#if defined (FMPI2C1)
37
38/** @defgroup FMPI2C_LL FMPI2C
39 * @{
40 */
41
42/* Private types -------------------------------------------------------------*/
43/* Private variables ---------------------------------------------------------*/
44
45/* Private constants ---------------------------------------------------------*/
46/** @defgroup FMPI2C_LL_Private_Constants FMPI2C Private Constants
47 * @{
48 */
49/**
50 * @}
51 */
52
53/* Private macros ------------------------------------------------------------*/
54#if defined(USE_FULL_LL_DRIVER)
55/** @defgroup FMPI2C_LL_Private_Macros FMPI2C Private Macros
56 * @{
57 */
58/**
59 * @}
60 */
61#endif /*USE_FULL_LL_DRIVER*/
62
63/* Exported types ------------------------------------------------------------*/
64#if defined(USE_FULL_LL_DRIVER)
65/** @defgroup FMPI2C_LL_ES_INIT FMPI2C Exported Init structure
66 * @{
67 */
68typedef struct
69{
70 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
71 This parameter can be a value of @ref FMPI2C_LL_EC_PERIPHERAL_MODE.
72
73 This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetMode(). */
74
75 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
76 This parameter must be set by referring to the STM32CubeMX Tool and
77 the helper macro @ref __LL_FMPI2C_CONVERT_TIMINGS().
78
79 This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetTiming(). */
80
81 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
82 This parameter can be a value of @ref FMPI2C_LL_EC_ANALOGFILTER_SELECTION.
83
84 This feature can be modified afterwards using unitary functions @ref LL_FMPI2C_EnableAnalogFilter() or LL_FMPI2C_DisableAnalogFilter(). */
85
86 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
87 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
88
89 This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetDigitalFilter(). */
90
91 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
92 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
93
94 This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */
95
96 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
97 This parameter can be a value of @ref FMPI2C_LL_EC_I2C_ACKNOWLEDGE.
98
99 This feature can be modified afterwards using unitary function @ref LL_FMPI2C_AcknowledgeNextData(). */
100
101 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
102 This parameter can be a value of @ref FMPI2C_LL_EC_OWNADDRESS1.
103
104 This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */
105} LL_FMPI2C_InitTypeDef;
106/**
107 * @}
108 */
109#endif /*USE_FULL_LL_DRIVER*/
110
111/* Exported constants --------------------------------------------------------*/
112/** @defgroup FMPI2C_LL_Exported_Constants FMPI2C Exported Constants
113 * @{
114 */
115
116/** @defgroup FMPI2C_LL_EC_CLEAR_FLAG Clear Flags Defines
117 * @brief Flags defines which can be used with LL_FMPI2C_WriteReg function
118 * @{
119 */
120#define LL_FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF /*!< Address Matched flag */
121#define LL_FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF /*!< Not Acknowledge flag */
122#define LL_FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF /*!< Stop detection flag */
123#define LL_FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF /*!< Bus error flag */
124#define LL_FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF /*!< Arbitration Lost flag */
125#define LL_FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF /*!< Overrun/Underrun flag */
126#define LL_FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF /*!< PEC error flag */
127#define LL_FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF /*!< Timeout detection flag */
128#define LL_FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF /*!< Alert flag */
129/**
130 * @}
131 */
132
133/** @defgroup FMPI2C_LL_EC_GET_FLAG Get Flags Defines
134 * @brief Flags defines which can be used with LL_FMPI2C_ReadReg function
135 * @{
136 */
137#define LL_FMPI2C_ISR_TXE FMPI2C_ISR_TXE /*!< Transmit data register empty */
138#define LL_FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS /*!< Transmit interrupt status */
139#define LL_FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE /*!< Receive data register not empty */
140#define LL_FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR /*!< Address matched (slave mode) */
141#define LL_FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF /*!< Not Acknowledge received flag */
142#define LL_FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF /*!< Stop detection flag */
143#define LL_FMPI2C_ISR_TC FMPI2C_ISR_TC /*!< Transfer Complete (master mode) */
144#define LL_FMPI2C_ISR_TCR FMPI2C_ISR_TCR /*!< Transfer Complete Reload */
145#define LL_FMPI2C_ISR_BERR FMPI2C_ISR_BERR /*!< Bus error */
146#define LL_FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO /*!< Arbitration lost */
147#define LL_FMPI2C_ISR_OVR FMPI2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
148#define LL_FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
149#define LL_FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
150#define LL_FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
151#define LL_FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY /*!< Bus busy */
152/**
153 * @}
154 */
155
156/** @defgroup FMPI2C_LL_EC_IT IT Defines
157 * @brief IT defines which can be used with LL_FMPI2C_ReadReg and LL_FMPI2C_WriteReg functions
158 * @{
159 */
160#define LL_FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE /*!< TX Interrupt enable */
161#define LL_FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE /*!< RX Interrupt enable */
162#define LL_FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
163#define LL_FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
164#define LL_FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
165#define LL_FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
166#define LL_FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE /*!< Error interrupts enable */
167/**
168 * @}
169 */
170
171/** @defgroup FMPI2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
172 * @{
173 */
174#define LL_FMPI2C_MODE_I2C 0x00000000U /*!< FMPI2C Master or Slave mode */
175#define LL_FMPI2C_MODE_SMBUS_HOST FMPI2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
176#define LL_FMPI2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
177#define LL_FMPI2C_MODE_SMBUS_DEVICE_ARP FMPI2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
178/**
179 * @}
180 */
181
182/** @defgroup FMPI2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
183 * @{
184 */
185#define LL_FMPI2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
186#define LL_FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF /*!< Analog filter is disabled. */
187/**
188 * @}
189 */
190
191/** @defgroup FMPI2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
192 * @{
193 */
194#define LL_FMPI2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
195#define LL_FMPI2C_ADDRESSING_MODE_10BIT FMPI2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
196/**
197 * @}
198 */
199
200/** @defgroup FMPI2C_LL_EC_OWNADDRESS1 Own Address 1 Length
201 * @{
202 */
203#define LL_FMPI2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
204#define LL_FMPI2C_OWNADDRESS1_10BIT FMPI2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
205/**
206 * @}
207 */
208
209/** @defgroup FMPI2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
210 * @{
211 */
212#define LL_FMPI2C_OWNADDRESS2_NOMASK FMPI2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
213#define LL_FMPI2C_OWNADDRESS2_MASK01 FMPI2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
214#define LL_FMPI2C_OWNADDRESS2_MASK02 FMPI2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
215#define LL_FMPI2C_OWNADDRESS2_MASK03 FMPI2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
216#define LL_FMPI2C_OWNADDRESS2_MASK04 FMPI2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
217#define LL_FMPI2C_OWNADDRESS2_MASK05 FMPI2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
218#define LL_FMPI2C_OWNADDRESS2_MASK06 FMPI2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
219#define LL_FMPI2C_OWNADDRESS2_MASK07 FMPI2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
220/**
221 * @}
222 */
223
224/** @defgroup FMPI2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
225 * @{
226 */
227#define LL_FMPI2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
228#define LL_FMPI2C_NACK FMPI2C_CR2_NACK /*!< NACK is sent after current received byte.*/
229/**
230 * @}
231 */
232
233/** @defgroup FMPI2C_LL_EC_ADDRSLAVE Slave Address Length
234 * @{
235 */
236#define LL_FMPI2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
237#define LL_FMPI2C_ADDRSLAVE_10BIT FMPI2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
238/**
239 * @}
240 */
241
242/** @defgroup FMPI2C_LL_EC_REQUEST Transfer Request Direction
243 * @{
244 */
245#define LL_FMPI2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
246#define LL_FMPI2C_REQUEST_READ FMPI2C_CR2_RD_WRN /*!< Master request a read transfer. */
247/**
248 * @}
249 */
250
251/** @defgroup FMPI2C_LL_EC_MODE Transfer End Mode
252 * @{
253 */
254#define LL_FMPI2C_MODE_RELOAD FMPI2C_CR2_RELOAD /*!< Enable FMPI2C Reload mode. */
255#define LL_FMPI2C_MODE_AUTOEND FMPI2C_CR2_AUTOEND /*!< Enable FMPI2C Automatic end mode with no HW PEC comparison. */
256#define LL_FMPI2C_MODE_SOFTEND 0x00000000U /*!< Enable FMPI2C Software end mode with no HW PEC comparison. */
257#define LL_FMPI2C_MODE_SMBUS_RELOAD LL_FMPI2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
258#define LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC LL_FMPI2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
259#define LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC LL_FMPI2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
260#define LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_AUTOEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
261#define LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_SOFTEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
262/**
263 * @}
264 */
265
266/** @defgroup FMPI2C_LL_EC_GENERATE Start And Stop Generation
267 * @{
268 */
269#define LL_FMPI2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
270#define LL_FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
271#define LL_FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Start for read request. */
272#define LL_FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Start for write request. */
273#define LL_FMPI2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
274#define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
275#define LL_FMPI2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
276#define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
277/**
278 * @}
279 */
280
281/** @defgroup FMPI2C_LL_EC_DIRECTION Read Write Direction
282 * @{
283 */
284#define LL_FMPI2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
285#define LL_FMPI2C_DIRECTION_READ FMPI2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
286/**
287 * @}
288 */
289
290/** @defgroup FMPI2C_LL_EC_DMA_REG_DATA DMA Register Data
291 * @{
292 */
293#define LL_FMPI2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
294#define LL_FMPI2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
295/**
296 * @}
297 */
298
299/** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
300 * @{
301 */
302#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
303#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH FMPI2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
304/**
305 * @}
306 */
307
308/** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
309 * @{
310 */
311#define LL_FMPI2C_SMBUS_TIMEOUTA FMPI2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
312#define LL_FMPI2C_SMBUS_TIMEOUTB FMPI2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
313#define LL_FMPI2C_SMBUS_ALL_TIMEOUT (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
314/**
315 * @}
316 */
317
318/**
319 * @}
320 */
321
322/* Exported macro ------------------------------------------------------------*/
323/** @defgroup FMPI2C_LL_Exported_Macros FMPI2C Exported Macros
324 * @{
325 */
326
327/** @defgroup FMPI2C_LL_EM_WRITE_READ Common Write and read registers Macros
328 * @{
329 */
330
331/**
332 * @brief Write a value in FMPI2C register
333 * @param __INSTANCE__ FMPI2C Instance
334 * @param __REG__ Register to be written
335 * @param __VALUE__ Value to be written in the register
336 * @retval None
337 */
338#define LL_FMPI2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
339
340/**
341 * @brief Read a value in FMPI2C register
342 * @param __INSTANCE__ FMPI2C Instance
343 * @param __REG__ Register to be read
344 * @retval Register value
345 */
346#define LL_FMPI2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
347/**
348 * @}
349 */
350
351/** @defgroup FMPI2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
352 * @{
353 */
354/**
355 * @brief Configure the SDA setup, hold time and the SCL high, low period.
356 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
357 * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
358 * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
359 * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
360 * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
361 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
362 */
363#define __LL_FMPI2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
364 ((((uint32_t)(__PRESCALER__) << FMPI2C_TIMINGR_PRESC_Pos) & FMPI2C_TIMINGR_PRESC) | \
365 (((uint32_t)(__DATA_SETUP_TIME__) << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL) | \
366 (((uint32_t)(__DATA_HOLD_TIME__) << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL) | \
367 (((uint32_t)(__CLOCK_HIGH_PERIOD__) << FMPI2C_TIMINGR_SCLH_Pos) & FMPI2C_TIMINGR_SCLH) | \
368 (((uint32_t)(__CLOCK_LOW_PERIOD__) << FMPI2C_TIMINGR_SCLL_Pos) & FMPI2C_TIMINGR_SCLL))
369/**
370 * @}
371 */
372
373/**
374 * @}
375 */
376
377/* Exported functions --------------------------------------------------------*/
378/** @defgroup FMPI2C_LL_Exported_Functions FMPI2C Exported Functions
379 * @{
380 */
381
382/** @defgroup FMPI2C_LL_EF_Configuration Configuration
383 * @{
384 */
385
386/**
387 * @brief Enable FMPI2C peripheral (PE = 1).
388 * @rmtoll CR1 PE LL_FMPI2C_Enable
389 * @param FMPI2Cx FMPI2C Instance.
390 * @retval None
391 */
392__STATIC_INLINE void LL_FMPI2C_Enable(FMPI2C_TypeDef *FMPI2Cx)
393{
394 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE);
395}
396
397/**
398 * @brief Disable FMPI2C peripheral (PE = 0).
399 * @note When PE = 0, the FMPI2C SCL and SDA lines are released.
400 * Internal state machines and status bits are put back to their reset value.
401 * When cleared, PE must be kept low for at least 3 APB clock cycles.
402 * @rmtoll CR1 PE LL_FMPI2C_Disable
403 * @param FMPI2Cx FMPI2C Instance.
404 * @retval None
405 */
406__STATIC_INLINE void LL_FMPI2C_Disable(FMPI2C_TypeDef *FMPI2Cx)
407{
408 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE);
409}
410
411/**
412 * @brief Check if the FMPI2C peripheral is enabled or disabled.
413 * @rmtoll CR1 PE LL_FMPI2C_IsEnabled
414 * @param FMPI2Cx FMPI2C Instance.
415 * @retval State of bit (1 or 0).
416 */
417__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(FMPI2C_TypeDef *FMPI2Cx)
418{
419 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE) == (FMPI2C_CR1_PE)) ? 1UL : 0UL);
420}
421
422/**
423 * @brief Configure Noise Filters (Analog and Digital).
424 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
425 * The filters can only be programmed when the FMPI2C is disabled (PE = 0).
426 * @rmtoll CR1 ANFOFF LL_FMPI2C_ConfigFilters\n
427 * CR1 DNF LL_FMPI2C_ConfigFilters
428 * @param FMPI2Cx FMPI2C Instance.
429 * @param AnalogFilter This parameter can be one of the following values:
430 * @arg @ref LL_FMPI2C_ANALOGFILTER_ENABLE
431 * @arg @ref LL_FMPI2C_ANALOGFILTER_DISABLE
432 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk).
433 * This parameter is used to configure the digital noise filter on SDA and SCL input.
434 * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk.
435 * @retval None
436 */
437__STATIC_INLINE void LL_FMPI2C_ConfigFilters(FMPI2C_TypeDef *FMPI2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
438{
439 MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF | FMPI2C_CR1_DNF, AnalogFilter | (DigitalFilter << FMPI2C_CR1_DNF_Pos));
440}
441
442/**
443 * @brief Configure Digital Noise Filter.
444 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
445 * This filter can only be programmed when the FMPI2C is disabled (PE = 0).
446 * @rmtoll CR1 DNF LL_FMPI2C_SetDigitalFilter
447 * @param FMPI2Cx FMPI2C Instance.
448 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk).
449 * This parameter is used to configure the digital noise filter on SDA and SCL input.
450 * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk.
451 * @retval None
452 */
453__STATIC_INLINE void LL_FMPI2C_SetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx, uint32_t DigitalFilter)
454{
455 MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_DNF, DigitalFilter << FMPI2C_CR1_DNF_Pos);
456}
457
458/**
459 * @brief Get the current Digital Noise Filter configuration.
460 * @rmtoll CR1 DNF LL_FMPI2C_GetDigitalFilter
461 * @param FMPI2Cx FMPI2C Instance.
462 * @retval Value between Min_Data=0x0 and Max_Data=0xF
463 */
464__STATIC_INLINE uint32_t LL_FMPI2C_GetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx)
465{
466 return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_DNF) >> FMPI2C_CR1_DNF_Pos);
467}
468
469/**
470 * @brief Enable Analog Noise Filter.
471 * @note This filter can only be programmed when the FMPI2C is disabled (PE = 0).
472 * @rmtoll CR1 ANFOFF LL_FMPI2C_EnableAnalogFilter
473 * @param FMPI2Cx FMPI2C Instance.
474 * @retval None
475 */
476__STATIC_INLINE void LL_FMPI2C_EnableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
477{
478 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF);
479}
480
481/**
482 * @brief Disable Analog Noise Filter.
483 * @note This filter can only be programmed when the FMPI2C is disabled (PE = 0).
484 * @rmtoll CR1 ANFOFF LL_FMPI2C_DisableAnalogFilter
485 * @param FMPI2Cx FMPI2C Instance.
486 * @retval None
487 */
488__STATIC_INLINE void LL_FMPI2C_DisableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
489{
490 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF);
491}
492
493/**
494 * @brief Check if Analog Noise Filter is enabled or disabled.
495 * @rmtoll CR1 ANFOFF LL_FMPI2C_IsEnabledAnalogFilter
496 * @param FMPI2Cx FMPI2C Instance.
497 * @retval State of bit (1 or 0).
498 */
499__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
500{
501 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF) != (FMPI2C_CR1_ANFOFF)) ? 1UL : 0UL);
502}
503
504/**
505 * @brief Enable DMA transmission requests.
506 * @rmtoll CR1 TXDMAEN LL_FMPI2C_EnableDMAReq_TX
507 * @param FMPI2Cx FMPI2C Instance.
508 * @retval None
509 */
510__STATIC_INLINE void LL_FMPI2C_EnableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
511{
512 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN);
513}
514
515/**
516 * @brief Disable DMA transmission requests.
517 * @rmtoll CR1 TXDMAEN LL_FMPI2C_DisableDMAReq_TX
518 * @param FMPI2Cx FMPI2C Instance.
519 * @retval None
520 */
521__STATIC_INLINE void LL_FMPI2C_DisableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
522{
523 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN);
524}
525
526/**
527 * @brief Check if DMA transmission requests are enabled or disabled.
528 * @rmtoll CR1 TXDMAEN LL_FMPI2C_IsEnabledDMAReq_TX
529 * @param FMPI2Cx FMPI2C Instance.
530 * @retval State of bit (1 or 0).
531 */
532__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
533{
534 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN) == (FMPI2C_CR1_TXDMAEN)) ? 1UL : 0UL);
535}
536
537/**
538 * @brief Enable DMA reception requests.
539 * @rmtoll CR1 RXDMAEN LL_FMPI2C_EnableDMAReq_RX
540 * @param FMPI2Cx FMPI2C Instance.
541 * @retval None
542 */
543__STATIC_INLINE void LL_FMPI2C_EnableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
544{
545 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN);
546}
547
548/**
549 * @brief Disable DMA reception requests.
550 * @rmtoll CR1 RXDMAEN LL_FMPI2C_DisableDMAReq_RX
551 * @param FMPI2Cx FMPI2C Instance.
552 * @retval None
553 */
554__STATIC_INLINE void LL_FMPI2C_DisableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
555{
556 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN);
557}
558
559/**
560 * @brief Check if DMA reception requests are enabled or disabled.
561 * @rmtoll CR1 RXDMAEN LL_FMPI2C_IsEnabledDMAReq_RX
562 * @param FMPI2Cx FMPI2C Instance.
563 * @retval State of bit (1 or 0).
564 */
565__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
566{
567 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN) == (FMPI2C_CR1_RXDMAEN)) ? 1UL : 0UL);
568}
569
570/**
571 * @brief Get the data register address used for DMA transfer
572 * @rmtoll TXDR TXDATA LL_FMPI2C_DMA_GetRegAddr\n
573 * RXDR RXDATA LL_FMPI2C_DMA_GetRegAddr
574 * @param FMPI2Cx FMPI2C Instance
575 * @param Direction This parameter can be one of the following values:
576 * @arg @ref LL_FMPI2C_DMA_REG_DATA_TRANSMIT
577 * @arg @ref LL_FMPI2C_DMA_REG_DATA_RECEIVE
578 * @retval Address of data register
579 */
580__STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t Direction)
581{
582 uint32_t data_reg_addr;
583
584 if (Direction == LL_FMPI2C_DMA_REG_DATA_TRANSMIT)
585 {
586 /* return address of TXDR register */
587 data_reg_addr = (uint32_t) &(FMPI2Cx->TXDR);
588 }
589 else
590 {
591 /* return address of RXDR register */
592 data_reg_addr = (uint32_t) &(FMPI2Cx->RXDR);
593 }
594
595 return data_reg_addr;
596}
597
598/**
599 * @brief Enable Clock stretching.
600 * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
601 * @rmtoll CR1 NOSTRETCH LL_FMPI2C_EnableClockStretching
602 * @param FMPI2Cx FMPI2C Instance.
603 * @retval None
604 */
605__STATIC_INLINE void LL_FMPI2C_EnableClockStretching(FMPI2C_TypeDef *FMPI2Cx)
606{
607 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH);
608}
609
610/**
611 * @brief Disable Clock stretching.
612 * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
613 * @rmtoll CR1 NOSTRETCH LL_FMPI2C_DisableClockStretching
614 * @param FMPI2Cx FMPI2C Instance.
615 * @retval None
616 */
617__STATIC_INLINE void LL_FMPI2C_DisableClockStretching(FMPI2C_TypeDef *FMPI2Cx)
618{
619 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH);
620}
621
622/**
623 * @brief Check if Clock stretching is enabled or disabled.
624 * @rmtoll CR1 NOSTRETCH LL_FMPI2C_IsEnabledClockStretching
625 * @param FMPI2Cx FMPI2C Instance.
626 * @retval State of bit (1 or 0).
627 */
628__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledClockStretching(FMPI2C_TypeDef *FMPI2Cx)
629{
630 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH) != (FMPI2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
631}
632
633/**
634 * @brief Enable hardware byte control in slave mode.
635 * @rmtoll CR1 SBC LL_FMPI2C_EnableSlaveByteControl
636 * @param FMPI2Cx FMPI2C Instance.
637 * @retval None
638 */
639__STATIC_INLINE void LL_FMPI2C_EnableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
640{
641 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC);
642}
643
644/**
645 * @brief Disable hardware byte control in slave mode.
646 * @rmtoll CR1 SBC LL_FMPI2C_DisableSlaveByteControl
647 * @param FMPI2Cx FMPI2C Instance.
648 * @retval None
649 */
650__STATIC_INLINE void LL_FMPI2C_DisableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
651{
652 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC);
653}
654
655/**
656 * @brief Check if hardware byte control in slave mode is enabled or disabled.
657 * @rmtoll CR1 SBC LL_FMPI2C_IsEnabledSlaveByteControl
658 * @param FMPI2Cx FMPI2C Instance.
659 * @retval State of bit (1 or 0).
660 */
661__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
662{
663 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC) == (FMPI2C_CR1_SBC)) ? 1UL : 0UL);
664}
665
666
667/**
668 * @brief Enable General Call.
669 * @note When enabled the Address 0x00 is ACKed.
670 * @rmtoll CR1 GCEN LL_FMPI2C_EnableGeneralCall
671 * @param FMPI2Cx FMPI2C Instance.
672 * @retval None
673 */
674__STATIC_INLINE void LL_FMPI2C_EnableGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
675{
676 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN);
677}
678
679/**
680 * @brief Disable General Call.
681 * @note When disabled the Address 0x00 is NACKed.
682 * @rmtoll CR1 GCEN LL_FMPI2C_DisableGeneralCall
683 * @param FMPI2Cx FMPI2C Instance.
684 * @retval None
685 */
686__STATIC_INLINE void LL_FMPI2C_DisableGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
687{
688 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN);
689}
690
691/**
692 * @brief Check if General Call is enabled or disabled.
693 * @rmtoll CR1 GCEN LL_FMPI2C_IsEnabledGeneralCall
694 * @param FMPI2Cx FMPI2C Instance.
695 * @retval State of bit (1 or 0).
696 */
697__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
698{
699 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN) == (FMPI2C_CR1_GCEN)) ? 1UL : 0UL);
700}
701
702/**
703 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
704 * @note Changing this bit is not allowed, when the START bit is set.
705 * @rmtoll CR2 ADD10 LL_FMPI2C_SetMasterAddressingMode
706 * @param FMPI2Cx FMPI2C Instance.
707 * @param AddressingMode This parameter can be one of the following values:
708 * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT
709 * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT
710 * @retval None
711 */
712__STATIC_INLINE void LL_FMPI2C_SetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t AddressingMode)
713{
714 MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_ADD10, AddressingMode);
715}
716
717/**
718 * @brief Get the Master addressing mode.
719 * @rmtoll CR2 ADD10 LL_FMPI2C_GetMasterAddressingMode
720 * @param FMPI2Cx FMPI2C Instance.
721 * @retval Returned value can be one of the following values:
722 * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT
723 * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT
724 */
725__STATIC_INLINE uint32_t LL_FMPI2C_GetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx)
726{
727 return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_ADD10));
728}
729
730/**
731 * @brief Set the Own Address1.
732 * @rmtoll OAR1 OA1 LL_FMPI2C_SetOwnAddress1\n
733 * OAR1 OA1MODE LL_FMPI2C_SetOwnAddress1
734 * @param FMPI2Cx FMPI2C Instance.
735 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
736 * @param OwnAddrSize This parameter can be one of the following values:
737 * @arg @ref LL_FMPI2C_OWNADDRESS1_7BIT
738 * @arg @ref LL_FMPI2C_OWNADDRESS1_10BIT
739 * @retval None
740 */
741__STATIC_INLINE void LL_FMPI2C_SetOwnAddress1(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
742{
743 MODIFY_REG(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1 | FMPI2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
744}
745
746/**
747 * @brief Enable acknowledge on Own Address1 match address.
748 * @rmtoll OAR1 OA1EN LL_FMPI2C_EnableOwnAddress1
749 * @param FMPI2Cx FMPI2C Instance.
750 * @retval None
751 */
752__STATIC_INLINE void LL_FMPI2C_EnableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
753{
754 SET_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN);
755}
756
757/**
758 * @brief Disable acknowledge on Own Address1 match address.
759 * @rmtoll OAR1 OA1EN LL_FMPI2C_DisableOwnAddress1
760 * @param FMPI2Cx FMPI2C Instance.
761 * @retval None
762 */
763__STATIC_INLINE void LL_FMPI2C_DisableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
764{
765 CLEAR_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN);
766}
767
768/**
769 * @brief Check if Own Address1 acknowledge is enabled or disabled.
770 * @rmtoll OAR1 OA1EN LL_FMPI2C_IsEnabledOwnAddress1
771 * @param FMPI2Cx FMPI2C Instance.
772 * @retval State of bit (1 or 0).
773 */
774__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
775{
776 return ((READ_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN) == (FMPI2C_OAR1_OA1EN)) ? 1UL : 0UL);
777}
778
779/**
780 * @brief Set the 7bits Own Address2.
781 * @note This action has no effect if own address2 is enabled.
782 * @rmtoll OAR2 OA2 LL_FMPI2C_SetOwnAddress2\n
783 * OAR2 OA2MSK LL_FMPI2C_SetOwnAddress2
784 * @param FMPI2Cx FMPI2C Instance.
785 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
786 * @param OwnAddrMask This parameter can be one of the following values:
787 * @arg @ref LL_FMPI2C_OWNADDRESS2_NOMASK
788 * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK01
789 * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK02
790 * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK03
791 * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK04
792 * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK05
793 * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK06
794 * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK07
795 * @retval None
796 */
797__STATIC_INLINE void LL_FMPI2C_SetOwnAddress2(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
798{
799 MODIFY_REG(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2 | FMPI2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
800}
801
802/**
803 * @brief Enable acknowledge on Own Address2 match address.
804 * @rmtoll OAR2 OA2EN LL_FMPI2C_EnableOwnAddress2
805 * @param FMPI2Cx FMPI2C Instance.
806 * @retval None
807 */
808__STATIC_INLINE void LL_FMPI2C_EnableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
809{
810 SET_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN);
811}
812
813/**
814 * @brief Disable acknowledge on Own Address2 match address.
815 * @rmtoll OAR2 OA2EN LL_FMPI2C_DisableOwnAddress2
816 * @param FMPI2Cx FMPI2C Instance.
817 * @retval None
818 */
819__STATIC_INLINE void LL_FMPI2C_DisableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
820{
821 CLEAR_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN);
822}
823
824/**
825 * @brief Check if Own Address1 acknowledge is enabled or disabled.
826 * @rmtoll OAR2 OA2EN LL_FMPI2C_IsEnabledOwnAddress2
827 * @param FMPI2Cx FMPI2C Instance.
828 * @retval State of bit (1 or 0).
829 */
830__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
831{
832 return ((READ_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN) == (FMPI2C_OAR2_OA2EN)) ? 1UL : 0UL);
833}
834
835/**
836 * @brief Configure the SDA setup, hold time and the SCL high, low period.
837 * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
838 * @rmtoll TIMINGR TIMINGR LL_FMPI2C_SetTiming
839 * @param FMPI2Cx FMPI2C Instance.
840 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
841 * @note This parameter is computed with the STM32CubeMX Tool.
842 * @retval None
843 */
844__STATIC_INLINE void LL_FMPI2C_SetTiming(FMPI2C_TypeDef *FMPI2Cx, uint32_t Timing)
845{
846 WRITE_REG(FMPI2Cx->TIMINGR, Timing);
847}
848
849/**
850 * @brief Get the Timing Prescaler setting.
851 * @rmtoll TIMINGR PRESC LL_FMPI2C_GetTimingPrescaler
852 * @param FMPI2Cx FMPI2C Instance.
853 * @retval Value between Min_Data=0x0 and Max_Data=0xF
854 */
855__STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(FMPI2C_TypeDef *FMPI2Cx)
856{
857 return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_PRESC) >> FMPI2C_TIMINGR_PRESC_Pos);
858}
859
860/**
861 * @brief Get the SCL low period setting.
862 * @rmtoll TIMINGR SCLL LL_FMPI2C_GetClockLowPeriod
863 * @param FMPI2Cx FMPI2C Instance.
864 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
865 */
866__STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(FMPI2C_TypeDef *FMPI2Cx)
867{
868 return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLL) >> FMPI2C_TIMINGR_SCLL_Pos);
869}
870
871/**
872 * @brief Get the SCL high period setting.
873 * @rmtoll TIMINGR SCLH LL_FMPI2C_GetClockHighPeriod
874 * @param FMPI2Cx FMPI2C Instance.
875 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
876 */
877__STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(FMPI2C_TypeDef *FMPI2Cx)
878{
879 return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLH) >> FMPI2C_TIMINGR_SCLH_Pos);
880}
881
882/**
883 * @brief Get the SDA hold time.
884 * @rmtoll TIMINGR SDADEL LL_FMPI2C_GetDataHoldTime
885 * @param FMPI2Cx FMPI2C Instance.
886 * @retval Value between Min_Data=0x0 and Max_Data=0xF
887 */
888__STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(FMPI2C_TypeDef *FMPI2Cx)
889{
890 return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SDADEL) >> FMPI2C_TIMINGR_SDADEL_Pos);
891}
892
893/**
894 * @brief Get the SDA setup time.
895 * @rmtoll TIMINGR SCLDEL LL_FMPI2C_GetDataSetupTime
896 * @param FMPI2Cx FMPI2C Instance.
897 * @retval Value between Min_Data=0x0 and Max_Data=0xF
898 */
899__STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef *FMPI2Cx)
900{
901 return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLDEL) >> FMPI2C_TIMINGR_SCLDEL_Pos);
902}
903
904/**
905 * @brief Configure peripheral mode.
906 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
907 * SMBus feature is supported by the FMPI2Cx Instance.
908 * @rmtoll CR1 SMBHEN LL_FMPI2C_SetMode\n
909 * CR1 SMBDEN LL_FMPI2C_SetMode
910 * @param FMPI2Cx FMPI2C Instance.
911 * @param PeripheralMode This parameter can be one of the following values:
912 * @arg @ref LL_FMPI2C_MODE_I2C
913 * @arg @ref LL_FMPI2C_MODE_SMBUS_HOST
914 * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE
915 * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP
916 * @retval None
917 */
918__STATIC_INLINE void LL_FMPI2C_SetMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t PeripheralMode)
919{
920 MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN, PeripheralMode);
921}
922
923/**
924 * @brief Get peripheral mode.
925 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
926 * SMBus feature is supported by the FMPI2Cx Instance.
927 * @rmtoll CR1 SMBHEN LL_FMPI2C_GetMode\n
928 * CR1 SMBDEN LL_FMPI2C_GetMode
929 * @param FMPI2Cx FMPI2C Instance.
930 * @retval Returned value can be one of the following values:
931 * @arg @ref LL_FMPI2C_MODE_I2C
932 * @arg @ref LL_FMPI2C_MODE_SMBUS_HOST
933 * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE
934 * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP
935 */
936__STATIC_INLINE uint32_t LL_FMPI2C_GetMode(FMPI2C_TypeDef *FMPI2Cx)
937{
938 return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN));
939}
940
941/**
942 * @brief Enable SMBus alert (Host or Device mode)
943 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
944 * SMBus feature is supported by the FMPI2Cx Instance.
945 * @note SMBus Device mode:
946 * - SMBus Alert pin is drived low and
947 * Alert Response Address Header acknowledge is enabled.
948 * SMBus Host mode:
949 * - SMBus Alert pin management is supported.
950 * @rmtoll CR1 ALERTEN LL_FMPI2C_EnableSMBusAlert
951 * @param FMPI2Cx FMPI2C Instance.
952 * @retval None
953 */
954__STATIC_INLINE void LL_FMPI2C_EnableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
955{
956 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN);
957}
958
959/**
960 * @brief Disable SMBus alert (Host or Device mode)
961 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
962 * SMBus feature is supported by the FMPI2Cx Instance.
963 * @note SMBus Device mode:
964 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
965 * Alert Response Address Header acknowledge is disabled.
966 * SMBus Host mode:
967 * - SMBus Alert pin management is not supported.
968 * @rmtoll CR1 ALERTEN LL_FMPI2C_DisableSMBusAlert
969 * @param FMPI2Cx FMPI2C Instance.
970 * @retval None
971 */
972__STATIC_INLINE void LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
973{
974 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN);
975}
976
977/**
978 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
979 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
980 * SMBus feature is supported by the FMPI2Cx Instance.
981 * @rmtoll CR1 ALERTEN LL_FMPI2C_IsEnabledSMBusAlert
982 * @param FMPI2Cx FMPI2C Instance.
983 * @retval State of bit (1 or 0).
984 */
985__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
986{
987 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN) == (FMPI2C_CR1_ALERTEN)) ? 1UL : 0UL);
988}
989
990/**
991 * @brief Enable SMBus Packet Error Calculation (PEC).
992 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
993 * SMBus feature is supported by the FMPI2Cx Instance.
994 * @rmtoll CR1 PECEN LL_FMPI2C_EnableSMBusPEC
995 * @param FMPI2Cx FMPI2C Instance.
996 * @retval None
997 */
998__STATIC_INLINE void LL_FMPI2C_EnableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
999{
1000 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN);
1001}
1002
1003/**
1004 * @brief Disable SMBus Packet Error Calculation (PEC).
1005 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1006 * SMBus feature is supported by the FMPI2Cx Instance.
1007 * @rmtoll CR1 PECEN LL_FMPI2C_DisableSMBusPEC
1008 * @param FMPI2Cx FMPI2C Instance.
1009 * @retval None
1010 */
1011__STATIC_INLINE void LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
1012{
1013 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN);
1014}
1015
1016/**
1017 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1018 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1019 * SMBus feature is supported by the FMPI2Cx Instance.
1020 * @rmtoll CR1 PECEN LL_FMPI2C_IsEnabledSMBusPEC
1021 * @param FMPI2Cx FMPI2C Instance.
1022 * @retval State of bit (1 or 0).
1023 */
1024__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
1025{
1026 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN) == (FMPI2C_CR1_PECEN)) ? 1UL : 0UL);
1027}
1028
1029/**
1030 * @brief Configure the SMBus Clock Timeout.
1031 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1032 * SMBus feature is supported by the FMPI2Cx Instance.
1033 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1034 * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_ConfigSMBusTimeout\n
1035 * TIMEOUTR TIDLE LL_FMPI2C_ConfigSMBusTimeout\n
1036 * TIMEOUTR TIMEOUTB LL_FMPI2C_ConfigSMBusTimeout
1037 * @param FMPI2Cx FMPI2C Instance.
1038 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1039 * @param TimeoutAMode This parameter can be one of the following values:
1040 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1041 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1042 * @param TimeoutB
1043 * @retval None
1044 */
1045__STATIC_INLINE void LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1046 uint32_t TimeoutB)
1047{
1048 MODIFY_REG(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA | FMPI2C_TIMEOUTR_TIDLE | FMPI2C_TIMEOUTR_TIMEOUTB,
1049 TimeoutA | TimeoutAMode | (TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos));
1050}
1051
1052/**
1053 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1054 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1055 * SMBus feature is supported by the FMPI2Cx Instance.
1056 * @note These bits can only be programmed when TimeoutA is disabled.
1057 * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_SetSMBusTimeoutA
1058 * @param FMPI2Cx FMPI2C Instance.
1059 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1060 * @retval None
1061 */
1062__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA)
1063{
1064 WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutA);
1065}
1066
1067/**
1068 * @brief Get the SMBus Clock TimeoutA setting.
1069 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1070 * SMBus feature is supported by the FMPI2Cx Instance.
1071 * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_GetSMBusTimeoutA
1072 * @param FMPI2Cx FMPI2C Instance.
1073 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1074 */
1075__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx)
1076{
1077 return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA));
1078}
1079
1080/**
1081 * @brief Set the SMBus Clock TimeoutA mode.
1082 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1083 * SMBus feature is supported by the FMPI2Cx Instance.
1084 * @note This bit can only be programmed when TimeoutA is disabled.
1085 * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_SetSMBusTimeoutAMode
1086 * @param FMPI2Cx FMPI2C Instance.
1087 * @param TimeoutAMode This parameter can be one of the following values:
1088 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1089 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1090 * @retval None
1091 */
1092__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutAMode)
1093{
1094 WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutAMode);
1095}
1096
1097/**
1098 * @brief Get the SMBus Clock TimeoutA mode.
1099 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1100 * SMBus feature is supported by the FMPI2Cx Instance.
1101 * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_GetSMBusTimeoutAMode
1102 * @param FMPI2Cx FMPI2C Instance.
1103 * @retval Returned value can be one of the following values:
1104 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1105 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1106 */
1107__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx)
1108{
1109 return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIDLE));
1110}
1111
1112/**
1113 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1114 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1115 * SMBus feature is supported by the FMPI2Cx Instance.
1116 * @note These bits can only be programmed when TimeoutB is disabled.
1117 * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_SetSMBusTimeoutB
1118 * @param FMPI2Cx FMPI2C Instance.
1119 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1120 * @retval None
1121 */
1122__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutB)
1123{
1124 WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos);
1125}
1126
1127/**
1128 * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
1129 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1130 * SMBus feature is supported by the FMPI2Cx Instance.
1131 * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_GetSMBusTimeoutB
1132 * @param FMPI2Cx FMPI2C Instance.
1133 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1134 */
1135__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx)
1136{
1137 return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTB) >> FMPI2C_TIMEOUTR_TIMEOUTB_Pos);
1138}
1139
1140/**
1141 * @brief Enable the SMBus Clock Timeout.
1142 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1143 * SMBus feature is supported by the FMPI2Cx Instance.
1144 * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_EnableSMBusTimeout\n
1145 * TIMEOUTR TEXTEN LL_FMPI2C_EnableSMBusTimeout
1146 * @param FMPI2Cx FMPI2C Instance.
1147 * @param ClockTimeout This parameter can be one of the following values:
1148 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
1149 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
1150 * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
1151 * @retval None
1152 */
1153__STATIC_INLINE void LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
1154{
1155 SET_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout);
1156}
1157
1158/**
1159 * @brief Disable the SMBus Clock Timeout.
1160 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1161 * SMBus feature is supported by the FMPI2Cx Instance.
1162 * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_DisableSMBusTimeout\n
1163 * TIMEOUTR TEXTEN LL_FMPI2C_DisableSMBusTimeout
1164 * @param FMPI2Cx FMPI2C Instance.
1165 * @param ClockTimeout This parameter can be one of the following values:
1166 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
1167 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
1168 * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
1169 * @retval None
1170 */
1171__STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
1172{
1173 CLEAR_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout);
1174}
1175
1176/**
1177 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1178 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1179 * SMBus feature is supported by the FMPI2Cx Instance.
1180 * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_IsEnabledSMBusTimeout\n
1181 * TIMEOUTR TEXTEN LL_FMPI2C_IsEnabledSMBusTimeout
1182 * @param FMPI2Cx FMPI2C Instance.
1183 * @param ClockTimeout This parameter can be one of the following values:
1184 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
1185 * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
1186 * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
1187 * @retval State of bit (1 or 0).
1188 */
1189__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
1190{
1191 return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
1192}
1193
1194/**
1195 * @}
1196 */
1197
1198/** @defgroup FMPI2C_LL_EF_IT_Management IT_Management
1199 * @{
1200 */
1201
1202/**
1203 * @brief Enable TXIS interrupt.
1204 * @rmtoll CR1 TXIE LL_FMPI2C_EnableIT_TX
1205 * @param FMPI2Cx FMPI2C Instance.
1206 * @retval None
1207 */
1208__STATIC_INLINE void LL_FMPI2C_EnableIT_TX(FMPI2C_TypeDef *FMPI2Cx)
1209{
1210 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE);
1211}
1212
1213/**
1214 * @brief Disable TXIS interrupt.
1215 * @rmtoll CR1 TXIE LL_FMPI2C_DisableIT_TX
1216 * @param FMPI2Cx FMPI2C Instance.
1217 * @retval None
1218 */
1219__STATIC_INLINE void LL_FMPI2C_DisableIT_TX(FMPI2C_TypeDef *FMPI2Cx)
1220{
1221 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE);
1222}
1223
1224/**
1225 * @brief Check if the TXIS Interrupt is enabled or disabled.
1226 * @rmtoll CR1 TXIE LL_FMPI2C_IsEnabledIT_TX
1227 * @param FMPI2Cx FMPI2C Instance.
1228 * @retval State of bit (1 or 0).
1229 */
1230__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TX(FMPI2C_TypeDef *FMPI2Cx)
1231{
1232 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE) == (FMPI2C_CR1_TXIE)) ? 1UL : 0UL);
1233}
1234
1235/**
1236 * @brief Enable RXNE interrupt.
1237 * @rmtoll CR1 RXIE LL_FMPI2C_EnableIT_RX
1238 * @param FMPI2Cx FMPI2C Instance.
1239 * @retval None
1240 */
1241__STATIC_INLINE void LL_FMPI2C_EnableIT_RX(FMPI2C_TypeDef *FMPI2Cx)
1242{
1243 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE);
1244}
1245
1246/**
1247 * @brief Disable RXNE interrupt.
1248 * @rmtoll CR1 RXIE LL_FMPI2C_DisableIT_RX
1249 * @param FMPI2Cx FMPI2C Instance.
1250 * @retval None
1251 */
1252__STATIC_INLINE void LL_FMPI2C_DisableIT_RX(FMPI2C_TypeDef *FMPI2Cx)
1253{
1254 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE);
1255}
1256
1257/**
1258 * @brief Check if the RXNE Interrupt is enabled or disabled.
1259 * @rmtoll CR1 RXIE LL_FMPI2C_IsEnabledIT_RX
1260 * @param FMPI2Cx FMPI2C Instance.
1261 * @retval State of bit (1 or 0).
1262 */
1263__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_RX(FMPI2C_TypeDef *FMPI2Cx)
1264{
1265 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE) == (FMPI2C_CR1_RXIE)) ? 1UL : 0UL);
1266}
1267
1268/**
1269 * @brief Enable Address match interrupt (slave mode only).
1270 * @rmtoll CR1 ADDRIE LL_FMPI2C_EnableIT_ADDR
1271 * @param FMPI2Cx FMPI2C Instance.
1272 * @retval None
1273 */
1274__STATIC_INLINE void LL_FMPI2C_EnableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
1275{
1276 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE);
1277}
1278
1279/**
1280 * @brief Disable Address match interrupt (slave mode only).
1281 * @rmtoll CR1 ADDRIE LL_FMPI2C_DisableIT_ADDR
1282 * @param FMPI2Cx FMPI2C Instance.
1283 * @retval None
1284 */
1285__STATIC_INLINE void LL_FMPI2C_DisableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
1286{
1287 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE);
1288}
1289
1290/**
1291 * @brief Check if Address match interrupt is enabled or disabled.
1292 * @rmtoll CR1 ADDRIE LL_FMPI2C_IsEnabledIT_ADDR
1293 * @param FMPI2Cx FMPI2C Instance.
1294 * @retval State of bit (1 or 0).
1295 */
1296__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
1297{
1298 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE) == (FMPI2C_CR1_ADDRIE)) ? 1UL : 0UL);
1299}
1300
1301/**
1302 * @brief Enable Not acknowledge received interrupt.
1303 * @rmtoll CR1 NACKIE LL_FMPI2C_EnableIT_NACK
1304 * @param FMPI2Cx FMPI2C Instance.
1305 * @retval None
1306 */
1307__STATIC_INLINE void LL_FMPI2C_EnableIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
1308{
1309 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE);
1310}
1311
1312/**
1313 * @brief Disable Not acknowledge received interrupt.
1314 * @rmtoll CR1 NACKIE LL_FMPI2C_DisableIT_NACK
1315 * @param FMPI2Cx FMPI2C Instance.
1316 * @retval None
1317 */
1318__STATIC_INLINE void LL_FMPI2C_DisableIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
1319{
1320 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE);
1321}
1322
1323/**
1324 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1325 * @rmtoll CR1 NACKIE LL_FMPI2C_IsEnabledIT_NACK
1326 * @param FMPI2Cx FMPI2C Instance.
1327 * @retval State of bit (1 or 0).
1328 */
1329__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
1330{
1331 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE) == (FMPI2C_CR1_NACKIE)) ? 1UL : 0UL);
1332}
1333
1334/**
1335 * @brief Enable STOP detection interrupt.
1336 * @rmtoll CR1 STOPIE LL_FMPI2C_EnableIT_STOP
1337 * @param FMPI2Cx FMPI2C Instance.
1338 * @retval None
1339 */
1340__STATIC_INLINE void LL_FMPI2C_EnableIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
1341{
1342 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE);
1343}
1344
1345/**
1346 * @brief Disable STOP detection interrupt.
1347 * @rmtoll CR1 STOPIE LL_FMPI2C_DisableIT_STOP
1348 * @param FMPI2Cx FMPI2C Instance.
1349 * @retval None
1350 */
1351__STATIC_INLINE void LL_FMPI2C_DisableIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
1352{
1353 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE);
1354}
1355
1356/**
1357 * @brief Check if STOP detection interrupt is enabled or disabled.
1358 * @rmtoll CR1 STOPIE LL_FMPI2C_IsEnabledIT_STOP
1359 * @param FMPI2Cx FMPI2C Instance.
1360 * @retval State of bit (1 or 0).
1361 */
1362__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
1363{
1364 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE) == (FMPI2C_CR1_STOPIE)) ? 1UL : 0UL);
1365}
1366
1367/**
1368 * @brief Enable Transfer Complete interrupt.
1369 * @note Any of these events will generate interrupt :
1370 * Transfer Complete (TC)
1371 * Transfer Complete Reload (TCR)
1372 * @rmtoll CR1 TCIE LL_FMPI2C_EnableIT_TC
1373 * @param FMPI2Cx FMPI2C Instance.
1374 * @retval None
1375 */
1376__STATIC_INLINE void LL_FMPI2C_EnableIT_TC(FMPI2C_TypeDef *FMPI2Cx)
1377{
1378 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE);
1379}
1380
1381/**
1382 * @brief Disable Transfer Complete interrupt.
1383 * @note Any of these events will generate interrupt :
1384 * Transfer Complete (TC)
1385 * Transfer Complete Reload (TCR)
1386 * @rmtoll CR1 TCIE LL_FMPI2C_DisableIT_TC
1387 * @param FMPI2Cx FMPI2C Instance.
1388 * @retval None
1389 */
1390__STATIC_INLINE void LL_FMPI2C_DisableIT_TC(FMPI2C_TypeDef *FMPI2Cx)
1391{
1392 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE);
1393}
1394
1395/**
1396 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1397 * @rmtoll CR1 TCIE LL_FMPI2C_IsEnabledIT_TC
1398 * @param FMPI2Cx FMPI2C Instance.
1399 * @retval State of bit (1 or 0).
1400 */
1401__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef *FMPI2Cx)
1402{
1403 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE) == (FMPI2C_CR1_TCIE)) ? 1UL : 0UL);
1404}
1405
1406/**
1407 * @brief Enable Error interrupts.
1408 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1409 * SMBus feature is supported by the FMPI2Cx Instance.
1410 * @note Any of these errors will generate interrupt :
1411 * Arbitration Loss (ARLO)
1412 * Bus Error detection (BERR)
1413 * Overrun/Underrun (OVR)
1414 * SMBus Timeout detection (TIMEOUT)
1415 * SMBus PEC error detection (PECERR)
1416 * SMBus Alert pin event detection (ALERT)
1417 * @rmtoll CR1 ERRIE LL_FMPI2C_EnableIT_ERR
1418 * @param FMPI2Cx FMPI2C Instance.
1419 * @retval None
1420 */
1421__STATIC_INLINE void LL_FMPI2C_EnableIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
1422{
1423 SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE);
1424}
1425
1426/**
1427 * @brief Disable Error interrupts.
1428 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1429 * SMBus feature is supported by the FMPI2Cx Instance.
1430 * @note Any of these errors will generate interrupt :
1431 * Arbitration Loss (ARLO)
1432 * Bus Error detection (BERR)
1433 * Overrun/Underrun (OVR)
1434 * SMBus Timeout detection (TIMEOUT)
1435 * SMBus PEC error detection (PECERR)
1436 * SMBus Alert pin event detection (ALERT)
1437 * @rmtoll CR1 ERRIE LL_FMPI2C_DisableIT_ERR
1438 * @param FMPI2Cx FMPI2C Instance.
1439 * @retval None
1440 */
1441__STATIC_INLINE void LL_FMPI2C_DisableIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
1442{
1443 CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE);
1444}
1445
1446/**
1447 * @brief Check if Error interrupts are enabled or disabled.
1448 * @rmtoll CR1 ERRIE LL_FMPI2C_IsEnabledIT_ERR
1449 * @param FMPI2Cx FMPI2C Instance.
1450 * @retval State of bit (1 or 0).
1451 */
1452__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
1453{
1454 return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE) == (FMPI2C_CR1_ERRIE)) ? 1UL : 0UL);
1455}
1456
1457/**
1458 * @}
1459 */
1460
1461/** @defgroup FMPI2C_LL_EF_FLAG_management FLAG_management
1462 * @{
1463 */
1464
1465/**
1466 * @brief Indicate the status of Transmit data register empty flag.
1467 * @note RESET: When next data is written in Transmit data register.
1468 * SET: When Transmit data register is empty.
1469 * @rmtoll ISR TXE LL_FMPI2C_IsActiveFlag_TXE
1470 * @param FMPI2Cx FMPI2C Instance.
1471 * @retval State of bit (1 or 0).
1472 */
1473__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(FMPI2C_TypeDef *FMPI2Cx)
1474{
1475 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXE) == (FMPI2C_ISR_TXE)) ? 1UL : 0UL);
1476}
1477
1478/**
1479 * @brief Indicate the status of Transmit interrupt flag.
1480 * @note RESET: When next data is written in Transmit data register.
1481 * SET: When Transmit data register is empty.
1482 * @rmtoll ISR TXIS LL_FMPI2C_IsActiveFlag_TXIS
1483 * @param FMPI2Cx FMPI2C Instance.
1484 * @retval State of bit (1 or 0).
1485 */
1486__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(FMPI2C_TypeDef *FMPI2Cx)
1487{
1488 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXIS) == (FMPI2C_ISR_TXIS)) ? 1UL : 0UL);
1489}
1490
1491/**
1492 * @brief Indicate the status of Receive data register not empty flag.
1493 * @note RESET: When Receive data register is read.
1494 * SET: When the received data is copied in Receive data register.
1495 * @rmtoll ISR RXNE LL_FMPI2C_IsActiveFlag_RXNE
1496 * @param FMPI2Cx FMPI2C Instance.
1497 * @retval State of bit (1 or 0).
1498 */
1499__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(FMPI2C_TypeDef *FMPI2Cx)
1500{
1501 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_RXNE) == (FMPI2C_ISR_RXNE)) ? 1UL : 0UL);
1502}
1503
1504/**
1505 * @brief Indicate the status of Address matched flag (slave mode).
1506 * @note RESET: Clear default value.
1507 * SET: When the received slave address matched with one of the enabled slave address.
1508 * @rmtoll ISR ADDR LL_FMPI2C_IsActiveFlag_ADDR
1509 * @param FMPI2Cx FMPI2C Instance.
1510 * @retval State of bit (1 or 0).
1511 */
1512__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx)
1513{
1514 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDR) == (FMPI2C_ISR_ADDR)) ? 1UL : 0UL);
1515}
1516
1517/**
1518 * @brief Indicate the status of Not Acknowledge received flag.
1519 * @note RESET: Clear default value.
1520 * SET: When a NACK is received after a byte transmission.
1521 * @rmtoll ISR NACKF LL_FMPI2C_IsActiveFlag_NACK
1522 * @param FMPI2Cx FMPI2C Instance.
1523 * @retval State of bit (1 or 0).
1524 */
1525__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(FMPI2C_TypeDef *FMPI2Cx)
1526{
1527 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_NACKF) == (FMPI2C_ISR_NACKF)) ? 1UL : 0UL);
1528}
1529
1530/**
1531 * @brief Indicate the status of Stop detection flag.
1532 * @note RESET: Clear default value.
1533 * SET: When a Stop condition is detected.
1534 * @rmtoll ISR STOPF LL_FMPI2C_IsActiveFlag_STOP
1535 * @param FMPI2Cx FMPI2C Instance.
1536 * @retval State of bit (1 or 0).
1537 */
1538__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(FMPI2C_TypeDef *FMPI2Cx)
1539{
1540 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_STOPF) == (FMPI2C_ISR_STOPF)) ? 1UL : 0UL);
1541}
1542
1543/**
1544 * @brief Indicate the status of Transfer complete flag (master mode).
1545 * @note RESET: Clear default value.
1546 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1547 * @rmtoll ISR TC LL_FMPI2C_IsActiveFlag_TC
1548 * @param FMPI2Cx FMPI2C Instance.
1549 * @retval State of bit (1 or 0).
1550 */
1551__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(FMPI2C_TypeDef *FMPI2Cx)
1552{
1553 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TC) == (FMPI2C_ISR_TC)) ? 1UL : 0UL);
1554}
1555
1556/**
1557 * @brief Indicate the status of Transfer complete flag (master mode).
1558 * @note RESET: Clear default value.
1559 * SET: When RELOAD=1 and NBYTES date have been transferred.
1560 * @rmtoll ISR TCR LL_FMPI2C_IsActiveFlag_TCR
1561 * @param FMPI2Cx FMPI2C Instance.
1562 * @retval State of bit (1 or 0).
1563 */
1564__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(FMPI2C_TypeDef *FMPI2Cx)
1565{
1566 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TCR) == (FMPI2C_ISR_TCR)) ? 1UL : 0UL);
1567}
1568
1569/**
1570 * @brief Indicate the status of Bus error flag.
1571 * @note RESET: Clear default value.
1572 * SET: When a misplaced Start or Stop condition is detected.
1573 * @rmtoll ISR BERR LL_FMPI2C_IsActiveFlag_BERR
1574 * @param FMPI2Cx FMPI2C Instance.
1575 * @retval State of bit (1 or 0).
1576 */
1577__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(FMPI2C_TypeDef *FMPI2Cx)
1578{
1579 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BERR) == (FMPI2C_ISR_BERR)) ? 1UL : 0UL);
1580}
1581
1582/**
1583 * @brief Indicate the status of Arbitration lost flag.
1584 * @note RESET: Clear default value.
1585 * SET: When arbitration lost.
1586 * @rmtoll ISR ARLO LL_FMPI2C_IsActiveFlag_ARLO
1587 * @param FMPI2Cx FMPI2C Instance.
1588 * @retval State of bit (1 or 0).
1589 */
1590__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx)
1591{
1592 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ARLO) == (FMPI2C_ISR_ARLO)) ? 1UL : 0UL);
1593}
1594
1595/**
1596 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1597 * @note RESET: Clear default value.
1598 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1599 * @rmtoll ISR OVR LL_FMPI2C_IsActiveFlag_OVR
1600 * @param FMPI2Cx FMPI2C Instance.
1601 * @retval State of bit (1 or 0).
1602 */
1603__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx)
1604{
1605 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_OVR) == (FMPI2C_ISR_OVR)) ? 1UL : 0UL);
1606}
1607
1608/**
1609 * @brief Indicate the status of SMBus PEC error flag in reception.
1610 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1611 * SMBus feature is supported by the FMPI2Cx Instance.
1612 * @note RESET: Clear default value.
1613 * SET: When the received PEC does not match with the PEC register content.
1614 * @rmtoll ISR PECERR LL_FMPI2C_IsActiveSMBusFlag_PECERR
1615 * @param FMPI2Cx FMPI2C Instance.
1616 * @retval State of bit (1 or 0).
1617 */
1618__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx)
1619{
1620 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_PECERR) == (FMPI2C_ISR_PECERR)) ? 1UL : 0UL);
1621}
1622
1623/**
1624 * @brief Indicate the status of SMBus Timeout detection flag.
1625 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1626 * SMBus feature is supported by the FMPI2Cx Instance.
1627 * @note RESET: Clear default value.
1628 * SET: When a timeout or extended clock timeout occurs.
1629 * @rmtoll ISR TIMEOUT LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT
1630 * @param FMPI2Cx FMPI2C Instance.
1631 * @retval State of bit (1 or 0).
1632 */
1633__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx)
1634{
1635 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TIMEOUT) == (FMPI2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1636}
1637
1638/**
1639 * @brief Indicate the status of SMBus alert flag.
1640 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1641 * SMBus feature is supported by the FMPI2Cx Instance.
1642 * @note RESET: Clear default value.
1643 * SET: When SMBus host configuration, SMBus alert enabled and
1644 * a falling edge event occurs on SMBA pin.
1645 * @rmtoll ISR ALERT LL_FMPI2C_IsActiveSMBusFlag_ALERT
1646 * @param FMPI2Cx FMPI2C Instance.
1647 * @retval State of bit (1 or 0).
1648 */
1649__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx)
1650{
1651 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ALERT) == (FMPI2C_ISR_ALERT)) ? 1UL : 0UL);
1652}
1653
1654/**
1655 * @brief Indicate the status of Bus Busy flag.
1656 * @note RESET: Clear default value.
1657 * SET: When a Start condition is detected.
1658 * @rmtoll ISR BUSY LL_FMPI2C_IsActiveFlag_BUSY
1659 * @param FMPI2Cx FMPI2C Instance.
1660 * @retval State of bit (1 or 0).
1661 */
1662__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BUSY(FMPI2C_TypeDef *FMPI2Cx)
1663{
1664 return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BUSY) == (FMPI2C_ISR_BUSY)) ? 1UL : 0UL);
1665}
1666
1667/**
1668 * @brief Clear Address Matched flag.
1669 * @rmtoll ICR ADDRCF LL_FMPI2C_ClearFlag_ADDR
1670 * @param FMPI2Cx FMPI2C Instance.
1671 * @retval None
1672 */
1673__STATIC_INLINE void LL_FMPI2C_ClearFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx)
1674{
1675 SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ADDRCF);
1676}
1677
1678/**
1679 * @brief Clear Not Acknowledge flag.
1680 * @rmtoll ICR NACKCF LL_FMPI2C_ClearFlag_NACK
1681 * @param FMPI2Cx FMPI2C Instance.
1682 * @retval None
1683 */
1684__STATIC_INLINE void LL_FMPI2C_ClearFlag_NACK(FMPI2C_TypeDef *FMPI2Cx)
1685{
1686 SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_NACKCF);
1687}
1688
1689/**
1690 * @brief Clear Stop detection flag.
1691 * @rmtoll ICR STOPCF LL_FMPI2C_ClearFlag_STOP
1692 * @param FMPI2Cx FMPI2C Instance.
1693 * @retval None
1694 */
1695__STATIC_INLINE void LL_FMPI2C_ClearFlag_STOP(FMPI2C_TypeDef *FMPI2Cx)
1696{
1697 SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_STOPCF);
1698}
1699
1700/**
1701 * @brief Clear Transmit data register empty flag (TXE).
1702 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1703 * @rmtoll ISR TXE LL_FMPI2C_ClearFlag_TXE
1704 * @param FMPI2Cx FMPI2C Instance.
1705 * @retval None
1706 */
1707__STATIC_INLINE void LL_FMPI2C_ClearFlag_TXE(FMPI2C_TypeDef *FMPI2Cx)
1708{
1709 WRITE_REG(FMPI2Cx->ISR, FMPI2C_ISR_TXE);
1710}
1711
1712/**
1713 * @brief Clear Bus error flag.
1714 * @rmtoll ICR BERRCF LL_FMPI2C_ClearFlag_BERR
1715 * @param FMPI2Cx FMPI2C Instance.
1716 * @retval None
1717 */
1718__STATIC_INLINE void LL_FMPI2C_ClearFlag_BERR(FMPI2C_TypeDef *FMPI2Cx)
1719{
1720 SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_BERRCF);
1721}
1722
1723/**
1724 * @brief Clear Arbitration lost flag.
1725 * @rmtoll ICR ARLOCF LL_FMPI2C_ClearFlag_ARLO
1726 * @param FMPI2Cx FMPI2C Instance.
1727 * @retval None
1728 */
1729__STATIC_INLINE void LL_FMPI2C_ClearFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx)
1730{
1731 SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ARLOCF);
1732}
1733
1734/**
1735 * @brief Clear Overrun/Underrun flag.
1736 * @rmtoll ICR OVRCF LL_FMPI2C_ClearFlag_OVR
1737 * @param FMPI2Cx FMPI2C Instance.
1738 * @retval None
1739 */
1740__STATIC_INLINE void LL_FMPI2C_ClearFlag_OVR(FMPI2C_TypeDef *FMPI2Cx)
1741{
1742 SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_OVRCF);
1743}
1744
1745/**
1746 * @brief Clear SMBus PEC error flag.
1747 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1748 * SMBus feature is supported by the FMPI2Cx Instance.
1749 * @rmtoll ICR PECCF LL_FMPI2C_ClearSMBusFlag_PECERR
1750 * @param FMPI2Cx FMPI2C Instance.
1751 * @retval None
1752 */
1753__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx)
1754{
1755 SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_PECCF);
1756}
1757
1758/**
1759 * @brief Clear SMBus Timeout detection flag.
1760 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1761 * SMBus feature is supported by the FMPI2Cx Instance.
1762 * @rmtoll ICR TIMOUTCF LL_FMPI2C_ClearSMBusFlag_TIMEOUT
1763 * @param FMPI2Cx FMPI2C Instance.
1764 * @retval None
1765 */
1766__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx)
1767{
1768 SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_TIMOUTCF);
1769}
1770
1771/**
1772 * @brief Clear SMBus Alert flag.
1773 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1774 * SMBus feature is supported by the FMPI2Cx Instance.
1775 * @rmtoll ICR ALERTCF LL_FMPI2C_ClearSMBusFlag_ALERT
1776 * @param FMPI2Cx FMPI2C Instance.
1777 * @retval None
1778 */
1779__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx)
1780{
1781 SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ALERTCF);
1782}
1783
1784/**
1785 * @}
1786 */
1787
1788/** @defgroup FMPI2C_LL_EF_Data_Management Data_Management
1789 * @{
1790 */
1791
1792/**
1793 * @brief Enable automatic STOP condition generation (master mode).
1794 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1795 * This bit has no effect in slave mode or when RELOAD bit is set.
1796 * @rmtoll CR2 AUTOEND LL_FMPI2C_EnableAutoEndMode
1797 * @param FMPI2Cx FMPI2C Instance.
1798 * @retval None
1799 */
1800__STATIC_INLINE void LL_FMPI2C_EnableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
1801{
1802 SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND);
1803}
1804
1805/**
1806 * @brief Disable automatic STOP condition generation (master mode).
1807 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1808 * @rmtoll CR2 AUTOEND LL_FMPI2C_DisableAutoEndMode
1809 * @param FMPI2Cx FMPI2C Instance.
1810 * @retval None
1811 */
1812__STATIC_INLINE void LL_FMPI2C_DisableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
1813{
1814 CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND);
1815}
1816
1817/**
1818 * @brief Check if automatic STOP condition is enabled or disabled.
1819 * @rmtoll CR2 AUTOEND LL_FMPI2C_IsEnabledAutoEndMode
1820 * @param FMPI2Cx FMPI2C Instance.
1821 * @retval State of bit (1 or 0).
1822 */
1823__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
1824{
1825 return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND) == (FMPI2C_CR2_AUTOEND)) ? 1UL : 0UL);
1826}
1827
1828/**
1829 * @brief Enable reload mode (master mode).
1830 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
1831 * @rmtoll CR2 RELOAD LL_FMPI2C_EnableReloadMode
1832 * @param FMPI2Cx FMPI2C Instance.
1833 * @retval None
1834 */
1835__STATIC_INLINE void LL_FMPI2C_EnableReloadMode(FMPI2C_TypeDef *FMPI2Cx)
1836{
1837 SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD);
1838}
1839
1840/**
1841 * @brief Disable reload mode (master mode).
1842 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
1843 * @rmtoll CR2 RELOAD LL_FMPI2C_DisableReloadMode
1844 * @param FMPI2Cx FMPI2C Instance.
1845 * @retval None
1846 */
1847__STATIC_INLINE void LL_FMPI2C_DisableReloadMode(FMPI2C_TypeDef *FMPI2Cx)
1848{
1849 CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD);
1850}
1851
1852/**
1853 * @brief Check if reload mode is enabled or disabled.
1854 * @rmtoll CR2 RELOAD LL_FMPI2C_IsEnabledReloadMode
1855 * @param FMPI2Cx FMPI2C Instance.
1856 * @retval State of bit (1 or 0).
1857 */
1858__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledReloadMode(FMPI2C_TypeDef *FMPI2Cx)
1859{
1860 return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD) == (FMPI2C_CR2_RELOAD)) ? 1UL : 0UL);
1861}
1862
1863/**
1864 * @brief Configure the number of bytes for transfer.
1865 * @note Changing these bits when START bit is set is not allowed.
1866 * @rmtoll CR2 NBYTES LL_FMPI2C_SetTransferSize
1867 * @param FMPI2Cx FMPI2C Instance.
1868 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
1869 * @retval None
1870 */
1871__STATIC_INLINE void LL_FMPI2C_SetTransferSize(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferSize)
1872{
1873 MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES, TransferSize << FMPI2C_CR2_NBYTES_Pos);
1874}
1875
1876/**
1877 * @brief Get the number of bytes configured for transfer.
1878 * @rmtoll CR2 NBYTES LL_FMPI2C_GetTransferSize
1879 * @param FMPI2Cx FMPI2C Instance.
1880 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1881 */
1882__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(FMPI2C_TypeDef *FMPI2Cx)
1883{
1884 return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES) >> FMPI2C_CR2_NBYTES_Pos);
1885}
1886
1887/**
1888 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
1889 * @note Usage in Slave mode only.
1890 * @rmtoll CR2 NACK LL_FMPI2C_AcknowledgeNextData
1891 * @param FMPI2Cx FMPI2C Instance.
1892 * @param TypeAcknowledge This parameter can be one of the following values:
1893 * @arg @ref LL_FMPI2C_ACK
1894 * @arg @ref LL_FMPI2C_NACK
1895 * @retval None
1896 */
1897__STATIC_INLINE void LL_FMPI2C_AcknowledgeNextData(FMPI2C_TypeDef *FMPI2Cx, uint32_t TypeAcknowledge)
1898{
1899 MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NACK, TypeAcknowledge);
1900}
1901
1902/**
1903 * @brief Generate a START or RESTART condition
1904 * @note The START bit can be set even if bus is BUSY or FMPI2C is in slave mode.
1905 * This action has no effect when RELOAD is set.
1906 * @rmtoll CR2 START LL_FMPI2C_GenerateStartCondition
1907 * @param FMPI2Cx FMPI2C Instance.
1908 * @retval None
1909 */
1910__STATIC_INLINE void LL_FMPI2C_GenerateStartCondition(FMPI2C_TypeDef *FMPI2Cx)
1911{
1912 SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_START);
1913}
1914
1915/**
1916 * @brief Generate a STOP condition after the current byte transfer (master mode).
1917 * @rmtoll CR2 STOP LL_FMPI2C_GenerateStopCondition
1918 * @param FMPI2Cx FMPI2C Instance.
1919 * @retval None
1920 */
1921__STATIC_INLINE void LL_FMPI2C_GenerateStopCondition(FMPI2C_TypeDef *FMPI2Cx)
1922{
1923 SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_STOP);
1924}
1925
1926/**
1927 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
1928 * @note The master sends the complete 10bit slave address read sequence :
1929 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
1930 * @rmtoll CR2 HEAD10R LL_FMPI2C_EnableAuto10BitRead
1931 * @param FMPI2Cx FMPI2C Instance.
1932 * @retval None
1933 */
1934__STATIC_INLINE void LL_FMPI2C_EnableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
1935{
1936 CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R);
1937}
1938
1939/**
1940 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
1941 * @note The master only sends the first 7 bits of 10bit address in Read direction.
1942 * @rmtoll CR2 HEAD10R LL_FMPI2C_DisableAuto10BitRead
1943 * @param FMPI2Cx FMPI2C Instance.
1944 * @retval None
1945 */
1946__STATIC_INLINE void LL_FMPI2C_DisableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
1947{
1948 SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R);
1949}
1950
1951/**
1952 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
1953 * @rmtoll CR2 HEAD10R LL_FMPI2C_IsEnabledAuto10BitRead
1954 * @param FMPI2Cx FMPI2C Instance.
1955 * @retval State of bit (1 or 0).
1956 */
1957__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
1958{
1959 return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R) != (FMPI2C_CR2_HEAD10R)) ? 1UL : 0UL);
1960}
1961
1962/**
1963 * @brief Configure the transfer direction (master mode).
1964 * @note Changing these bits when START bit is set is not allowed.
1965 * @rmtoll CR2 RD_WRN LL_FMPI2C_SetTransferRequest
1966 * @param FMPI2Cx FMPI2C Instance.
1967 * @param TransferRequest This parameter can be one of the following values:
1968 * @arg @ref LL_FMPI2C_REQUEST_WRITE
1969 * @arg @ref LL_FMPI2C_REQUEST_READ
1970 * @retval None
1971 */
1972__STATIC_INLINE void LL_FMPI2C_SetTransferRequest(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferRequest)
1973{
1974 MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN, TransferRequest);
1975}
1976
1977/**
1978 * @brief Get the transfer direction requested (master mode).
1979 * @rmtoll CR2 RD_WRN LL_FMPI2C_GetTransferRequest
1980 * @param FMPI2Cx FMPI2C Instance.
1981 * @retval Returned value can be one of the following values:
1982 * @arg @ref LL_FMPI2C_REQUEST_WRITE
1983 * @arg @ref LL_FMPI2C_REQUEST_READ
1984 */
1985__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferRequest(FMPI2C_TypeDef *FMPI2Cx)
1986{
1987 return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN));
1988}
1989
1990/**
1991 * @brief Configure the slave address for transfer (master mode).
1992 * @note Changing these bits when START bit is set is not allowed.
1993 * @rmtoll CR2 SADD LL_FMPI2C_SetSlaveAddr
1994 * @param FMPI2Cx FMPI2C Instance.
1995 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
1996 * @retval None
1997 */
1998__STATIC_INLINE void LL_FMPI2C_SetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr)
1999{
2000 MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD, SlaveAddr);
2001}
2002
2003/**
2004 * @brief Get the slave address programmed for transfer.
2005 * @rmtoll CR2 SADD LL_FMPI2C_GetSlaveAddr
2006 * @param FMPI2Cx FMPI2C Instance.
2007 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2008 */
2009__STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx)
2010{
2011 return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_SADD));
2012}
2013
2014/**
2015 * @brief Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2016 * @rmtoll CR2 SADD LL_FMPI2C_HandleTransfer\n
2017 * CR2 ADD10 LL_FMPI2C_HandleTransfer\n
2018 * CR2 RD_WRN LL_FMPI2C_HandleTransfer\n
2019 * CR2 START LL_FMPI2C_HandleTransfer\n
2020 * CR2 STOP LL_FMPI2C_HandleTransfer\n
2021 * CR2 RELOAD LL_FMPI2C_HandleTransfer\n
2022 * CR2 NBYTES LL_FMPI2C_HandleTransfer\n
2023 * CR2 AUTOEND LL_FMPI2C_HandleTransfer\n
2024 * CR2 HEAD10R LL_FMPI2C_HandleTransfer
2025 * @param FMPI2Cx FMPI2C Instance.
2026 * @param SlaveAddr Specifies the slave address to be programmed.
2027 * @param SlaveAddrSize This parameter can be one of the following values:
2028 * @arg @ref LL_FMPI2C_ADDRSLAVE_7BIT
2029 * @arg @ref LL_FMPI2C_ADDRSLAVE_10BIT
2030 * @param TransferSize Specifies the number of bytes to be programmed.
2031 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2032 * @param EndMode This parameter can be one of the following values:
2033 * @arg @ref LL_FMPI2C_MODE_RELOAD
2034 * @arg @ref LL_FMPI2C_MODE_AUTOEND
2035 * @arg @ref LL_FMPI2C_MODE_SOFTEND
2036 * @arg @ref LL_FMPI2C_MODE_SMBUS_RELOAD
2037 * @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC
2038 * @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC
2039 * @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC
2040 * @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC
2041 * @param Request This parameter can be one of the following values:
2042 * @arg @ref LL_FMPI2C_GENERATE_NOSTARTSTOP
2043 * @arg @ref LL_FMPI2C_GENERATE_STOP
2044 * @arg @ref LL_FMPI2C_GENERATE_START_READ
2045 * @arg @ref LL_FMPI2C_GENERATE_START_WRITE
2046 * @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_READ
2047 * @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE
2048 * @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_READ
2049 * @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE
2050 * @retval None
2051 */
2052__STATIC_INLINE void LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2053 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2054{
2055 MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD | FMPI2C_CR2_ADD10 |
2056 (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) |
2057 FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RELOAD |
2058 FMPI2C_CR2_NBYTES | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_HEAD10R,
2059 SlaveAddr | SlaveAddrSize | (TransferSize << FMPI2C_CR2_NBYTES_Pos) | EndMode | Request);
2060}
2061
2062/**
2063 * @brief Indicate the value of transfer direction (slave mode).
2064 * @note RESET: Write transfer, Slave enters in receiver mode.
2065 * SET: Read transfer, Slave enters in transmitter mode.
2066 * @rmtoll ISR DIR LL_FMPI2C_GetTransferDirection
2067 * @param FMPI2Cx FMPI2C Instance.
2068 * @retval Returned value can be one of the following values:
2069 * @arg @ref LL_FMPI2C_DIRECTION_WRITE
2070 * @arg @ref LL_FMPI2C_DIRECTION_READ
2071 */
2072__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(FMPI2C_TypeDef *FMPI2Cx)
2073{
2074 return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_DIR));
2075}
2076
2077/**
2078 * @brief Return the slave matched address.
2079 * @rmtoll ISR ADDCODE LL_FMPI2C_GetAddressMatchCode
2080 * @param FMPI2Cx FMPI2C Instance.
2081 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2082 */
2083__STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef *FMPI2Cx)
2084{
2085 return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDCODE) >> FMPI2C_ISR_ADDCODE_Pos << 1);
2086}
2087
2088/**
2089 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2090 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
2091 * SMBus feature is supported by the FMPI2Cx Instance.
2092 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
2093 * This bit has no effect when RELOAD bit is set.
2094 * This bit has no effect in device mode when SBC bit is not set.
2095 * @rmtoll CR2 PECBYTE LL_FMPI2C_EnableSMBusPECCompare
2096 * @param FMPI2Cx FMPI2C Instance.
2097 * @retval None
2098 */
2099__STATIC_INLINE void LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx)
2100{
2101 SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE);
2102}
2103
2104/**
2105 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2106 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
2107 * SMBus feature is supported by the FMPI2Cx Instance.
2108 * @rmtoll CR2 PECBYTE LL_FMPI2C_IsEnabledSMBusPECCompare
2109 * @param FMPI2Cx FMPI2C Instance.
2110 * @retval State of bit (1 or 0).
2111 */
2112__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx)
2113{
2114 return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE) == (FMPI2C_CR2_PECBYTE)) ? 1UL : 0UL);
2115}
2116
2117/**
2118 * @brief Get the SMBus Packet Error byte calculated.
2119 * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
2120 * SMBus feature is supported by the FMPI2Cx Instance.
2121 * @rmtoll PECR PEC LL_FMPI2C_GetSMBusPEC
2122 * @param FMPI2Cx FMPI2C Instance.
2123 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2124 */
2125__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
2126{
2127 return (uint32_t)(READ_BIT(FMPI2Cx->PECR, FMPI2C_PECR_PEC));
2128}
2129
2130/**
2131 * @brief Read Receive Data register.
2132 * @rmtoll RXDR RXDATA LL_FMPI2C_ReceiveData8
2133 * @param FMPI2Cx FMPI2C Instance.
2134 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2135 */
2136__STATIC_INLINE uint8_t LL_FMPI2C_ReceiveData8(FMPI2C_TypeDef *FMPI2Cx)
2137{
2138 return (uint8_t)(READ_BIT(FMPI2Cx->RXDR, FMPI2C_RXDR_RXDATA));
2139}
2140
2141/**
2142 * @brief Write in Transmit Data Register .
2143 * @rmtoll TXDR TXDATA LL_FMPI2C_TransmitData8
2144 * @param FMPI2Cx FMPI2C Instance.
2145 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2146 * @retval None
2147 */
2148__STATIC_INLINE void LL_FMPI2C_TransmitData8(FMPI2C_TypeDef *FMPI2Cx, uint8_t Data)
2149{
2150 WRITE_REG(FMPI2Cx->TXDR, Data);
2151}
2152
2153/**
2154 * @}
2155 */
2156
2157#if defined(USE_FULL_LL_DRIVER)
2158/** @defgroup FMPI2C_LL_EF_Init Initialization and de-initialization functions
2159 * @{
2160 */
2161
2162ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct);
2163ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx);
2164void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct);
2165
2166
2167/**
2168 * @}
2169 */
2170#endif /* USE_FULL_LL_DRIVER */
2171
2172/**
2173 * @}
2174 */
2175
2176/**
2177 * @}
2178 */
2179
2180#endif /* FMPI2C1 */
2181
2182/**
2183 * @}
2184 */
2185
2186#endif /* FMPI2C_CR1_PE */
2187#ifdef __cplusplus
2188}
2189#endif
2190
2191#endif /* STM32F4xx_LL_FMPI2C_H */
2192
2193/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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