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stm32f4xx_ll_fsmc.h

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_ll_fsmc.h
4	* @author MCD Application Team
5	* @brief Header file of FSMC HAL module.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19
20	/* Define to prevent recursive inclusion -------------------------------------*/
21	#ifndef __STM32F4xx_LL_FSMC_H
22	#define __STM32F4xx_LL_FSMC_H
23
24	#ifdef __cplusplus
25	extern "C" {
26	#endif
27
28	/* Includes ------------------------------------------------------------------*/
29	#include "stm32f4xx_hal_def.h"
30
31	/** @addtogroup STM32F4xx_HAL_Driver
32	* @{
33	*/
34
35	/** @addtogroup FSMC_LL
36	* @{
37	*/
38
39	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F412Zx) \|\|\
40	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
41	/* Private types -------------------------------------------------------------*/
42	/** @defgroup FSMC_LL_Private_Types FSMC Private Types
43	* @{
44	*/
45
46	/**
47	* @brief FSMC NORSRAM Configuration Structure definition
48	*/
49	typedef struct
50	{
51	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
52	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
53
54	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
55	multiplexed on the data bus or not.
56	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
57
58	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
59	the corresponding memory device.
60	This parameter can be a value of @ref FSMC_Memory_Type */
61
62	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
63	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
64
65	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
66	valid only with synchronous burst Flash memories.
67	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
68
69	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
70	the Flash memory in burst mode.
71	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
72
73	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
74	memory, valid only when accessing Flash memories in burst mode.
75	This parameter can be a value of @ref FSMC_Wrap_Mode
76	This mode is available only for the STM32F405/407/4015/417xx devices */
77
78	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
79	clock cycle before the wait state or during the wait state,
80	valid only when accessing memories in burst mode.
81	This parameter can be a value of @ref FSMC_Wait_Timing */
82
83	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
84	This parameter can be a value of @ref FSMC_Write_Operation */
85
86	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
87	signal, valid for Flash memory access in burst mode.
88	This parameter can be a value of @ref FSMC_Wait_Signal */
89
90	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
91	This parameter can be a value of @ref FSMC_Extended_Mode */
92
93	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
94	valid only with asynchronous Flash memories.
95	This parameter can be a value of @ref FSMC_AsynchronousWait */
96
97	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
98	This parameter can be a value of @ref FSMC_Write_Burst */
99
100	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
101	This parameter is only enabled through the FMC_BCR1 register, and don't care
102	through FMC_BCR2..4 registers.
103	This parameter can be a value of @ref FMC_Continous_Clock
104	This mode is available only for the STM32F412Vx/Zx/Rx devices */
105
106	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
107	This parameter is only enabled through the FMC_BCR1 register, and don't care
108	through FMC_BCR2..4 registers.
109	This parameter can be a value of @ref FMC_Write_FIFO
110	This mode is available only for the STM32F412Vx/Vx devices */
111
112	uint32_t PageSize; /*!< Specifies the memory page size.
113	This parameter can be a value of @ref FMC_Page_Size */
114	}FSMC_NORSRAM_InitTypeDef;
115
116	/**
117	* @brief FSMC NORSRAM Timing parameters structure definition
118	*/
119	typedef struct
120	{
121	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
122	the duration of the address setup time.
123	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
124	@note This parameter is not used with synchronous NOR Flash memories. */
125
126	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
127	the duration of the address hold time.
128	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
129	@note This parameter is not used with synchronous NOR Flash memories. */
130
131	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
132	the duration of the data setup time.
133	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
134	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
135	NOR Flash memories. */
136
137	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
138	the duration of the bus turnaround.
139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
140	@note This parameter is only used for multiplexed NOR Flash memories. */
141
142	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
143	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
144	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
145	accesses. */
146
147	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
148	to the memory before getting the first data.
149	The parameter value depends on the memory type as shown below:
150	- It must be set to 0 in case of a CRAM
151	- It is don't care in asynchronous NOR, SRAM or ROM accesses
152	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
153	with synchronous burst mode enable */
154
155	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
156	This parameter can be a value of @ref FSMC_Access_Mode */
157
158	}FSMC_NORSRAM_TimingTypeDef;
159
160	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
161	/**
162	* @brief FSMC NAND Configuration Structure definition
163	*/
164	typedef struct
165	{
166	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
167	This parameter can be a value of @ref FSMC_NAND_Bank */
168
169	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
170	This parameter can be any value of @ref FSMC_Wait_feature */
171
172	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
173	This parameter can be any value of @ref FSMC_NAND_Data_Width */
174
175	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
176	This parameter can be any value of @ref FSMC_ECC */
177
178	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
179	This parameter can be any value of @ref FSMC_ECC_Page_Size */
180
181	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
182	delay between CLE low and RE low.
183	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
184
185	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
186	delay between ALE low and RE low.
187	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
188
189	}FSMC_NAND_InitTypeDef;
190
191	/**
192	* @brief FSMC NAND/PCCARD Timing parameters structure definition
193	*/
194	typedef struct
195	{
196	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
197	the command assertion for NAND-Flash read or write access
198	to common/Attribute or I/O memory space (depending on
199	the memory space timing to be configured).
200	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
201
202	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
203	command for NAND-Flash read or write access to
204	common/Attribute or I/O memory space (depending on the
205	memory space timing to be configured).
206	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
207
208	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
209	(and data for write access) after the command de-assertion
210	for NAND-Flash read or write access to common/Attribute
211	or I/O memory space (depending on the memory space timing
212	to be configured).
213	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
214
215	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
216	data bus is kept in HiZ after the start of a NAND-Flash
217	write access to common/Attribute or I/O memory space (depending
218	on the memory space timing to be configured).
219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
220
221	}FSMC_NAND_PCC_TimingTypeDef;
222
223	/**
224	* @brief FSMC NAND Configuration Structure definition
225	*/
226	typedef struct
227	{
228	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
229	This parameter can be any value of @ref FSMC_Wait_feature */
230
231	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
232	delay between CLE low and RE low.
233	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
234
235	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
236	delay between ALE low and RE low.
237	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
238
239	}FSMC_PCCARD_InitTypeDef;
240	/**
241	* @}
242	*/
243	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
244
245	/* Private constants ---------------------------------------------------------*/
246	/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
247	* @{
248	*/
249
250	/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
251	* @{
252	*/
253	/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
254	* @{
255	*/
256	#define FSMC_NORSRAM_BANK1 0x00000000U
257	#define FSMC_NORSRAM_BANK2 0x00000002U
258	#define FSMC_NORSRAM_BANK3 0x00000004U
259	#define FSMC_NORSRAM_BANK4 0x00000006U
260	/**
261	* @}
262	*/
263
264	/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
265	* @{
266	*/
267	#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
268	#define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
269	/**
270	* @}
271	*/
272
273	/** @defgroup FSMC_Memory_Type FSMC Memory Type
274	* @{
275	*/
276	#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
277	#define FSMC_MEMORY_TYPE_PSRAM 0x00000004U
278	#define FSMC_MEMORY_TYPE_NOR 0x00000008U
279	/**
280	* @}
281	*/
282
283	/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
284	* @{
285	*/
286	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
287	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
288	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
289	/**
290	* @}
291	*/
292
293	/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
294	* @{
295	*/
296	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
297	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
298	/**
299	* @}
300	*/
301
302	/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
303	* @{
304	*/
305	#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
306	#define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
307	/**
308	* @}
309	*/
310
311	/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
312	* @{
313	*/
314	#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
315	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
316	/**
317	* @}
318	*/
319
320	/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
321	* @note These values are available only for the STM32F405/415/407/417xx devices.
322	* @{
323	*/
324	#define FSMC_WRAP_MODE_DISABLE 0x00000000U
325	#define FSMC_WRAP_MODE_ENABLE 0x00000400U
326	/**
327	* @}
328	*/
329
330	/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
331	* @{
332	*/
333	#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
334	#define FSMC_WAIT_TIMING_DURING_WS 0x00000800U
335	/**
336	* @}
337	*/
338
339	/** @defgroup FSMC_Write_Operation FSMC Write Operation
340	* @{
341	*/
342	#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
343	#define FSMC_WRITE_OPERATION_ENABLE 0x00001000U
344	/**
345	* @}
346	*/
347
348	/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
349	* @{
350	*/
351	#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
352	#define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U
353	/**
354	* @}
355	*/
356
357	/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
358	* @{
359	*/
360	#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
361	#define FSMC_EXTENDED_MODE_ENABLE 0x00004000U
362	/**
363	* @}
364	*/
365
366	/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
367	* @{
368	*/
369	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
370	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
371	/**
372	* @}
373	*/
374
375	/** @defgroup FSMC_Page_Size FSMC Page Size
376	* @{
377	*/
378	#define FSMC_PAGE_SIZE_NONE 0x00000000U
379	#define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
380	#define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
381	#define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 \| FSMC_BCR1_CPSIZE_1))
382	#define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
383	/**
384	* @}
385	*/
386
387	/** @defgroup FSMC_Write_FIFO FSMC Write FIFO
388	* @note These values are available only for the STM32F412Vx/Zx/Rx devices.
389	* @{
390	*/
391	#define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
392	#define FSMC_WRITE_FIFO_ENABLE 0x00000000U
393	/**
394	* @}
395	*/
396
397	/** @defgroup FSMC_Write_Burst FSMC Write Burst
398	* @{
399	*/
400	#define FSMC_WRITE_BURST_DISABLE 0x00000000U
401	#define FSMC_WRITE_BURST_ENABLE 0x00080000U
402	/**
403	* @}
404	*/
405
406	/** @defgroup FSMC_Continous_Clock FSMC Continous Clock
407	* @note These values are available only for the STM32F412Vx/Zx/Rx devices.
408	* @{
409	*/
410	#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
411	#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
412	/**
413	* @}
414	*/
415
416	/** @defgroup FSMC_Access_Mode FSMC Access Mode
417	* @{
418	*/
419	#define FSMC_ACCESS_MODE_A 0x00000000U
420	#define FSMC_ACCESS_MODE_B 0x10000000U
421	#define FSMC_ACCESS_MODE_C 0x20000000U
422	#define FSMC_ACCESS_MODE_D 0x30000000U
423	/**
424	* @}
425	*/
426	/**
427	* @}
428	*/
429
430	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
431	/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
432	* @{
433	*/
434	/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
435	* @{
436	*/
437	#define FSMC_NAND_BANK2 0x00000010U
438	#define FSMC_NAND_BANK3 0x00000100U
439	/**
440	* @}
441	*/
442
443	/** @defgroup FSMC_Wait_feature FSMC Wait feature
444	* @{
445	*/
446	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
447	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
448	/**
449	* @}
450	*/
451
452	/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
453	* @{
454	*/
455	#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
456	#define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U
457	/**
458	* @}
459	*/
460
461	/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
462	* @{
463	*/
464	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
465	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
466	/**
467	* @}
468	*/
469
470	/** @defgroup FSMC_ECC FSMC ECC
471	* @{
472	*/
473	#define FSMC_NAND_ECC_DISABLE 0x00000000U
474	#define FSMC_NAND_ECC_ENABLE 0x00000040U
475	/**
476	* @}
477	*/
478
479	/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
480	* @{
481	*/
482	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
483	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
484	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
485	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
486	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
487	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
488	/**
489	* @}
490	*/
491	/**
492	* @}
493	*/
494	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
495
496	/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
497	* @{
498	*/
499	#define FSMC_IT_RISING_EDGE 0x00000008U
500	#define FSMC_IT_LEVEL 0x00000010U
501	#define FSMC_IT_FALLING_EDGE 0x00000020U
502	#define FSMC_IT_REFRESH_ERROR 0x00004000U
503	/**
504	* @}
505	*/
506
507	/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
508	* @{
509	*/
510	#define FSMC_FLAG_RISING_EDGE 0x00000001U
511	#define FSMC_FLAG_LEVEL 0x00000002U
512	#define FSMC_FLAG_FALLING_EDGE 0x00000004U
513	#define FSMC_FLAG_FEMPT 0x00000040U
514	/**
515	* @}
516	*/
517
518	/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
519	* @{
520	*/
521	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
522	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
523	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
524	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
525	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
526	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
527
528	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
529	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
530	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
531	#define FSMC_NAND_DEVICE FSMC_Bank2_3
532	#define FSMC_PCCARD_DEVICE FSMC_Bank4
533	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
534
535	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
536	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
537	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
538
539	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
540	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
541	#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
542	#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
543
544	#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
545	#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
546	#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
547	#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
548	#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
549	#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
550
551	#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
552	#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
553
554	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
555	#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
556	#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
557	#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
558
559	#define FMC_NAND_Init FSMC_NAND_Init
560	#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
561	#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
562	#define FMC_NAND_DeInit FSMC_NAND_DeInit
563	#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
564	#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
565	#define FMC_NAND_GetECC FSMC_NAND_GetECC
566	#define FMC_PCCARD_Init FSMC_PCCARD_Init
567	#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
568	#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
569	#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
570	#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
571
572	#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
573	#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
574	#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
575	#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
576	#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
577	#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
578	#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
579	#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
580	#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
581	#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
582	#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
583	#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
584	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
585
586	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
587	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
588	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
589	#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
590	#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
591	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
592
593	#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
594	#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
595	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
596	#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
597	#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
598
599	#define FMC_NAND_BANK2 FSMC_NAND_BANK2
600	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
601
602	#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
603	#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
604	#define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
605
606	#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
607	#define FMC_IT_LEVEL FSMC_IT_LEVEL
608	#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
609	#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
610
611	#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
612	#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
613	#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
614	#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
615	/**
616	* @}
617	*/
618
619	/**
620	* @}
621	*/
622
623	/* Private macro -------------------------------------------------------------*/
624	/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
625	* @{
626	*/
627
628	/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
629	* @brief macros to handle NOR device enable/disable and read/write operations
630	* @{
631	*/
632	/**
633	* @brief Enable the NORSRAM device access.
634	* @param __INSTANCE__ FSMC_NORSRAM Instance
635	* @param __BANK__ FSMC_NORSRAM Bank
636	* @retval none
637	*/
638	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FSMC_BCR1_MBKEN)
639
640	/**
641	* @brief Disable the NORSRAM device access.
642	* @param __INSTANCE__ FSMC_NORSRAM Instance
643	* @param __BANK__ FSMC_NORSRAM Bank
644	* @retval none
645	*/
646	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
647	/**
648	* @}
649	*/
650
651	/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
652	* @brief macros to handle NAND device enable/disable
653	* @{
654	*/
655	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
656	/**
657	* @brief Enable the NAND device access.
658	* @param __INSTANCE__ FSMC_NAND Instance
659	* @param __BANK__ FSMC_NAND Bank
660	* @retval none
661	*/
662	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FSMC_PCR2_PBKEN): \
663	((__INSTANCE__)->PCR3 \|= FSMC_PCR3_PBKEN))
664
665	/**
666	* @brief Disable the NAND device access.
667	* @param __INSTANCE__ FSMC_NAND Instance
668	* @param __BANK__ FSMC_NAND Bank
669	* @retval none
670	*/
671	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
672	((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
673	/**
674	* @}
675	*/
676
677	/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
678	* @brief macros to handle SRAM read/write operations
679	* @{
680	*/
681	/**
682	* @brief Enable the PCCARD device access.
683	* @param __INSTANCE__ FSMC_PCCARD Instance
684	* @retval none
685	*/
686	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FSMC_PCR4_PBKEN)
687
688	/**
689	* @brief Disable the PCCARD device access.
690	* @param __INSTANCE__ FSMC_PCCARD Instance
691	* @retval none
692	*/
693	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
694	/**
695	* @}
696	*/
697
698	/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
699	* @brief macros to handle FSMC flags and interrupts
700	* @{
701	*/
702	/**
703	* @brief Enable the NAND device interrupt.
704	* @param __INSTANCE__ FSMC_NAND Instance
705	* @param __BANK__ FSMC_NAND Bank
706	* @param __INTERRUPT__ FSMC_NAND interrupt
707	* This parameter can be any combination of the following values:
708	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
709	* @arg FSMC_IT_LEVEL: Interrupt level.
710	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
711	* @retval None
712	*/
713	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
714	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
715
716	/**
717	* @brief Disable the NAND device interrupt.
718	* @param __INSTANCE__ FSMC_NAND Instance
719	* @param __BANK__ FSMC_NAND Bank
720	* @param __INTERRUPT__ FSMC_NAND interrupt
721	* This parameter can be any combination of the following values:
722	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
723	* @arg FSMC_IT_LEVEL: Interrupt level.
724	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
725	* @retval None
726	*/
727	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
728	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
729
730	/**
731	* @brief Get flag status of the NAND device.
732	* @param __INSTANCE__ FSMC_NAND Instance
733	* @param __BANK__ FSMC_NAND Bank
734	* @param __FLAG__ FSMC_NAND flag
735	* This parameter can be any combination of the following values:
736	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
737	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
738	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
739	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
740	* @retval The state of FLAG (SET or RESET).
741	*/
742	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
743	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
744
745	/**
746	* @brief Clear flag status of the NAND device.
747	* @param __INSTANCE__ FSMC_NAND Instance
748	* @param __BANK__ FSMC_NAND Bank
749	* @param __FLAG__ FSMC_NAND flag
750	* This parameter can be any combination of the following values:
751	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
752	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
753	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
754	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
755	* @retval None
756	*/
757	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
758	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
759
760	/**
761	* @brief Enable the PCCARD device interrupt.
762	* @param __INSTANCE__ FSMC_PCCARD Instance
763	* @param __INTERRUPT__ FSMC_PCCARD interrupt
764	* This parameter can be any combination of the following values:
765	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
766	* @arg FSMC_IT_LEVEL: Interrupt level.
767	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
768	* @retval None
769	*/
770	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
771
772	/**
773	* @brief Disable the PCCARD device interrupt.
774	* @param __INSTANCE__ FSMC_PCCARD Instance
775	* @param __INTERRUPT__ FSMC_PCCARD interrupt
776	* This parameter can be any combination of the following values:
777	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
778	* @arg FSMC_IT_LEVEL: Interrupt level.
779	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
780	* @retval None
781	*/
782	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
783
784	/**
785	* @brief Get flag status of the PCCARD device.
786	* @param __INSTANCE__ FSMC_PCCARD Instance
787	* @param __FLAG__ FSMC_PCCARD flag
788	* This parameter can be any combination of the following values:
789	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
790	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
791	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
792	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
793	* @retval The state of FLAG (SET or RESET).
794	*/
795	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
796
797	/**
798	* @brief Clear flag status of the PCCARD device.
799	* @param __INSTANCE__ FSMC_PCCARD Instance
800	* @param __FLAG__ FSMC_PCCARD flag
801	* This parameter can be any combination of the following values:
802	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
803	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
804	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
805	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
806	* @retval None
807	*/
808	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
809	/**
810	* @}
811	*/
812	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
813
814	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
815	* @{
816	*/
817	#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) \|\| \
818	((__BANK__) == FSMC_NORSRAM_BANK2) \|\| \
819	((__BANK__) == FSMC_NORSRAM_BANK3) \|\| \
820	((__BANK__) == FSMC_NORSRAM_BANK4))
821
822	#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
823	((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
824
825	#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) \|\| \
826	((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
827	((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
828
829	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
830	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
831	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
832
833	#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) \|\| \
834	((__MODE__) == FSMC_ACCESS_MODE_B) \|\| \
835	((__MODE__) == FSMC_ACCESS_MODE_C) \|\| \
836	((__MODE__) == FSMC_ACCESS_MODE_D))
837
838	#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) \|\| \
839	((BANK) == FSMC_NAND_BANK3))
840
841	#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
842	((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
843
844	#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
845	((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
846
847	#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) \|\| \
848	((STATE) == FSMC_NAND_ECC_ENABLE))
849
850	#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
851	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
852	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
853	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
854	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
855	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
856
857	#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
858
859	#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
860
861	#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
862
863	#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
864
865	#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
866
867	#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
868
869	#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
870
871	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
872
873	#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
874
875	#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
876
877	#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
878	((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
879
880	#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
881	((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
882
883	#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) \|\| \
884	((__MODE__) == FSMC_WRAP_MODE_ENABLE))
885
886	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
887	((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
888
889	#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
890	((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
891
892	#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
893	((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
894
895	#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
896	((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
897
898	#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
899	((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
900
901	#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
902
903	#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) \|\| \
904	((__BURST__) == FSMC_WRITE_BURST_ENABLE))
905
906	#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
907
908	#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
909
910	#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
911
912	#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
913
914	#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
915	((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
916
917	#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
918
919	#define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) \|\| \
920	((SIZE) == FSMC_PAGE_SIZE_128) \|\| \
921	((SIZE) == FSMC_PAGE_SIZE_256) \|\| \
922	((SIZE) == FSMC_PAGE_SIZE_512) \|\| \
923	((SIZE) == FSMC_PAGE_SIZE_1024))
924
925	#define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) \|\| \
926	((FIFO) == FSMC_WRITE_FIFO_ENABLE))
927
928	/**
929	* @}
930	*/
931	/**
932	* @}
933	*/
934
935	/* Private functions ---------------------------------------------------------*/
936	/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
937	* @{
938	*/
939
940	/** @defgroup FSMC_LL_NORSRAM NOR SRAM
941	* @{
942	*/
943
944	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
945	* @{
946	*/
947	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_InitTypeDef Init);
948	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
949	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
950	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
951	/**
952	* @}
953	*/
954
955	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
956	* @{
957	*/
958	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
959	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
960	/**
961	* @}
962	*/
963	/**
964	* @}
965	*/
966
967	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
968	/** @defgroup FSMC_LL_NAND NAND
969	* @{
970	*/
971	/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
972	* @{
973	*/
974	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
975	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
976	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
977	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
978	/**
979	* @}
980	*/
981
982	/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
983	* @{
984	*/
985	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
986	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
987	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
988	/**
989	* @}
990	*/
991	/**
992	* @}
993	*/
994
995	/** @defgroup FSMC_LL_PCCARD PCCARD
996	* @{
997	*/
998	/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
999	* @{
1000	*/
1001	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
1002	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
1003	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
1004	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
1005	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
1006	/**
1007	* @}
1008	*/
1009	/**
1010	* @}
1011	*/
1012	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
1013
1014	/**
1015	* @}
1016	*/
1017	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
1018
1019	/**
1020	* @}
1021	*/
1022
1023	/**
1024	* @}
1025	*/
1026
1027	#ifdef __cplusplus
1028	}
1029	#endif
1030
1031	#endif /* __STM32F4xx_LL_FSMC_H */
1032
1033	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h

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