source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h

Last change on this file was 1, checked in by AlexLir, 4 years ago
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef __STM32F4xx_LL_I2C_H
22#define __STM32F4xx_LL_I2C_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f4xx.h"
30
31/** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35#if defined (I2C1) || defined (I2C2) || defined (I2C3)
36
37/** @defgroup I2C_LL I2C
38 * @{
39 */
40
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43
44/* Private constants ---------------------------------------------------------*/
45/** @defgroup I2C_LL_Private_Constants I2C Private Constants
46 * @{
47 */
48
49/* Defines used to perform compute and check in the macros */
50#define LL_I2C_MAX_SPEED_STANDARD 100000U
51#define LL_I2C_MAX_SPEED_FAST 400000U
52/**
53 * @}
54 */
55
56/* Private macros ------------------------------------------------------------*/
57#if defined(USE_FULL_LL_DRIVER)
58/** @defgroup I2C_LL_Private_Macros I2C Private Macros
59 * @{
60 */
61/**
62 * @}
63 */
64#endif /*USE_FULL_LL_DRIVER*/
65
66/* Exported types ------------------------------------------------------------*/
67#if defined(USE_FULL_LL_DRIVER)
68/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
69 * @{
70 */
71typedef struct
72{
73 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
74 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
75
76 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
77
78 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
79 This parameter must be set to a value lower than 400kHz (in Hz)
80
81 This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
82 or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
83
84 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
85 This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
86
87 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
88
89#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
90 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
91 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
92
93 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
94
95 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
96 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
97
98 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
99
100#endif
101 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
102 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
103
104 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
105
106 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
107 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
108
109 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
110
111 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
112 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
113
114 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
115} LL_I2C_InitTypeDef;
116/**
117 * @}
118 */
119#endif /*USE_FULL_LL_DRIVER*/
120
121/* Exported constants --------------------------------------------------------*/
122/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
123 * @{
124 */
125
126/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
127 * @brief Flags defines which can be used with LL_I2C_ReadReg function
128 * @{
129 */
130#define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
131#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
132 Address matched flag (slave mode) */
133#define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
134#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
135#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
136#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
137#define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
138#define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
139#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
140#define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
141#define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
142#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
143#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
144#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
145#define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
146#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
147#define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
148#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
149#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
150#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
151#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
152/**
153 * @}
154 */
155
156/** @defgroup I2C_LL_EC_IT IT Defines
157 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
158 * @{
159 */
160#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
161#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
162#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
163/**
164 * @}
165 */
166
167#if defined(I2C_FLTR_ANOFF)
168/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
169 * @{
170 */
171#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
172#define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF /*!< Analog filter is disabled.*/
173/**
174 * @}
175 */
176
177#endif
178/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
179 * @{
180 */
181#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
182#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
183/**
184 * @}
185 */
186
187/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
188 * @{
189 */
190#define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
191#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
192/**
193 * @}
194 */
195
196/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
197 * @{
198 */
199#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
200#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
201/**
202 * @}
203 */
204
205/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
206 * @{
207 */
208#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
209#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
210#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
211#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
212/**
213 * @}
214 */
215
216/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
217 * @{
218 */
219#define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
220#define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
221/**
222 * @}
223 */
224
225/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
226 * @{
227 */
228#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
229#define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
230/**
231 * @}
232 */
233
234/**
235 * @}
236 */
237
238/* Exported macro ------------------------------------------------------------*/
239/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
240 * @{
241 */
242
243/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
244 * @{
245 */
246
247/**
248 * @brief Write a value in I2C register
249 * @param __INSTANCE__ I2C Instance
250 * @param __REG__ Register to be written
251 * @param __VALUE__ Value to be written in the register
252 * @retval None
253 */
254#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
255
256/**
257 * @brief Read a value in I2C register
258 * @param __INSTANCE__ I2C Instance
259 * @param __REG__ Register to be read
260 * @retval Register value
261 */
262#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
263/**
264 * @}
265 */
266
267/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
268 * @{
269 */
270
271/**
272 * @brief Convert Peripheral Clock Frequency in Mhz.
273 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
274 * @retval Value of peripheral clock (in Mhz)
275 */
276#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
277
278/**
279 * @brief Convert Peripheral Clock Frequency in Hz.
280 * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
281 * @retval Value of peripheral clock (in Hz)
282 */
283#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
284
285/**
286 * @brief Compute I2C Clock rising time.
287 * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
288 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
289 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
290 */
291#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
292
293/**
294 * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
295 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
296 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
297 * @param __DUTYCYCLE__ This parameter can be one of the following values:
298 * @arg @ref LL_I2C_DUTYCYCLE_2
299 * @arg @ref LL_I2C_DUTYCYCLE_16_9
300 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
301 */
302#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
303 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
304 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
305
306/**
307 * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
308 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
309 * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
310 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
311 */
312#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
313
314/**
315 * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
316 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
317 * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
318 * @param __DUTYCYCLE__ This parameter can be one of the following values:
319 * @arg @ref LL_I2C_DUTYCYCLE_2
320 * @arg @ref LL_I2C_DUTYCYCLE_16_9
321 * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
322 */
323#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
324 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
325 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
326
327/**
328 * @brief Get the Least significant bits of a 10-Bits address.
329 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
330 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
331 */
332#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
333
334/**
335 * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
336 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
337 * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
338 */
339#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
340
341/**
342 * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
343 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
344 * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
345 */
346#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
347
348/**
349 * @}
350 */
351
352/**
353 * @}
354 */
355
356/* Exported functions --------------------------------------------------------*/
357
358/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
359 * @{
360 */
361
362/** @defgroup I2C_LL_EF_Configuration Configuration
363 * @{
364 */
365
366/**
367 * @brief Enable I2C peripheral (PE = 1).
368 * @rmtoll CR1 PE LL_I2C_Enable
369 * @param I2Cx I2C Instance.
370 * @retval None
371 */
372__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
373{
374 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
375}
376
377/**
378 * @brief Disable I2C peripheral (PE = 0).
379 * @rmtoll CR1 PE LL_I2C_Disable
380 * @param I2Cx I2C Instance.
381 * @retval None
382 */
383__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
384{
385 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
386}
387
388/**
389 * @brief Check if the I2C peripheral is enabled or disabled.
390 * @rmtoll CR1 PE LL_I2C_IsEnabled
391 * @param I2Cx I2C Instance.
392 * @retval State of bit (1 or 0).
393 */
394__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
395{
396 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
397}
398
399#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
400/**
401 * @brief Configure Noise Filters (Analog and Digital).
402 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
403 * The filters can only be programmed when the I2C is disabled (PE = 0).
404 * @rmtoll FLTR ANOFF LL_I2C_ConfigFilters\n
405 * FLTR DNF LL_I2C_ConfigFilters
406 * @param I2Cx I2C Instance.
407 * @param AnalogFilter This parameter can be one of the following values:
408 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
409 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
410 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
411 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
412 * @retval None
413 */
414__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
415{
416 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter);
417}
418#endif
419#if defined(I2C_FLTR_DNF)
420
421/**
422 * @brief Configure Digital Noise Filter.
423 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
424 * This filter can only be programmed when the I2C is disabled (PE = 0).
425 * @rmtoll FLTR DNF LL_I2C_SetDigitalFilter
426 * @param I2Cx I2C Instance.
427 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
428 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
429 * @retval None
430 */
431__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
432{
433 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter);
434}
435
436/**
437 * @brief Get the current Digital Noise Filter configuration.
438 * @rmtoll FLTR DNF LL_I2C_GetDigitalFilter
439 * @param I2Cx I2C Instance.
440 * @retval Value between Min_Data=0x0 and Max_Data=0xF
441 */
442__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
443{
444 return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF));
445}
446#endif
447#if defined(I2C_FLTR_ANOFF)
448
449/**
450 * @brief Enable Analog Noise Filter.
451 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
452 * @rmtoll FLTR ANOFF LL_I2C_EnableAnalogFilter
453 * @param I2Cx I2C Instance.
454 * @retval None
455 */
456__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
457{
458 CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
459}
460
461/**
462 * @brief Disable Analog Noise Filter.
463 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
464 * @rmtoll FLTR ANOFF LL_I2C_DisableAnalogFilter
465 * @param I2Cx I2C Instance.
466 * @retval None
467 */
468__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
469{
470 SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
471}
472
473/**
474 * @brief Check if Analog Noise Filter is enabled or disabled.
475 * @rmtoll FLTR ANOFF LL_I2C_IsEnabledAnalogFilter
476 * @param I2Cx I2C Instance.
477 * @retval State of bit (1 or 0).
478 */
479__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
480{
481 return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF));
482}
483#endif
484
485/**
486 * @brief Enable DMA transmission requests.
487 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
488 * @param I2Cx I2C Instance.
489 * @retval None
490 */
491__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
492{
493 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
494}
495
496/**
497 * @brief Disable DMA transmission requests.
498 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
499 * @param I2Cx I2C Instance.
500 * @retval None
501 */
502__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
503{
504 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
505}
506
507/**
508 * @brief Check if DMA transmission requests are enabled or disabled.
509 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
510 * @param I2Cx I2C Instance.
511 * @retval State of bit (1 or 0).
512 */
513__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
514{
515 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
516}
517
518/**
519 * @brief Enable DMA reception requests.
520 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
521 * @param I2Cx I2C Instance.
522 * @retval None
523 */
524__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
525{
526 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
527}
528
529/**
530 * @brief Disable DMA reception requests.
531 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
532 * @param I2Cx I2C Instance.
533 * @retval None
534 */
535__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
536{
537 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
538}
539
540/**
541 * @brief Check if DMA reception requests are enabled or disabled.
542 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
543 * @param I2Cx I2C Instance.
544 * @retval State of bit (1 or 0).
545 */
546__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
547{
548 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
549}
550
551/**
552 * @brief Get the data register address used for DMA transfer.
553 * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
554 * @param I2Cx I2C Instance.
555 * @retval Address of data register
556 */
557__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
558{
559 return (uint32_t) & (I2Cx->DR);
560}
561
562/**
563 * @brief Enable Clock stretching.
564 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
565 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
566 * @param I2Cx I2C Instance.
567 * @retval None
568 */
569__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
570{
571 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
572}
573
574/**
575 * @brief Disable Clock stretching.
576 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
577 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
578 * @param I2Cx I2C Instance.
579 * @retval None
580 */
581__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
582{
583 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
584}
585
586/**
587 * @brief Check if Clock stretching is enabled or disabled.
588 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
589 * @param I2Cx I2C Instance.
590 * @retval State of bit (1 or 0).
591 */
592__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
593{
594 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
595}
596
597/**
598 * @brief Enable General Call.
599 * @note When enabled the Address 0x00 is ACKed.
600 * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
601 * @param I2Cx I2C Instance.
602 * @retval None
603 */
604__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
605{
606 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
607}
608
609/**
610 * @brief Disable General Call.
611 * @note When disabled the Address 0x00 is NACKed.
612 * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
613 * @param I2Cx I2C Instance.
614 * @retval None
615 */
616__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
617{
618 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
619}
620
621/**
622 * @brief Check if General Call is enabled or disabled.
623 * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
624 * @param I2Cx I2C Instance.
625 * @retval State of bit (1 or 0).
626 */
627__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
628{
629 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
630}
631
632/**
633 * @brief Set the Own Address1.
634 * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
635 * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
636 * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
637 * OAR1 ADDMODE LL_I2C_SetOwnAddress1
638 * @param I2Cx I2C Instance.
639 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
640 * @param OwnAddrSize This parameter can be one of the following values:
641 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
642 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
643 * @retval None
644 */
645__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
646{
647 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
648}
649
650/**
651 * @brief Set the 7bits Own Address2.
652 * @note This action has no effect if own address2 is enabled.
653 * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
654 * @param I2Cx I2C Instance.
655 * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
656 * @retval None
657 */
658__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
659{
660 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
661}
662
663/**
664 * @brief Enable acknowledge on Own Address2 match address.
665 * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
666 * @param I2Cx I2C Instance.
667 * @retval None
668 */
669__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
670{
671 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
672}
673
674/**
675 * @brief Disable acknowledge on Own Address2 match address.
676 * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
677 * @param I2Cx I2C Instance.
678 * @retval None
679 */
680__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
681{
682 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
683}
684
685/**
686 * @brief Check if Own Address1 acknowledge is enabled or disabled.
687 * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
688 * @param I2Cx I2C Instance.
689 * @retval State of bit (1 or 0).
690 */
691__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
692{
693 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
694}
695
696/**
697 * @brief Configure the Peripheral clock frequency.
698 * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
699 * @param I2Cx I2C Instance.
700 * @param PeriphClock Peripheral Clock (in Hz)
701 * @retval None
702 */
703__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
704{
705 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
706}
707
708/**
709 * @brief Get the Peripheral clock frequency.
710 * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
711 * @param I2Cx I2C Instance.
712 * @retval Value of Peripheral Clock (in Hz)
713 */
714__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
715{
716 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
717}
718
719/**
720 * @brief Configure the Duty cycle (Fast mode only).
721 * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
722 * @param I2Cx I2C Instance.
723 * @param DutyCycle This parameter can be one of the following values:
724 * @arg @ref LL_I2C_DUTYCYCLE_2
725 * @arg @ref LL_I2C_DUTYCYCLE_16_9
726 * @retval None
727 */
728__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
729{
730 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
731}
732
733/**
734 * @brief Get the Duty cycle (Fast mode only).
735 * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
736 * @param I2Cx I2C Instance.
737 * @retval Returned value can be one of the following values:
738 * @arg @ref LL_I2C_DUTYCYCLE_2
739 * @arg @ref LL_I2C_DUTYCYCLE_16_9
740 */
741__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
742{
743 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
744}
745
746/**
747 * @brief Configure the I2C master clock speed mode.
748 * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
749 * @param I2Cx I2C Instance.
750 * @param ClockSpeedMode This parameter can be one of the following values:
751 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
752 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
753 * @retval None
754 */
755__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
756{
757 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
758}
759
760/**
761 * @brief Get the the I2C master speed mode.
762 * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
763 * @param I2Cx I2C Instance.
764 * @retval Returned value can be one of the following values:
765 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
766 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
767 */
768__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
769{
770 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
771}
772
773/**
774 * @brief Configure the SCL, SDA rising time.
775 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
776 * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
777 * @param I2Cx I2C Instance.
778 * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
779 * @retval None
780 */
781__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
782{
783 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
784}
785
786/**
787 * @brief Get the SCL, SDA rising time.
788 * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
789 * @param I2Cx I2C Instance.
790 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
791 */
792__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
793{
794 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
795}
796
797/**
798 * @brief Configure the SCL high and low period.
799 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
800 * @rmtoll CCR CCR LL_I2C_SetClockPeriod
801 * @param I2Cx I2C Instance.
802 * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
803 * @retval None
804 */
805__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
806{
807 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
808}
809
810/**
811 * @brief Get the SCL high and low period.
812 * @rmtoll CCR CCR LL_I2C_GetClockPeriod
813 * @param I2Cx I2C Instance.
814 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
815 */
816__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
817{
818 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
819}
820
821/**
822 * @brief Configure the SCL speed.
823 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
824 * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
825 * TRISE TRISE LL_I2C_ConfigSpeed\n
826 * CCR FS LL_I2C_ConfigSpeed\n
827 * CCR DUTY LL_I2C_ConfigSpeed\n
828 * CCR CCR LL_I2C_ConfigSpeed
829 * @param I2Cx I2C Instance.
830 * @param PeriphClock Peripheral Clock (in Hz)
831 * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
832 * @param DutyCycle This parameter can be one of the following values:
833 * @arg @ref LL_I2C_DUTYCYCLE_2
834 * @arg @ref LL_I2C_DUTYCYCLE_16_9
835 * @retval None
836 */
837__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
838 uint32_t DutyCycle)
839{
840 uint32_t freqrange = 0x0U;
841 uint32_t clockconfig = 0x0U;
842
843 /* Compute frequency range */
844 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
845
846 /* Configure I2Cx: Frequency range register */
847 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
848
849 /* Configure I2Cx: Rise Time register */
850 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
851
852 /* Configure Speed mode, Duty Cycle and Clock control register value */
853 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
854 {
855 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
856 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
857 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
858 DutyCycle;
859 }
860 else
861 {
862 /* Set Speed mode at standard for Clock Speed request in standard clock range */
863 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
864 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
865 }
866
867 /* Configure I2Cx: Clock control register */
868 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
869}
870
871/**
872 * @brief Configure peripheral mode.
873 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
874 * SMBus feature is supported by the I2Cx Instance.
875 * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
876 * CR1 SMBTYPE LL_I2C_SetMode\n
877 * CR1 ENARP LL_I2C_SetMode
878 * @param I2Cx I2C Instance.
879 * @param PeripheralMode This parameter can be one of the following values:
880 * @arg @ref LL_I2C_MODE_I2C
881 * @arg @ref LL_I2C_MODE_SMBUS_HOST
882 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
883 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
884 * @retval None
885 */
886__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
887{
888 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
889}
890
891/**
892 * @brief Get peripheral mode.
893 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
894 * SMBus feature is supported by the I2Cx Instance.
895 * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
896 * CR1 SMBTYPE LL_I2C_GetMode\n
897 * CR1 ENARP LL_I2C_GetMode
898 * @param I2Cx I2C Instance.
899 * @retval Returned value can be one of the following values:
900 * @arg @ref LL_I2C_MODE_I2C
901 * @arg @ref LL_I2C_MODE_SMBUS_HOST
902 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
903 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
904 */
905__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
906{
907 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
908}
909
910/**
911 * @brief Enable SMBus alert (Host or Device mode)
912 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
913 * SMBus feature is supported by the I2Cx Instance.
914 * @note SMBus Device mode:
915 * - SMBus Alert pin is drived low and
916 * Alert Response Address Header acknowledge is enabled.
917 * SMBus Host mode:
918 * - SMBus Alert pin management is supported.
919 * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
920 * @param I2Cx I2C Instance.
921 * @retval None
922 */
923__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
924{
925 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
926}
927
928/**
929 * @brief Disable SMBus alert (Host or Device mode)
930 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
931 * SMBus feature is supported by the I2Cx Instance.
932 * @note SMBus Device mode:
933 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
934 * Alert Response Address Header acknowledge is disabled.
935 * SMBus Host mode:
936 * - SMBus Alert pin management is not supported.
937 * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
938 * @param I2Cx I2C Instance.
939 * @retval None
940 */
941__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
942{
943 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
944}
945
946/**
947 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
948 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
949 * SMBus feature is supported by the I2Cx Instance.
950 * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
951 * @param I2Cx I2C Instance.
952 * @retval State of bit (1 or 0).
953 */
954__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
955{
956 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
957}
958
959/**
960 * @brief Enable SMBus Packet Error Calculation (PEC).
961 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
962 * SMBus feature is supported by the I2Cx Instance.
963 * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
964 * @param I2Cx I2C Instance.
965 * @retval None
966 */
967__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
968{
969 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
970}
971
972/**
973 * @brief Disable SMBus Packet Error Calculation (PEC).
974 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
975 * SMBus feature is supported by the I2Cx Instance.
976 * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
977 * @param I2Cx I2C Instance.
978 * @retval None
979 */
980__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
981{
982 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
983}
984
985/**
986 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
987 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
988 * SMBus feature is supported by the I2Cx Instance.
989 * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
990 * @param I2Cx I2C Instance.
991 * @retval State of bit (1 or 0).
992 */
993__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
994{
995 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
996}
997
998/**
999 * @}
1000 */
1001
1002/** @defgroup I2C_LL_EF_IT_Management IT_Management
1003 * @{
1004 */
1005
1006/**
1007 * @brief Enable TXE interrupt.
1008 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
1009 * CR2 ITBUFEN LL_I2C_EnableIT_TX
1010 * @param I2Cx I2C Instance.
1011 * @retval None
1012 */
1013__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1014{
1015 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1016}
1017
1018/**
1019 * @brief Disable TXE interrupt.
1020 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
1021 * CR2 ITBUFEN LL_I2C_DisableIT_TX
1022 * @param I2Cx I2C Instance.
1023 * @retval None
1024 */
1025__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1026{
1027 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1028}
1029
1030/**
1031 * @brief Check if the TXE Interrupt is enabled or disabled.
1032 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
1033 * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
1034 * @param I2Cx I2C Instance.
1035 * @retval State of bit (1 or 0).
1036 */
1037__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
1038{
1039 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
1040}
1041
1042/**
1043 * @brief Enable RXNE interrupt.
1044 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
1045 * CR2 ITBUFEN LL_I2C_EnableIT_RX
1046 * @param I2Cx I2C Instance.
1047 * @retval None
1048 */
1049__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1050{
1051 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1052}
1053
1054/**
1055 * @brief Disable RXNE interrupt.
1056 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
1057 * CR2 ITBUFEN LL_I2C_DisableIT_RX
1058 * @param I2Cx I2C Instance.
1059 * @retval None
1060 */
1061__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1062{
1063 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1064}
1065
1066/**
1067 * @brief Check if the RXNE Interrupt is enabled or disabled.
1068 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
1069 * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
1070 * @param I2Cx I2C Instance.
1071 * @retval State of bit (1 or 0).
1072 */
1073__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
1074{
1075 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
1076}
1077
1078/**
1079 * @brief Enable Events interrupts.
1080 * @note Any of these events will generate interrupt :
1081 * Start Bit (SB)
1082 * Address sent, Address matched (ADDR)
1083 * 10-bit header sent (ADD10)
1084 * Stop detection (STOPF)
1085 * Byte transfer finished (BTF)
1086 *
1087 * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
1088 * Receive buffer not empty (RXNE)
1089 * Transmit buffer empty (TXE)
1090 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
1091 * @param I2Cx I2C Instance.
1092 * @retval None
1093 */
1094__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
1095{
1096 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
1097}
1098
1099/**
1100 * @brief Disable Events interrupts.
1101 * @note Any of these events will generate interrupt :
1102 * Start Bit (SB)
1103 * Address sent, Address matched (ADDR)
1104 * 10-bit header sent (ADD10)
1105 * Stop detection (STOPF)
1106 * Byte transfer finished (BTF)
1107 * Receive buffer not empty (RXNE)
1108 * Transmit buffer empty (TXE)
1109 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
1110 * @param I2Cx I2C Instance.
1111 * @retval None
1112 */
1113__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
1114{
1115 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
1116}
1117
1118/**
1119 * @brief Check if Events interrupts are enabled or disabled.
1120 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
1121 * @param I2Cx I2C Instance.
1122 * @retval State of bit (1 or 0).
1123 */
1124__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
1125{
1126 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
1127}
1128
1129/**
1130 * @brief Enable Buffer interrupts.
1131 * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
1132 * Receive buffer not empty (RXNE)
1133 * Transmit buffer empty (TXE)
1134 * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
1135 * @param I2Cx I2C Instance.
1136 * @retval None
1137 */
1138__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
1139{
1140 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
1141}
1142
1143/**
1144 * @brief Disable Buffer interrupts.
1145 * @note Any of these Buffer events will generate interrupt :
1146 * Receive buffer not empty (RXNE)
1147 * Transmit buffer empty (TXE)
1148 * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
1149 * @param I2Cx I2C Instance.
1150 * @retval None
1151 */
1152__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
1153{
1154 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
1155}
1156
1157/**
1158 * @brief Check if Buffer interrupts are enabled or disabled.
1159 * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
1160 * @param I2Cx I2C Instance.
1161 * @retval State of bit (1 or 0).
1162 */
1163__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
1164{
1165 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
1166}
1167
1168/**
1169 * @brief Enable Error interrupts.
1170 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1171 * SMBus feature is supported by the I2Cx Instance.
1172 * @note Any of these errors will generate interrupt :
1173 * Bus Error detection (BERR)
1174 * Arbitration Loss (ARLO)
1175 * Acknowledge Failure(AF)
1176 * Overrun/Underrun (OVR)
1177 * SMBus Timeout detection (TIMEOUT)
1178 * SMBus PEC error detection (PECERR)
1179 * SMBus Alert pin event detection (SMBALERT)
1180 * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
1181 * @param I2Cx I2C Instance.
1182 * @retval None
1183 */
1184__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1185{
1186 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
1187}
1188
1189/**
1190 * @brief Disable Error interrupts.
1191 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1192 * SMBus feature is supported by the I2Cx Instance.
1193 * @note Any of these errors will generate interrupt :
1194 * Bus Error detection (BERR)
1195 * Arbitration Loss (ARLO)
1196 * Acknowledge Failure(AF)
1197 * Overrun/Underrun (OVR)
1198 * SMBus Timeout detection (TIMEOUT)
1199 * SMBus PEC error detection (PECERR)
1200 * SMBus Alert pin event detection (SMBALERT)
1201 * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
1202 * @param I2Cx I2C Instance.
1203 * @retval None
1204 */
1205__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1206{
1207 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
1208}
1209
1210/**
1211 * @brief Check if Error interrupts are enabled or disabled.
1212 * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
1213 * @param I2Cx I2C Instance.
1214 * @retval State of bit (1 or 0).
1215 */
1216__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1217{
1218 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
1219}
1220
1221/**
1222 * @}
1223 */
1224
1225/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1226 * @{
1227 */
1228
1229/**
1230 * @brief Indicate the status of Transmit data register empty flag.
1231 * @note RESET: When next data is written in Transmit data register.
1232 * SET: When Transmit data register is empty.
1233 * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
1234 * @param I2Cx I2C Instance.
1235 * @retval State of bit (1 or 0).
1236 */
1237__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1238{
1239 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
1240}
1241
1242/**
1243 * @brief Indicate the status of Byte Transfer Finished flag.
1244 * RESET: When Data byte transfer not done.
1245 * SET: When Data byte transfer succeeded.
1246 * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
1247 * @param I2Cx I2C Instance.
1248 * @retval State of bit (1 or 0).
1249 */
1250__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
1251{
1252 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
1253}
1254
1255/**
1256 * @brief Indicate the status of Receive data register not empty flag.
1257 * @note RESET: When Receive data register is read.
1258 * SET: When the received data is copied in Receive data register.
1259 * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
1260 * @param I2Cx I2C Instance.
1261 * @retval State of bit (1 or 0).
1262 */
1263__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1264{
1265 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
1266}
1267
1268/**
1269 * @brief Indicate the status of Start Bit (master mode).
1270 * @note RESET: When No Start condition.
1271 * SET: When Start condition is generated.
1272 * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
1273 * @param I2Cx I2C Instance.
1274 * @retval State of bit (1 or 0).
1275 */
1276__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
1277{
1278 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
1279}
1280
1281/**
1282 * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
1283 * @note RESET: Clear default value.
1284 * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
1285 * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
1286 * @param I2Cx I2C Instance.
1287 * @retval State of bit (1 or 0).
1288 */
1289__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1290{
1291 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
1292}
1293
1294/**
1295 * @brief Indicate the status of 10-bit header sent (master mode).
1296 * @note RESET: When no ADD10 event occurred.
1297 * SET: When the master has sent the first address byte (header).
1298 * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
1299 * @param I2Cx I2C Instance.
1300 * @retval State of bit (1 or 0).
1301 */
1302__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
1303{
1304 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
1305}
1306
1307/**
1308 * @brief Indicate the status of Acknowledge failure flag.
1309 * @note RESET: No acknowledge failure.
1310 * SET: When an acknowledge failure is received after a byte transmission.
1311 * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
1312 * @param I2Cx I2C Instance.
1313 * @retval State of bit (1 or 0).
1314 */
1315__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
1316{
1317 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
1318}
1319
1320/**
1321 * @brief Indicate the status of Stop detection flag (slave mode).
1322 * @note RESET: Clear default value.
1323 * SET: When a Stop condition is detected.
1324 * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
1325 * @param I2Cx I2C Instance.
1326 * @retval State of bit (1 or 0).
1327 */
1328__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1329{
1330 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
1331}
1332
1333/**
1334 * @brief Indicate the status of Bus error flag.
1335 * @note RESET: Clear default value.
1336 * SET: When a misplaced Start or Stop condition is detected.
1337 * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
1338 * @param I2Cx I2C Instance.
1339 * @retval State of bit (1 or 0).
1340 */
1341__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1342{
1343 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
1344}
1345
1346/**
1347 * @brief Indicate the status of Arbitration lost flag.
1348 * @note RESET: Clear default value.
1349 * SET: When arbitration lost.
1350 * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
1351 * @param I2Cx I2C Instance.
1352 * @retval State of bit (1 or 0).
1353 */
1354__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1355{
1356 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
1357}
1358
1359/**
1360 * @brief Indicate the status of Overrun/Underrun flag.
1361 * @note RESET: Clear default value.
1362 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1363 * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
1364 * @param I2Cx I2C Instance.
1365 * @retval State of bit (1 or 0).
1366 */
1367__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1368{
1369 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
1370}
1371
1372/**
1373 * @brief Indicate the status of SMBus PEC error flag in reception.
1374 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1375 * SMBus feature is supported by the I2Cx Instance.
1376 * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1377 * @param I2Cx I2C Instance.
1378 * @retval State of bit (1 or 0).
1379 */
1380__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1381{
1382 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
1383}
1384
1385/**
1386 * @brief Indicate the status of SMBus Timeout detection flag.
1387 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1388 * SMBus feature is supported by the I2Cx Instance.
1389 * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1390 * @param I2Cx I2C Instance.
1391 * @retval State of bit (1 or 0).
1392 */
1393__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1394{
1395 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
1396}
1397
1398/**
1399 * @brief Indicate the status of SMBus alert flag.
1400 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1401 * SMBus feature is supported by the I2Cx Instance.
1402 * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
1403 * @param I2Cx I2C Instance.
1404 * @retval State of bit (1 or 0).
1405 */
1406__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1407{
1408 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
1409}
1410
1411/**
1412 * @brief Indicate the status of Bus Busy flag.
1413 * @note RESET: Clear default value.
1414 * SET: When a Start condition is detected.
1415 * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
1416 * @param I2Cx I2C Instance.
1417 * @retval State of bit (1 or 0).
1418 */
1419__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1420{
1421 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
1422}
1423
1424/**
1425 * @brief Indicate the status of Dual flag.
1426 * @note RESET: Received address matched with OAR1.
1427 * SET: Received address matched with OAR2.
1428 * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
1429 * @param I2Cx I2C Instance.
1430 * @retval State of bit (1 or 0).
1431 */
1432__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
1433{
1434 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
1435}
1436
1437/**
1438 * @brief Indicate the status of SMBus Host address reception (Slave mode).
1439 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1440 * SMBus feature is supported by the I2Cx Instance.
1441 * @note RESET: No SMBus Host address
1442 * SET: SMBus Host address received.
1443 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1444 * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
1445 * @param I2Cx I2C Instance.
1446 * @retval State of bit (1 or 0).
1447 */
1448__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
1449{
1450 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
1451}
1452
1453/**
1454 * @brief Indicate the status of SMBus Device default address reception (Slave mode).
1455 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1456 * SMBus feature is supported by the I2Cx Instance.
1457 * @note RESET: No SMBus Device default address
1458 * SET: SMBus Device default address received.
1459 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1460 * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
1461 * @param I2Cx I2C Instance.
1462 * @retval State of bit (1 or 0).
1463 */
1464__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
1465{
1466 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
1467}
1468
1469/**
1470 * @brief Indicate the status of General call address reception (Slave mode).
1471 * @note RESET: No General call address
1472 * SET: General call address received.
1473 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1474 * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
1475 * @param I2Cx I2C Instance.
1476 * @retval State of bit (1 or 0).
1477 */
1478__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
1479{
1480 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
1481}
1482
1483/**
1484 * @brief Indicate the status of Master/Slave flag.
1485 * @note RESET: Slave Mode.
1486 * SET: Master Mode.
1487 * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
1488 * @param I2Cx I2C Instance.
1489 * @retval State of bit (1 or 0).
1490 */
1491__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
1492{
1493 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
1494}
1495
1496/**
1497 * @brief Clear Address Matched flag.
1498 * @note Clearing this flag is done by a read access to the I2Cx_SR1
1499 * register followed by a read access to the I2Cx_SR2 register.
1500 * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
1501 * @param I2Cx I2C Instance.
1502 * @retval None
1503 */
1504__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1505{
1506 __IO uint32_t tmpreg;
1507 tmpreg = I2Cx->SR1;
1508 (void) tmpreg;
1509 tmpreg = I2Cx->SR2;
1510 (void) tmpreg;
1511}
1512
1513/**
1514 * @brief Clear Acknowledge failure flag.
1515 * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
1516 * @param I2Cx I2C Instance.
1517 * @retval None
1518 */
1519__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
1520{
1521 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
1522}
1523
1524/**
1525 * @brief Clear Stop detection flag.
1526 * @note Clearing this flag is done by a read access to the I2Cx_SR1
1527 * register followed by a write access to I2Cx_CR1 register.
1528 * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
1529 * CR1 PE LL_I2C_ClearFlag_STOP
1530 * @param I2Cx I2C Instance.
1531 * @retval None
1532 */
1533__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1534{
1535 __IO uint32_t tmpreg;
1536 tmpreg = I2Cx->SR1;
1537 (void) tmpreg;
1538 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
1539}
1540
1541/**
1542 * @brief Clear Bus error flag.
1543 * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
1544 * @param I2Cx I2C Instance.
1545 * @retval None
1546 */
1547__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1548{
1549 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
1550}
1551
1552/**
1553 * @brief Clear Arbitration lost flag.
1554 * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
1555 * @param I2Cx I2C Instance.
1556 * @retval None
1557 */
1558__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1559{
1560 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
1561}
1562
1563/**
1564 * @brief Clear Overrun/Underrun flag.
1565 * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
1566 * @param I2Cx I2C Instance.
1567 * @retval None
1568 */
1569__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1570{
1571 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
1572}
1573
1574/**
1575 * @brief Clear SMBus PEC error flag.
1576 * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
1577 * @param I2Cx I2C Instance.
1578 * @retval None
1579 */
1580__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1581{
1582 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
1583}
1584
1585/**
1586 * @brief Clear SMBus Timeout detection flag.
1587 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1588 * SMBus feature is supported by the I2Cx Instance.
1589 * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
1590 * @param I2Cx I2C Instance.
1591 * @retval None
1592 */
1593__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1594{
1595 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
1596}
1597
1598/**
1599 * @brief Clear SMBus Alert flag.
1600 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1601 * SMBus feature is supported by the I2Cx Instance.
1602 * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
1603 * @param I2Cx I2C Instance.
1604 * @retval None
1605 */
1606__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1607{
1608 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
1609}
1610
1611/**
1612 * @}
1613 */
1614
1615/** @defgroup I2C_LL_EF_Data_Management Data_Management
1616 * @{
1617 */
1618
1619/**
1620 * @brief Enable Reset of I2C peripheral.
1621 * @rmtoll CR1 SWRST LL_I2C_EnableReset
1622 * @param I2Cx I2C Instance.
1623 * @retval None
1624 */
1625__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
1626{
1627 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
1628}
1629
1630/**
1631 * @brief Disable Reset of I2C peripheral.
1632 * @rmtoll CR1 SWRST LL_I2C_DisableReset
1633 * @param I2Cx I2C Instance.
1634 * @retval None
1635 */
1636__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
1637{
1638 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
1639}
1640
1641/**
1642 * @brief Check if the I2C peripheral is under reset state or not.
1643 * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
1644 * @param I2Cx I2C Instance.
1645 * @retval State of bit (1 or 0).
1646 */
1647__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
1648{
1649 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
1650}
1651
1652/**
1653 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
1654 * @note Usage in Slave or Master mode.
1655 * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
1656 * @param I2Cx I2C Instance.
1657 * @param TypeAcknowledge This parameter can be one of the following values:
1658 * @arg @ref LL_I2C_ACK
1659 * @arg @ref LL_I2C_NACK
1660 * @retval None
1661 */
1662__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1663{
1664 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
1665}
1666
1667/**
1668 * @brief Generate a START or RESTART condition
1669 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1670 * This action has no effect when RELOAD is set.
1671 * @rmtoll CR1 START LL_I2C_GenerateStartCondition
1672 * @param I2Cx I2C Instance.
1673 * @retval None
1674 */
1675__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1676{
1677 SET_BIT(I2Cx->CR1, I2C_CR1_START);
1678}
1679
1680/**
1681 * @brief Generate a STOP condition after the current byte transfer (master mode).
1682 * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
1683 * @param I2Cx I2C Instance.
1684 * @retval None
1685 */
1686__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
1687{
1688 SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
1689}
1690
1691/**
1692 * @brief Enable bit POS (master/host mode).
1693 * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
1694 * @rmtoll CR1 POS LL_I2C_EnableBitPOS
1695 * @param I2Cx I2C Instance.
1696 * @retval None
1697 */
1698__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
1699{
1700 SET_BIT(I2Cx->CR1, I2C_CR1_POS);
1701}
1702
1703/**
1704 * @brief Disable bit POS (master/host mode).
1705 * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
1706 * @rmtoll CR1 POS LL_I2C_DisableBitPOS
1707 * @param I2Cx I2C Instance.
1708 * @retval None
1709 */
1710__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
1711{
1712 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
1713}
1714
1715/**
1716 * @brief Check if bit POS is enabled or disabled.
1717 * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
1718 * @param I2Cx I2C Instance.
1719 * @retval State of bit (1 or 0).
1720 */
1721__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
1722{
1723 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
1724}
1725
1726/**
1727 * @brief Indicate the value of transfer direction.
1728 * @note RESET: Bus is in read transfer (peripheral point of view).
1729 * SET: Bus is in write transfer (peripheral point of view).
1730 * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
1731 * @param I2Cx I2C Instance.
1732 * @retval Returned value can be one of the following values:
1733 * @arg @ref LL_I2C_DIRECTION_WRITE
1734 * @arg @ref LL_I2C_DIRECTION_READ
1735 */
1736__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
1737{
1738 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
1739}
1740
1741/**
1742 * @brief Enable DMA last transfer.
1743 * @note This action mean that next DMA EOT is the last transfer.
1744 * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
1745 * @param I2Cx I2C Instance.
1746 * @retval None
1747 */
1748__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
1749{
1750 SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
1751}
1752
1753/**
1754 * @brief Disable DMA last transfer.
1755 * @note This action mean that next DMA EOT is not the last transfer.
1756 * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
1757 * @param I2Cx I2C Instance.
1758 * @retval None
1759 */
1760__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
1761{
1762 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
1763}
1764
1765/**
1766 * @brief Check if DMA last transfer is enabled or disabled.
1767 * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
1768 * @param I2Cx I2C Instance.
1769 * @retval State of bit (1 or 0).
1770 */
1771__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
1772{
1773 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
1774}
1775
1776/**
1777 * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
1778 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1779 * SMBus feature is supported by the I2Cx Instance.
1780 * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
1781 * or by a START or STOP condition, it is also cleared by software.
1782 * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
1783 * @param I2Cx I2C Instance.
1784 * @retval None
1785 */
1786__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
1787{
1788 SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
1789}
1790
1791/**
1792 * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
1793 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1794 * SMBus feature is supported by the I2Cx Instance.
1795 * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
1796 * @param I2Cx I2C Instance.
1797 * @retval None
1798 */
1799__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
1800{
1801 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
1802}
1803
1804/**
1805 * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
1806 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1807 * SMBus feature is supported by the I2Cx Instance.
1808 * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
1809 * @param I2Cx I2C Instance.
1810 * @retval State of bit (1 or 0).
1811 */
1812__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
1813{
1814 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
1815}
1816
1817/**
1818 * @brief Get the SMBus Packet Error byte calculated.
1819 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1820 * SMBus feature is supported by the I2Cx Instance.
1821 * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
1822 * @param I2Cx I2C Instance.
1823 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1824 */
1825__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
1826{
1827 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
1828}
1829
1830/**
1831 * @brief Read Receive Data register.
1832 * @rmtoll DR DR LL_I2C_ReceiveData8
1833 * @param I2Cx I2C Instance.
1834 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1835 */
1836__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
1837{
1838 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
1839}
1840
1841/**
1842 * @brief Write in Transmit Data Register .
1843 * @rmtoll DR DR LL_I2C_TransmitData8
1844 * @param I2Cx I2C Instance.
1845 * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
1846 * @retval None
1847 */
1848__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
1849{
1850 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
1851}
1852
1853/**
1854 * @}
1855 */
1856
1857#if defined(USE_FULL_LL_DRIVER)
1858/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
1859 * @{
1860 */
1861
1862uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
1863uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
1864void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
1865
1866
1867/**
1868 * @}
1869 */
1870#endif /* USE_FULL_LL_DRIVER */
1871
1872/**
1873 * @}
1874 */
1875
1876/**
1877 * @}
1878 */
1879
1880#endif /* I2C1 || I2C2 || I2C3 */
1881
1882/**
1883 * @}
1884 */
1885
1886#ifdef __cplusplus
1887}
1888#endif
1889
1890#endif /* __STM32F4xx_LL_I2C_H */
1891
1892/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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