source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h

Last change on this file was 1, checked in by AlexLir, 4 years ago
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef __STM32F4xx_LL_PWR_H
22#define __STM32F4xx_LL_PWR_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f4xx.h"
30
31/** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35#if defined(PWR)
36
37/** @defgroup PWR_LL PWR
38 * @{
39 */
40
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43/* Private constants ---------------------------------------------------------*/
44/* Private macros ------------------------------------------------------------*/
45/* Exported types ------------------------------------------------------------*/
46/* Exported constants --------------------------------------------------------*/
47/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
48 * @{
49 */
50
51/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
52 * @brief Flags defines which can be used with LL_PWR_WriteReg function
53 * @{
54 */
55#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
56#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
57/**
58 * @}
59 */
60
61/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
62 * @brief Flags defines which can be used with LL_PWR_ReadReg function
63 * @{
64 */
65#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
66#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
67#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
68#define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */
69#if defined(PWR_CSR_EWUP)
70#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */
71#elif defined(PWR_CSR_EWUP1)
72#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
73#endif /* PWR_CSR_EWUP */
74#if defined(PWR_CSR_EWUP2)
75#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
76#endif /* PWR_CSR_EWUP2 */
77#if defined(PWR_CSR_EWUP3)
78#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
79#endif /* PWR_CSR_EWUP3 */
80/**
81 * @}
82 */
83
84/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
85 * @{
86 */
87#if defined(PWR_CR_VOS_0)
88#define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0)
89#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1)
90#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
91#else
92#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS)
93#define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U
94#endif /* PWR_CR_VOS_0 */
95/**
96 * @}
97 */
98
99/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
100 * @{
101 */
102#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
103#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
104#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
105#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
106#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
107#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
108#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
109#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
110#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
111#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
112#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
113/**
114 * @}
115 */
116
117/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
118 * @{
119 */
120#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
121#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
122/**
123 * @}
124 */
125
126/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
127 * @{
128 */
129#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
130#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
131#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
132#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
133#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
134#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
135#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
136#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
137/**
138 * @}
139 */
140/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
141 * @{
142 */
143#if defined(PWR_CSR_EWUP)
144#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */
145#endif /* PWR_CSR_EWUP */
146#if defined(PWR_CSR_EWUP1)
147#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
148#endif /* PWR_CSR_EWUP1 */
149#if defined(PWR_CSR_EWUP2)
150#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */
151#endif /* PWR_CSR_EWUP2 */
152#if defined(PWR_CSR_EWUP3)
153#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */
154#endif /* PWR_CSR_EWUP3 */
155/**
156 * @}
157 */
158
159/**
160 * @}
161 */
162
163
164/* Exported macro ------------------------------------------------------------*/
165/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
166 * @{
167 */
168
169/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
170 * @{
171 */
172
173/**
174 * @brief Write a value in PWR register
175 * @param __REG__ Register to be written
176 * @param __VALUE__ Value to be written in the register
177 * @retval None
178 */
179#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
180
181/**
182 * @brief Read a value in PWR register
183 * @param __REG__ Register to be read
184 * @retval Register value
185 */
186#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
187/**
188 * @}
189 */
190
191/**
192 * @}
193 */
194
195/* Exported functions --------------------------------------------------------*/
196/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
197 * @{
198 */
199
200/** @defgroup PWR_LL_EF_Configuration Configuration
201 * @{
202 */
203#if defined(PWR_CR_FISSR)
204/**
205 * @brief Enable FLASH interface STOP while system Run is ON
206 * @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP
207 * @note This mode is enabled only with STOP low power mode.
208 * @retval None
209 */
210__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
211{
212 SET_BIT(PWR->CR, PWR_CR_FISSR);
213}
214
215/**
216 * @brief Disable FLASH Interface STOP while system Run is ON
217 * @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP
218 * @retval None
219 */
220__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
221{
222 CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
223}
224
225/**
226 * @brief Check if FLASH Interface STOP while system Run feature is enabled
227 * @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP
228 * @retval State of bit (1 or 0).
229 */
230__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
231{
232 return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
233}
234#endif /* PWR_CR_FISSR */
235
236#if defined(PWR_CR_FMSSR)
237/**
238 * @brief Enable FLASH Memory STOP while system Run is ON
239 * @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP
240 * @note This mode is enabled only with STOP low power mode.
241 * @retval None
242 */
243__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
244{
245 SET_BIT(PWR->CR, PWR_CR_FMSSR);
246}
247
248/**
249 * @brief Disable FLASH Memory STOP while system Run is ON
250 * @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP
251 * @retval None
252 */
253__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
254{
255 CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
256}
257
258/**
259 * @brief Check if FLASH Memory STOP while system Run feature is enabled
260 * @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP
261 * @retval State of bit (1 or 0).
262 */
263__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
264{
265 return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
266}
267#endif /* PWR_CR_FMSSR */
268#if defined(PWR_CR_UDEN)
269/**
270 * @brief Enable Under Drive Mode
271 * @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode
272 * @note This mode is enabled only with STOP low power mode.
273 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
274 * mode is only available when the main Regulator or the low power Regulator
275 * is in low voltage mode.
276 * @note If the Under-drive mode was enabled, it is automatically disabled after
277 * exiting Stop mode.
278 * When the voltage Regulator operates in Under-drive mode, an additional
279 * startup delay is induced when waking up from Stop mode.
280 * @retval None
281 */
282__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
283{
284 SET_BIT(PWR->CR, PWR_CR_UDEN);
285}
286
287/**
288 * @brief Disable Under Drive Mode
289 * @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode
290 * @retval None
291 */
292__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
293{
294 CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
295}
296
297/**
298 * @brief Check if Under Drive Mode is enabled
299 * @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode
300 * @retval State of bit (1 or 0).
301 */
302__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
303{
304 return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
305}
306#endif /* PWR_CR_UDEN */
307
308#if defined(PWR_CR_ODSWEN)
309/**
310 * @brief Enable Over drive switching
311 * @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching
312 * @retval None
313 */
314__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
315{
316 SET_BIT(PWR->CR, PWR_CR_ODSWEN);
317}
318
319/**
320 * @brief Disable Over drive switching
321 * @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching
322 * @retval None
323 */
324__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
325{
326 CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
327}
328
329/**
330 * @brief Check if Over drive switching is enabled
331 * @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching
332 * @retval State of bit (1 or 0).
333 */
334__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
335{
336 return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
337}
338#endif /* PWR_CR_ODSWEN */
339#if defined(PWR_CR_ODEN)
340/**
341 * @brief Enable Over drive Mode
342 * @rmtoll CR ODEN LL_PWR_EnableOverDriveMode
343 * @retval None
344 */
345__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
346{
347 SET_BIT(PWR->CR, PWR_CR_ODEN);
348}
349
350/**
351 * @brief Disable Over drive Mode
352 * @rmtoll CR ODEN LL_PWR_DisableOverDriveMode
353 * @retval None
354 */
355__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
356{
357 CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
358}
359
360/**
361 * @brief Check if Over drive switching is enabled
362 * @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode
363 * @retval State of bit (1 or 0).
364 */
365__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
366{
367 return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
368}
369#endif /* PWR_CR_ODEN */
370#if defined(PWR_CR_MRUDS)
371/**
372 * @brief Enable Main Regulator in deepsleep under-drive Mode
373 * @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode
374 * @retval None
375 */
376__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
377{
378 SET_BIT(PWR->CR, PWR_CR_MRUDS);
379}
380
381/**
382 * @brief Disable Main Regulator in deepsleep under-drive Mode
383 * @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode
384 * @retval None
385 */
386__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
387{
388 CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
389}
390
391/**
392 * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled
393 * @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
394 * @retval State of bit (1 or 0).
395 */
396__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
397{
398 return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
399}
400#endif /* PWR_CR_MRUDS */
401
402#if defined(PWR_CR_LPUDS)
403/**
404 * @brief Enable Low Power Regulator in deepsleep under-drive Mode
405 * @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
406 * @retval None
407 */
408__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
409{
410 SET_BIT(PWR->CR, PWR_CR_LPUDS);
411}
412
413/**
414 * @brief Disable Low Power Regulator in deepsleep under-drive Mode
415 * @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
416 * @retval None
417 */
418__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
419{
420 CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
421}
422
423/**
424 * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled
425 * @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
426 * @retval State of bit (1 or 0).
427 */
428__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
429{
430 return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
431}
432#endif /* PWR_CR_LPUDS */
433
434#if defined(PWR_CR_MRLVDS)
435/**
436 * @brief Enable Main Regulator low voltage Mode
437 * @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode
438 * @retval None
439 */
440__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
441{
442 SET_BIT(PWR->CR, PWR_CR_MRLVDS);
443}
444
445/**
446 * @brief Disable Main Regulator low voltage Mode
447 * @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode
448 * @retval None
449 */
450__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
451{
452 CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
453}
454
455/**
456 * @brief Check if Main Regulator low voltage Mode is enabled
457 * @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode
458 * @retval State of bit (1 or 0).
459 */
460__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
461{
462 return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
463}
464#endif /* PWR_CR_MRLVDS */
465
466#if defined(PWR_CR_LPLVDS)
467/**
468 * @brief Enable Low Power Regulator low voltage Mode
469 * @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode
470 * @retval None
471 */
472__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
473{
474 SET_BIT(PWR->CR, PWR_CR_LPLVDS);
475}
476
477/**
478 * @brief Disable Low Power Regulator low voltage Mode
479 * @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode
480 * @retval None
481 */
482__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
483{
484 CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
485}
486
487/**
488 * @brief Check if Low Power Regulator low voltage Mode is enabled
489 * @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
490 * @retval State of bit (1 or 0).
491 */
492__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
493{
494 return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
495}
496#endif /* PWR_CR_LPLVDS */
497/**
498 * @brief Set the main internal Regulator output voltage
499 * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling
500 * @param VoltageScaling This parameter can be one of the following values:
501 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
502 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
503 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
504 * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
505 * @retval None
506 */
507__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
508{
509 MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
510}
511
512/**
513 * @brief Get the main internal Regulator output voltage
514 * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling
515 * @retval Returned value can be one of the following values:
516 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
517 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
518 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
519 * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
520 */
521__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
522{
523 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
524}
525/**
526 * @brief Enable the Flash Power Down in Stop Mode
527 * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown
528 * @retval None
529 */
530__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
531{
532 SET_BIT(PWR->CR, PWR_CR_FPDS);
533}
534
535/**
536 * @brief Disable the Flash Power Down in Stop Mode
537 * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown
538 * @retval None
539 */
540__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
541{
542 CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
543}
544
545/**
546 * @brief Check if the Flash Power Down in Stop Mode is enabled
547 * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown
548 * @retval State of bit (1 or 0).
549 */
550__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
551{
552 return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
553}
554
555/**
556 * @brief Enable access to the backup domain
557 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
558 * @retval None
559 */
560__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
561{
562 SET_BIT(PWR->CR, PWR_CR_DBP);
563}
564
565/**
566 * @brief Disable access to the backup domain
567 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
568 * @retval None
569 */
570__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
571{
572 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
573}
574
575/**
576 * @brief Check if the backup domain is enabled
577 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
578 * @retval State of bit (1 or 0).
579 */
580__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
581{
582 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
583}
584/**
585 * @brief Enable the backup Regulator
586 * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator
587 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
588 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
589 * @retval None
590 */
591__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
592{
593 SET_BIT(PWR->CSR, PWR_CSR_BRE);
594}
595
596/**
597 * @brief Disable the backup Regulator
598 * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator
599 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
600 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
601 * @retval None
602 */
603__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
604{
605 CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
606}
607
608/**
609 * @brief Check if the backup Regulator is enabled
610 * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator
611 * @retval State of bit (1 or 0).
612 */
613__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
614{
615 return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
616}
617
618/**
619 * @brief Set voltage Regulator mode during deep sleep mode
620 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
621 * @param RegulMode This parameter can be one of the following values:
622 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
623 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
624 * @retval None
625 */
626__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
627{
628 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
629}
630
631/**
632 * @brief Get voltage Regulator mode during deep sleep mode
633 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
634 * @retval Returned value can be one of the following values:
635 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
636 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
637 */
638__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
639{
640 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
641}
642
643/**
644 * @brief Set Power Down mode when CPU enters deepsleep
645 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
646 * @rmtoll CR MRUDS LL_PWR_SetPowerMode\n
647 * @rmtoll CR LPUDS LL_PWR_SetPowerMode\n
648 * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
649 * @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n
650 * @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n
651 * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
652 * @rmtoll CR LPDS LL_PWR_SetPowerMode
653 * @param PDMode This parameter can be one of the following values:
654 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
655 * @arg @ref LL_PWR_MODE_STOP_LPREGU
656 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
657 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
658 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
659 * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
660 *
661 * (*) not available on all devices
662 * @arg @ref LL_PWR_MODE_STANDBY
663 * @retval None
664 */
665__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
666{
667#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
668 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
669#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
670 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
671#else
672 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
673#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
674}
675
676/**
677 * @brief Get Power Down mode when CPU enters deepsleep
678 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
679 * @rmtoll CR MRUDS LL_PWR_GetPowerMode\n
680 * @rmtoll CR LPUDS LL_PWR_GetPowerMode\n
681 * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
682 * @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n
683 * @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n
684 * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
685 * @rmtoll CR LPDS LL_PWR_GetPowerMode
686 * @retval Returned value can be one of the following values:
687 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
688 * @arg @ref LL_PWR_MODE_STOP_LPREGU
689 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
690 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
691 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
692 * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
693 *
694 * (*) not available on all devices
695 * @arg @ref LL_PWR_MODE_STANDBY
696 */
697__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
698{
699#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
700 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
701#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
702 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
703#else
704 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
705#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
706}
707
708/**
709 * @brief Configure the voltage threshold detected by the Power Voltage Detector
710 * @rmtoll CR PLS LL_PWR_SetPVDLevel
711 * @param PVDLevel This parameter can be one of the following values:
712 * @arg @ref LL_PWR_PVDLEVEL_0
713 * @arg @ref LL_PWR_PVDLEVEL_1
714 * @arg @ref LL_PWR_PVDLEVEL_2
715 * @arg @ref LL_PWR_PVDLEVEL_3
716 * @arg @ref LL_PWR_PVDLEVEL_4
717 * @arg @ref LL_PWR_PVDLEVEL_5
718 * @arg @ref LL_PWR_PVDLEVEL_6
719 * @arg @ref LL_PWR_PVDLEVEL_7
720 * @retval None
721 */
722__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
723{
724 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
725}
726
727/**
728 * @brief Get the voltage threshold detection
729 * @rmtoll CR PLS LL_PWR_GetPVDLevel
730 * @retval Returned value can be one of the following values:
731 * @arg @ref LL_PWR_PVDLEVEL_0
732 * @arg @ref LL_PWR_PVDLEVEL_1
733 * @arg @ref LL_PWR_PVDLEVEL_2
734 * @arg @ref LL_PWR_PVDLEVEL_3
735 * @arg @ref LL_PWR_PVDLEVEL_4
736 * @arg @ref LL_PWR_PVDLEVEL_5
737 * @arg @ref LL_PWR_PVDLEVEL_6
738 * @arg @ref LL_PWR_PVDLEVEL_7
739 */
740__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
741{
742 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
743}
744
745/**
746 * @brief Enable Power Voltage Detector
747 * @rmtoll CR PVDE LL_PWR_EnablePVD
748 * @retval None
749 */
750__STATIC_INLINE void LL_PWR_EnablePVD(void)
751{
752 SET_BIT(PWR->CR, PWR_CR_PVDE);
753}
754
755/**
756 * @brief Disable Power Voltage Detector
757 * @rmtoll CR PVDE LL_PWR_DisablePVD
758 * @retval None
759 */
760__STATIC_INLINE void LL_PWR_DisablePVD(void)
761{
762 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
763}
764
765/**
766 * @brief Check if Power Voltage Detector is enabled
767 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
768 * @retval State of bit (1 or 0).
769 */
770__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
771{
772 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
773}
774
775/**
776 * @brief Enable the WakeUp PINx functionality
777 * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n
778 * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
779 * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
780 * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
781 * @param WakeUpPin This parameter can be one of the following values:
782 * @arg @ref LL_PWR_WAKEUP_PIN1
783 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
784 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
785 *
786 * (*) not available on all devices
787 * @retval None
788 */
789__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
790{
791 SET_BIT(PWR->CSR, WakeUpPin);
792}
793
794/**
795 * @brief Disable the WakeUp PINx functionality
796 * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n
797 * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
798 * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
799 * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
800 * @param WakeUpPin This parameter can be one of the following values:
801 * @arg @ref LL_PWR_WAKEUP_PIN1
802 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
803 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
804 *
805 * (*) not available on all devices
806 * @retval None
807 */
808__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
809{
810 CLEAR_BIT(PWR->CSR, WakeUpPin);
811}
812
813/**
814 * @brief Check if the WakeUp PINx functionality is enabled
815 * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n
816 * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
817 * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
818 * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
819 * @param WakeUpPin This parameter can be one of the following values:
820 * @arg @ref LL_PWR_WAKEUP_PIN1
821 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
822 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
823 *
824 * (*) not available on all devices
825 * @retval State of bit (1 or 0).
826 */
827__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
828{
829 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
830}
831
832
833/**
834 * @}
835 */
836
837/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
838 * @{
839 */
840
841/**
842 * @brief Get Wake-up Flag
843 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
844 * @retval State of bit (1 or 0).
845 */
846__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
847{
848 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
849}
850
851/**
852 * @brief Get Standby Flag
853 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
854 * @retval State of bit (1 or 0).
855 */
856__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
857{
858 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
859}
860
861/**
862 * @brief Get Backup Regulator ready Flag
863 * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR
864 * @retval State of bit (1 or 0).
865 */
866__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
867{
868 return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
869}
870/**
871 * @brief Indicate whether VDD voltage is below the selected PVD threshold
872 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
873 * @retval State of bit (1 or 0).
874 */
875__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
876{
877 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
878}
879
880/**
881 * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
882 * @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS
883 * @retval State of bit (1 or 0).
884 */
885__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
886{
887 return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
888}
889#if defined(PWR_CR_ODEN)
890/**
891 * @brief Indicate whether the Over-Drive mode is ready or not
892 * @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD
893 * @retval State of bit (1 or 0).
894 */
895__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
896{
897 return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
898}
899#endif /* PWR_CR_ODEN */
900
901#if defined(PWR_CR_ODSWEN)
902/**
903 * @brief Indicate whether the Over-Drive mode switching is ready or not
904 * @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW
905 * @retval State of bit (1 or 0).
906 */
907__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
908{
909 return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
910}
911#endif /* PWR_CR_ODSWEN */
912
913#if defined(PWR_CR_UDEN)
914/**
915 * @brief Indicate whether the Under-Drive mode is ready or not
916 * @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD
917 * @retval State of bit (1 or 0).
918 */
919__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
920{
921 return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
922}
923#endif /* PWR_CR_UDEN */
924/**
925 * @brief Clear Standby Flag
926 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
927 * @retval None
928 */
929__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
930{
931 SET_BIT(PWR->CR, PWR_CR_CSBF);
932}
933
934/**
935 * @brief Clear Wake-up Flags
936 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
937 * @retval None
938 */
939__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
940{
941 SET_BIT(PWR->CR, PWR_CR_CWUF);
942}
943#if defined(PWR_CSR_UDRDY)
944/**
945 * @brief Clear Under-Drive ready Flag
946 * @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD
947 * @retval None
948 */
949__STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
950{
951 WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
952}
953#endif /* PWR_CSR_UDRDY */
954
955/**
956 * @}
957 */
958
959#if defined(USE_FULL_LL_DRIVER)
960/** @defgroup PWR_LL_EF_Init De-initialization function
961 * @{
962 */
963ErrorStatus LL_PWR_DeInit(void);
964/**
965 * @}
966 */
967#endif /* USE_FULL_LL_DRIVER */
968
969/**
970 * @}
971 */
972
973/**
974 * @}
975 */
976
977#endif /* defined(PWR) */
978
979/**
980 * @}
981 */
982
983#ifdef __cplusplus
984}
985#endif
986
987#endif /* __STM32F4xx_LL_PWR_H */
988
989/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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