source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h

Last change on this file was 1, checked in by AlexLir, 4 years ago
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SYSCFG registers
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
22 * All rights reserved.</center></h2>
23 *
24 * This software component is licensed by ST under BSD 3-Clause license,
25 * the "License"; You may not use this file except in compliance with the
26 * License. You may obtain a copy of the License at:
27 * opensource.org/licenses/BSD-3-Clause
28 *
29 ******************************************************************************
30 */
31
32/* Define to prevent recursive inclusion -------------------------------------*/
33#ifndef __STM32F4xx_LL_SYSTEM_H
34#define __STM32F4xx_LL_SYSTEM_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40/* Includes ------------------------------------------------------------------*/
41#include "stm32f4xx.h"
42
43/** @addtogroup STM32F4xx_LL_Driver
44 * @{
45 */
46
47#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
48
49/** @defgroup SYSTEM_LL SYSTEM
50 * @{
51 */
52
53/* Private types -------------------------------------------------------------*/
54/* Private variables ---------------------------------------------------------*/
55
56/* Private constants ---------------------------------------------------------*/
57/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
58 * @{
59 */
60
61/**
62 * @}
63 */
64
65/* Private macros ------------------------------------------------------------*/
66
67/* Exported types ------------------------------------------------------------*/
68/* Exported constants --------------------------------------------------------*/
69/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
70 * @{
71 */
72
73/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
74* @{
75*/
76#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /*!< Main Flash memory mapped at 0x00000000 */
77#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
78#if defined(FSMC_Bank1)
79#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */
80#endif /* FSMC_Bank1 */
81#if defined(FMC_Bank1)
82#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */
83#define LL_SYSCFG_REMAP_SDRAM SYSCFG_MEMRMP_MEM_MODE_2 /*!< FMC/SDRAM mapped at 0x00000000 */
84#endif /* FMC_Bank1 */
85#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
86
87/**
88 * @}
89 */
90
91#if defined(SYSCFG_PMC_MII_RMII_SEL)
92 /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
93* @{
94*/
95#define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /*!< ETH Media MII interface */
96#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */
97
98/**
99 * @}
100 */
101#endif /* SYSCFG_PMC_MII_RMII_SEL */
102
103
104
105#if defined(SYSCFG_MEMRMP_UFB_MODE)
106/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
107 * @{
108 */
109#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
110 and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
111#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_UFB_MODE /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
112 and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
113/**
114 * @}
115 */
116#endif /* SYSCFG_MEMRMP_UFB_MODE */
117/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
118 * @{
119 */
120#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
121#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */
122#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/
123#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
124/**
125 * @}
126 */
127
128/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
129 * @{
130 */
131#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */
132#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */
133#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */
134#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */
135#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */
136#if defined(GPIOF)
137#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */
138#endif /* GPIOF */
139#if defined(GPIOG)
140#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */
141#endif /* GPIOG */
142#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /*!< EXTI PORT H */
143#if defined(GPIOI)
144#define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /*!< EXTI PORT I */
145#endif /* GPIOI */
146#if defined(GPIOJ)
147#define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /*!< EXTI PORT J */
148#endif /* GPIOJ */
149#if defined(GPIOK)
150#define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /*!< EXTI PORT k */
151#endif /* GPIOK */
152/**
153 * @}
154 */
155
156/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
157 * @{
158 */
159#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */
160#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */
161#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */
162#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */
163#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */
164#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */
165#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */
166#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */
167#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */
168#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */
169#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */
170#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */
171#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */
172#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */
173#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */
174#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */
175/**
176 * @}
177 */
178
179/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
180 * @{
181 */
182#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
183#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4
184 with Break Input of TIM1/8 */
185#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input
186 and also the PVDE and PLS bits of the Power Control Interface */
187#endif /* SYSCFG_CFGR2_CLL */
188/**
189 * @}
190 */
191
192#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
193/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL
194 * @{
195 */
196#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000
197#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL
198/**
199 * @}
200 */
201/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN
202 * @{
203 */
204#define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN
205#define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN
206/**
207 * @}
208 */
209/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source SYSCFG MCHDLY DFSDMD0SEL
210 * @{
211 */
212#define LL_SYSCFG_DFSDM1_DataIn0 SYSCFG_MCHDLYCR_DFSDM1D0SEL
213#define LL_SYSCFG_DFSDM2_DataIn0 SYSCFG_MCHDLYCR_DFSDM2D0SEL
214
215#define LL_SYSCFG_DFSDM1_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000)
216#define LL_SYSCFG_DFSDM1_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL)
217#define LL_SYSCFG_DFSDM2_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000)
218#define LL_SYSCFG_DFSDM2_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL)
219/**
220 * @}
221 */
222/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL
223 * @{
224 */
225#define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL
226#define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL
227
228#define LL_SYSCFG_DFSDM1_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000)
229#define LL_SYSCFG_DFSDM1_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL)
230#define LL_SYSCFG_DFSDM2_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000)
231#define LL_SYSCFG_DFSDM2_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL)
232/**
233 * @}
234 */
235/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL
236 * @{
237 */
238#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000
239#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
240/**
241 * @}
242 */
243/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL
244 * @{
245 */
246#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000
247#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
248/**
249 * @}
250 */
251/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG
252 * @{
253 */
254#define LL_SYSCFG_DFSDM1_CKIN_PAD (uint32_t)0x00000000
255#define LL_SYSCFG_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
256/**
257 * @}
258 */
259/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
260 * @{
261 */
262#define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000
263#define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
264/**
265 * @}
266 */
267
268/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
269 * @{
270 */
271#define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000
272#define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL
273/**
274 * @}
275 */
276/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
277 * @{
278 */
279#define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000
280#define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL
281/**
282 * @}
283 */
284/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL
285 * @{
286 */
287#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000
288#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
289/**
290 * @}
291 */
292/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL
293 * @{
294 */
295#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000
296#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
297/**
298 * @}
299 */
300/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL
301 * @{
302 */
303#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000
304#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
305/**
306 * @}
307 */
308/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL
309 * @{
310 */
311#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000
312#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
313/**
314 * @}
315 */
316/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
317 * @{
318 */
319#define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000
320#define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
321/**
322 * @}
323 */
324/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
325 * @{
326 */
327#define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000
328#define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
329/**
330 * @}
331 */
332#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
333
334/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
335 * @{
336 */
337#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
338#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
339#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
340#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
341#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
342/**
343 * @}
344 */
345
346/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
347 * @{
348 */
349#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
350#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
351#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
352#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
353#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
354#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
355#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
356#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
357#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
358#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
359#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
360#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
361#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
362#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
363#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
364#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
365#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
366#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
367#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
368#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
369#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
370#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
371#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
372#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
373#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
374#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
375#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP /*!< LPTIM counter stopped when core is halted */
376#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
377#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
378#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
379#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
380#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
381#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
382#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
383#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
384#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
385#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
386#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */
387#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
388#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
389#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
390#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
391#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
392#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
393#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
394#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
395#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */
396#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
397/**
398 * @}
399 */
400
401/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
402 * @{
403 */
404#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
405#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
406#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
407#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
408#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
409#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
410#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
411#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
412#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
413/**
414 * @}
415 */
416
417/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
418 * @{
419 */
420#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
421#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
422#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
423#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
424#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
425#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
426#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
427#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
428#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
429#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
430#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
431#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
432#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
433#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
434#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
435#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
436/**
437 * @}
438 */
439
440/**
441 * @}
442 */
443
444/* Exported macro ------------------------------------------------------------*/
445
446/* Exported functions --------------------------------------------------------*/
447/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
448 * @{
449 */
450
451/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
452 * @{
453 */
454/**
455 * @brief Set memory mapping at address 0x00000000
456 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
457 * @param Memory This parameter can be one of the following values:
458 * @arg @ref LL_SYSCFG_REMAP_FLASH
459 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
460 * @arg @ref LL_SYSCFG_REMAP_SRAM
461 * @arg @ref LL_SYSCFG_REMAP_FSMC (*)
462 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
463 * @retval None
464 */
465__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
466{
467 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
468}
469
470/**
471 * @brief Get memory mapping at address 0x00000000
472 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
473 * @retval Returned value can be one of the following values:
474 * @arg @ref LL_SYSCFG_REMAP_FLASH
475 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
476 * @arg @ref LL_SYSCFG_REMAP_SRAM
477 * @arg @ref LL_SYSCFG_REMAP_FSMC (*)
478 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
479 */
480__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
481{
482 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
483}
484
485#if defined(SYSCFG_MEMRMP_SWP_FMC)
486/**
487 * @brief Enables the FMC Memory Mapping Swapping
488 * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping
489 * @note SDRAM is accessible at 0x60000000 and NOR/RAM
490 * is accessible at 0xC0000000
491 * @retval None
492 */
493__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
494{
495 SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
496}
497
498/**
499 * @brief Disables the FMC Memory Mapping Swapping
500 * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping
501 * @note SDRAM is accessible at 0xC0000000 (default mapping)
502 * and NOR/RAM is accessible at 0x60000000 (default mapping)
503 * @retval None
504 */
505__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
506{
507 CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
508}
509
510#endif /* SYSCFG_MEMRMP_SWP_FMC */
511/**
512 * @brief Enables the Compensation cell Power Down
513 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
514 * @note The I/O compensation cell can be used only when the device supply
515 * voltage ranges from 2.4 to 3.6 V
516 * @retval None
517 */
518__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
519{
520 SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
521}
522
523/**
524 * @brief Disables the Compensation cell Power Down
525 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
526 * @note The I/O compensation cell can be used only when the device supply
527 * voltage ranges from 2.4 to 3.6 V
528 * @retval None
529 */
530__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
531{
532 CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
533}
534
535/**
536 * @brief Get Compensation Cell ready Flag
537 * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
538 * @retval State of bit (1 or 0).
539 */
540__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
541{
542 return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
543}
544
545#if defined(SYSCFG_PMC_MII_RMII_SEL)
546/**
547 * @brief Select Ethernet PHY interface
548 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
549 * @param Interface This parameter can be one of the following values:
550 * @arg @ref LL_SYSCFG_PMC_ETHMII
551 * @arg @ref LL_SYSCFG_PMC_ETHRMII
552 * @retval None
553 */
554__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
555{
556 MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
557}
558
559/**
560 * @brief Get Ethernet PHY interface
561 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
562 * @retval Returned value can be one of the following values:
563 * @arg @ref LL_SYSCFG_PMC_ETHMII
564 * @arg @ref LL_SYSCFG_PMC_ETHRMII
565 * @retval None
566 */
567__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
568{
569 return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
570}
571#endif /* SYSCFG_PMC_MII_RMII_SEL */
572
573
574
575#if defined(SYSCFG_MEMRMP_UFB_MODE)
576/**
577 * @brief Select Flash bank mode (Bank flashed at 0x08000000)
578 * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_SetFlashBankMode
579 * @param Bank This parameter can be one of the following values:
580 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
581 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
582 * @retval None
583 */
584__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
585{
586 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
587}
588
589/**
590 * @brief Get Flash bank mode (Bank flashed at 0x08000000)
591 * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_GetFlashBankMode
592 * @retval Returned value can be one of the following values:
593 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
594 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
595 */
596__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
597{
598 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
599}
600#endif /* SYSCFG_MEMRMP_UFB_MODE */
601
602#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
603/**
604 * @brief Enable the I2C fast mode plus driving capability.
605 * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_EnableFastModePlus\n
606 * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_EnableFastModePlus
607 * @param ConfigFastModePlus This parameter can be a combination of the following values:
608 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
609 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
610 * (*) value not defined in all devices
611 * @retval None
612 */
613__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
614{
615 SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
616}
617
618/**
619 * @brief Disable the I2C fast mode plus driving capability.
620 * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_DisableFastModePlus\n
621 * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_DisableFastModePlus\n
622 * @param ConfigFastModePlus This parameter can be a combination of the following values:
623 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
624 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
625 * (*) value not defined in all devices
626 * @retval None
627 */
628__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
629{
630 CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
631}
632#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
633
634/**
635 * @brief Configure source input for the EXTI external interrupt.
636 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
637 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
638 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
639 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
640 * @param Port This parameter can be one of the following values:
641 * @arg @ref LL_SYSCFG_EXTI_PORTA
642 * @arg @ref LL_SYSCFG_EXTI_PORTB
643 * @arg @ref LL_SYSCFG_EXTI_PORTC
644 * @arg @ref LL_SYSCFG_EXTI_PORTD
645 * @arg @ref LL_SYSCFG_EXTI_PORTE
646 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
647 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
648 * @arg @ref LL_SYSCFG_EXTI_PORTH
649 *
650 * (*) value not defined in all devices
651 * @param Line This parameter can be one of the following values:
652 * @arg @ref LL_SYSCFG_EXTI_LINE0
653 * @arg @ref LL_SYSCFG_EXTI_LINE1
654 * @arg @ref LL_SYSCFG_EXTI_LINE2
655 * @arg @ref LL_SYSCFG_EXTI_LINE3
656 * @arg @ref LL_SYSCFG_EXTI_LINE4
657 * @arg @ref LL_SYSCFG_EXTI_LINE5
658 * @arg @ref LL_SYSCFG_EXTI_LINE6
659 * @arg @ref LL_SYSCFG_EXTI_LINE7
660 * @arg @ref LL_SYSCFG_EXTI_LINE8
661 * @arg @ref LL_SYSCFG_EXTI_LINE9
662 * @arg @ref LL_SYSCFG_EXTI_LINE10
663 * @arg @ref LL_SYSCFG_EXTI_LINE11
664 * @arg @ref LL_SYSCFG_EXTI_LINE12
665 * @arg @ref LL_SYSCFG_EXTI_LINE13
666 * @arg @ref LL_SYSCFG_EXTI_LINE14
667 * @arg @ref LL_SYSCFG_EXTI_LINE15
668 * @retval None
669 */
670__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
671{
672 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
673}
674
675/**
676 * @brief Get the configured defined for specific EXTI Line
677 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
678 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
679 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
680 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
681 * @param Line This parameter can be one of the following values:
682 * @arg @ref LL_SYSCFG_EXTI_LINE0
683 * @arg @ref LL_SYSCFG_EXTI_LINE1
684 * @arg @ref LL_SYSCFG_EXTI_LINE2
685 * @arg @ref LL_SYSCFG_EXTI_LINE3
686 * @arg @ref LL_SYSCFG_EXTI_LINE4
687 * @arg @ref LL_SYSCFG_EXTI_LINE5
688 * @arg @ref LL_SYSCFG_EXTI_LINE6
689 * @arg @ref LL_SYSCFG_EXTI_LINE7
690 * @arg @ref LL_SYSCFG_EXTI_LINE8
691 * @arg @ref LL_SYSCFG_EXTI_LINE9
692 * @arg @ref LL_SYSCFG_EXTI_LINE10
693 * @arg @ref LL_SYSCFG_EXTI_LINE11
694 * @arg @ref LL_SYSCFG_EXTI_LINE12
695 * @arg @ref LL_SYSCFG_EXTI_LINE13
696 * @arg @ref LL_SYSCFG_EXTI_LINE14
697 * @arg @ref LL_SYSCFG_EXTI_LINE15
698 * @retval Returned value can be one of the following values:
699 * @arg @ref LL_SYSCFG_EXTI_PORTA
700 * @arg @ref LL_SYSCFG_EXTI_PORTB
701 * @arg @ref LL_SYSCFG_EXTI_PORTC
702 * @arg @ref LL_SYSCFG_EXTI_PORTD
703 * @arg @ref LL_SYSCFG_EXTI_PORTE
704 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
705 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
706 * @arg @ref LL_SYSCFG_EXTI_PORTH
707 * (*) value not defined in all devices
708 */
709__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
710{
711 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
712}
713
714#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
715/**
716 * @brief Set connections to TIM1/8 break inputs
717 * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
718 * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
719 * @param Break This parameter can be a combination of the following values:
720 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
721 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
722 * @retval None
723 */
724__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
725{
726 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break);
727}
728
729/**
730 * @brief Get connections to TIM1/8 Break inputs
731 * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
732 * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
733 * @retval Returned value can be can be a combination of the following values:
734 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
735 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
736 */
737__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
738{
739 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK));
740}
741#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
742#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
743/**
744 * @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
745 * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection
746 * @param ClockSource This parameter can be one of the following values:
747 * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
748 * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
749 * @retval None
750 */
751__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
752{
753 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
754}
755/**
756 * @brief Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
757 * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection
758 * @retval Returned value can be one of the following values:
759 * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
760 * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
761 * @retval None
762 */
763__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
764{
765 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
766}
767/**
768 * @brief Enables the DFSDM1 or DFSDM2 Delay clock
769 * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock
770 * @param MCHDLY This paramater can be one of the following values
771 * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
772 * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
773 * @retval None
774 */
775__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
776{
777 SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
778}
779
780/**
781 * @brief Disables the DFSDM1 or the DFSDM2 Delay clock
782 * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock
783 * @param MCHDLY This paramater can be one of the following values
784 * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
785 * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
786 * @retval None
787 */
788__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
789{
790 CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
791}
792
793/**
794 * @brief Select the source for DFSDM1 or DFSDM2 DatIn0
795 * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source
796 * @param Source This parameter can be one of the following values:
797 * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
798 * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
799 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
800 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
801 * @retval None
802 */
803__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
804{
805 MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
806}
807/**
808 * @brief Get the source for DFSDM1 or DFSDM2 DatIn0.
809 * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_GetDataIn0Source
810 * @param Source This parameter can be one of the following values:
811 * @arg @ref LL_SYSCFG_DFSDM1_DataIn0
812 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0
813 * @retval Returned value can be one of the following values:
814 * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
815 * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
816 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
817 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
818 * @retval None
819 */
820__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
821{
822 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
823}
824/**
825 * @brief Select the source for DFSDM1 or DFSDM2 DatIn2
826 * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source
827 * @param Source This parameter can be one of the following values:
828 * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
829 * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
830 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
831 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
832 * @retval None
833 */
834__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
835{
836 MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
837}
838/**
839 * @brief Get the source for DFSDM1 or DFSDM2 DatIn2.
840 * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_GetDataIn2Source
841 * @param Source This parameter can be one of the following values:
842 * @arg @ref LL_SYSCFG_DFSDM1_DataIn2
843 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2
844 * @retval Returned value can be one of the following values:
845 * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
846 * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
847 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
848 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
849 * @retval None
850 */
851__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
852{
853 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
854}
855
856/**
857 * @brief Select the distribution of the bitsream lock gated by TIM4 OC2
858 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
859 * @param Source This parameter can be one of the following values:
860 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
861 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
862 * @retval None
863 */
864__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
865{
866 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
867}
868/**
869 * @brief Get the distribution of the bitsream lock gated by TIM4 OC2
870 * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
871 * @retval Returned value can be one of the following values:
872 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
873 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
874 * @retval None
875 */
876__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
877{
878 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
879}
880
881/**
882 * @brief Select the distribution of the bitsream lock gated by TIM4 OC1
883 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
884 * @param Source This parameter can be one of the following values:
885 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
886 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
887 * @retval None
888 */
889__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
890{
891 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
892}
893/**
894 * @brief Get the distribution of the bitsream lock gated by TIM4 OC1
895 * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
896 * @retval Returned value can be one of the following values:
897 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
898 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
899 * @retval None
900 */
901__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
902{
903 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
904}
905
906/**
907 * @brief Select the DFSDM1 Clock In
908 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection
909 * @param ClockSource This parameter can be one of the following values:
910 * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
911 * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
912 * @retval None
913 */
914__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
915{
916 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
917}
918/**
919 * @brief GET the DFSDM1 Clock In
920 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_GetClockInSourceSelection
921 * @retval Returned value can be one of the following values:
922 * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
923 * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
924 * @retval None
925 */
926__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
927{
928 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
929}
930
931/**
932 * @brief Select the DFSDM1 Clock Out
933 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
934 * @param ClockSource This parameter can be one of the following values:
935 * @arg @ref LL_SYSCFG_DFSDM1_CKOUT
936 * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
937 * @retval None
938 */
939__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
940{
941 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
942}
943/**
944 * @brief GET the DFSDM1 Clock Out
945 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_GetClockOutSourceSelection
946 * @retval Returned value can be one of the following values:
947 * @arg @ref LL_SYSCFG_DFSDM1_CKOUT
948 * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
949 * @retval None
950 */
951__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
952{
953 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
954}
955
956/**
957 * @brief Enables the DFSDM2 Delay clock
958 * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_EnableDelayClock
959 * @retval None
960 */
961__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
962{
963 SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
964}
965
966/**
967 * @brief Disables the DFSDM2 Delay clock
968 * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_DisableDelayClock
969 * @retval None
970 */
971__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
972{
973 CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
974}
975/**
976 * @brief Select the source for DFSDM2 DatIn0
977 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source
978 * @param Source This parameter can be one of the following values:
979 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
980 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
981 * @retval None
982 */
983__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
984{
985 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
986}
987/**
988 * @brief Get the source for DFSDM2 DatIn0.
989 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_GetDataIn0Source
990 * @retval Returned value can be one of the following values:
991 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
992 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
993 * @retval None
994 */
995__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
996{
997 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
998}
999
1000/**
1001 * @brief Select the source for DFSDM2 DatIn2
1002 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source
1003 * @param Source This parameter can be one of the following values:
1004 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
1005 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
1006 * @retval None
1007 */
1008__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
1009{
1010 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
1011}
1012/**
1013 * @brief Get the source for DFSDM2 DatIn2.
1014 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_GetDataIn2Source
1015 * @retval Returned value can be one of the following values:
1016 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
1017 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
1018 * @retval None
1019 */
1020__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
1021{
1022 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
1023}
1024
1025/**
1026 * @brief Select the source for DFSDM2 DatIn4
1027 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source
1028 * @param Source This parameter can be one of the following values:
1029 * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
1030 * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
1031 * @retval None
1032 */
1033__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
1034{
1035 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
1036}
1037/**
1038 * @brief Get the source for DFSDM2 DatIn4.
1039 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_GetDataIn4Source
1040 * @retval Returned value can be one of the following values:
1041 * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
1042 * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
1043 * @retval None
1044 */
1045__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
1046{
1047 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
1048}
1049
1050/**
1051 * @brief Select the source for DFSDM2 DatIn6
1052 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source
1053 * @param Source This parameter can be one of the following values:
1054 * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
1055 * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
1056 * @retval None
1057 */
1058__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
1059{
1060 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
1061}
1062/**
1063 * @brief Get the source for DFSDM2 DatIn6.
1064 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_GetDataIn6Source
1065 * @retval Returned value can be one of the following values:
1066 * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
1067 * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
1068 * @retval None
1069 */
1070__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
1071{
1072 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
1073}
1074
1075/**
1076 * @brief Select the distribution of the bitsream lock gated by TIM3 OC4
1077 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
1078 * @param Source This parameter can be one of the following values:
1079 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
1080 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
1081 * @retval None
1082 */
1083__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
1084{
1085 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
1086}
1087/**
1088 * @brief Get the distribution of the bitsream lock gated by TIM3 OC4
1089 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
1090 * @retval Returned value can be one of the following values:
1091 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
1092 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
1093 * @retval None
1094 */
1095__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
1096{
1097 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
1098}
1099
1100/**
1101 * @brief Select the distribution of the bitsream lock gated by TIM3 OC3
1102 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
1103 * @param Source This parameter can be one of the following values:
1104 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
1105 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
1106 * @retval None
1107 */
1108__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
1109{
1110 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
1111}
1112/**
1113 * @brief Get the distribution of the bitsream lock gated by TIM3 OC4
1114 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
1115 * @retval Returned value can be one of the following values:
1116 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
1117 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
1118 * @retval None
1119 */
1120__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
1121{
1122 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
1123}
1124
1125/**
1126 * @brief Select the distribution of the bitsream lock gated by TIM3 OC2
1127 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
1128 * @param Source This parameter can be one of the following values:
1129 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
1130 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
1131 * @retval None
1132 */
1133__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
1134{
1135 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
1136}
1137/**
1138 * @brief Get the distribution of the bitsream lock gated by TIM3 OC2
1139 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
1140 * @retval Returned value can be one of the following values:
1141 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
1142 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
1143 * @retval None
1144 */
1145__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
1146{
1147 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
1148}
1149
1150/**
1151 * @brief Select the distribution of the bitsream lock gated by TIM3 OC1
1152 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
1153 * @param Source This parameter can be one of the following values:
1154 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
1155 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
1156 * @retval None
1157 */
1158__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
1159{
1160 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
1161}
1162/**
1163 * @brief Get the distribution of the bitsream lock gated by TIM3 OC1
1164 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
1165 * @retval Returned value can be one of the following values:
1166 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
1167 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
1168 * @retval None
1169 */
1170__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
1171{
1172 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
1173}
1174
1175/**
1176 * @brief Select the DFSDM2 Clock In
1177 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection
1178 * @param ClockSource This parameter can be one of the following values:
1179 * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
1180 * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
1181 * @retval None
1182 */
1183__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
1184{
1185 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
1186}
1187/**
1188 * @brief GET the DFSDM2 Clock In
1189 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_GetClockInSourceSelection
1190 * @retval Returned value can be one of the following values:
1191 * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
1192 * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
1193 * @retval None
1194 */
1195__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
1196{
1197 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
1198}
1199
1200/**
1201 * @brief Select the DFSDM2 Clock Out
1202 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
1203 * @param ClockSource This parameter can be one of the following values:
1204 * @arg @ref LL_SYSCFG_DFSDM2_CKOUT
1205 * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
1206 * @retval None
1207 */
1208__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
1209{
1210 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
1211}
1212/**
1213 * @brief GET the DFSDM2 Clock Out
1214 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_GetClockOutSourceSelection
1215 * @retval Returned value can be one of the following values:
1216 * @arg @ref LL_SYSCFG_DFSDM2_CKOUT
1217 * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
1218 * @retval None
1219 */
1220__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
1221{
1222 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
1223}
1224
1225#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
1226/**
1227 * @}
1228 */
1229
1230
1231/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1232 * @{
1233 */
1234
1235/**
1236 * @brief Return the device identifier
1237 * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413
1238 * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419
1239 * @note For STM32F401xx devices, the device ID is 0x423
1240 * @note For STM32F401xx devices, the device ID is 0x433
1241 * @note For STM32F411xx devices, the device ID is 0x431
1242 * @note For STM32F410xx devices, the device ID is 0x458
1243 * @note For STM32F412xx devices, the device ID is 0x441
1244 * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463
1245 * @note For STM32F446xx devices, the device ID is 0x421
1246 * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434
1247 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1248 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1249 */
1250__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1251{
1252 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1253}
1254
1255/**
1256 * @brief Return the device revision identifier
1257 * @note This field indicates the revision of the device.
1258 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices
1259 For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices
1260 For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices
1261 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices
1262 For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices
1263 For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices
1264 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1265 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1266 */
1267__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1268{
1269 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1270}
1271
1272/**
1273 * @brief Enable the Debug Module during SLEEP mode
1274 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
1275 * @retval None
1276 */
1277__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1278{
1279 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1280}
1281
1282/**
1283 * @brief Disable the Debug Module during SLEEP mode
1284 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
1285 * @retval None
1286 */
1287__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1288{
1289 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1290}
1291
1292/**
1293 * @brief Enable the Debug Module during STOP mode
1294 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1295 * @retval None
1296 */
1297__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1298{
1299 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1300}
1301
1302/**
1303 * @brief Disable the Debug Module during STOP mode
1304 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1305 * @retval None
1306 */
1307__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1308{
1309 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1310}
1311
1312/**
1313 * @brief Enable the Debug Module during STANDBY mode
1314 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1315 * @retval None
1316 */
1317__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1318{
1319 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1320}
1321
1322/**
1323 * @brief Disable the Debug Module during STANDBY mode
1324 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1325 * @retval None
1326 */
1327__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1328{
1329 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1330}
1331
1332/**
1333 * @brief Set Trace pin assignment control
1334 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1335 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1336 * @param PinAssignment This parameter can be one of the following values:
1337 * @arg @ref LL_DBGMCU_TRACE_NONE
1338 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1339 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1340 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1341 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1342 * @retval None
1343 */
1344__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1345{
1346 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1347}
1348
1349/**
1350 * @brief Get Trace pin assignment control
1351 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1352 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1353 * @retval Returned value can be one of the following values:
1354 * @arg @ref LL_DBGMCU_TRACE_NONE
1355 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1356 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1357 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1358 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1359 */
1360__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1361{
1362 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1363}
1364
1365/**
1366 * @brief Freeze APB1 peripherals (group1 peripherals)
1367 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1368 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1369 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1370 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1371 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1372 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1373 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1374 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1375 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1376 * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1377 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1378 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1379 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1380 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1381 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1382 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1383 * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1384 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1385 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1386 * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1387 * @param Periphs This parameter can be a combination of the following values:
1388 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1389 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1390 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1391 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1392 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
1393 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1394 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1395 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1396 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1397 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
1398 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1399 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1400 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1401 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1402 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1403 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1404 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
1405 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
1406 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1407 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
1408 *
1409 * (*) value not defined in all devices.
1410 * @retval None
1411 */
1412__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1413{
1414 SET_BIT(DBGMCU->APB1FZ, Periphs);
1415}
1416
1417/**
1418 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1419 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1420 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1421 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1422 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1423 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1424 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1425 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1426 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1427 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1428 * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1429 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1430 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1431 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1432 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1433 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1434 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1435 * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1436 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1437 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1438 * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1439 * @param Periphs This parameter can be a combination of the following values:
1440 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1441 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1442 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1443 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1444 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
1445 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1446 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1447 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1448 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1449 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
1450 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1451 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1452 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1453 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1454 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1455 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1456 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
1457 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
1458 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1459 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
1460 *
1461 * (*) value not defined in all devices.
1462 * @retval None
1463 */
1464__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1465{
1466 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
1467}
1468
1469/**
1470 * @brief Freeze APB2 peripherals
1471 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1472 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1473 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1474 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1475 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1476 * @param Periphs This parameter can be a combination of the following values:
1477 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1478 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1479 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
1480 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
1481 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
1482 *
1483 * (*) value not defined in all devices.
1484 * @retval None
1485 */
1486__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1487{
1488 SET_BIT(DBGMCU->APB2FZ, Periphs);
1489}
1490
1491/**
1492 * @brief Unfreeze APB2 peripherals
1493 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1494 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1495 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1496 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1497 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1498 * @param Periphs This parameter can be a combination of the following values:
1499 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1500 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1501 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
1502 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
1503 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
1504 *
1505 * (*) value not defined in all devices.
1506 * @retval None
1507 */
1508__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1509{
1510 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1511}
1512/**
1513 * @}
1514 */
1515
1516/** @defgroup SYSTEM_LL_EF_FLASH FLASH
1517 * @{
1518 */
1519
1520/**
1521 * @brief Set FLASH Latency
1522 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1523 * @param Latency This parameter can be one of the following values:
1524 * @arg @ref LL_FLASH_LATENCY_0
1525 * @arg @ref LL_FLASH_LATENCY_1
1526 * @arg @ref LL_FLASH_LATENCY_2
1527 * @arg @ref LL_FLASH_LATENCY_3
1528 * @arg @ref LL_FLASH_LATENCY_4
1529 * @arg @ref LL_FLASH_LATENCY_5
1530 * @arg @ref LL_FLASH_LATENCY_6
1531 * @arg @ref LL_FLASH_LATENCY_7
1532 * @arg @ref LL_FLASH_LATENCY_8
1533 * @arg @ref LL_FLASH_LATENCY_9
1534 * @arg @ref LL_FLASH_LATENCY_10
1535 * @arg @ref LL_FLASH_LATENCY_11
1536 * @arg @ref LL_FLASH_LATENCY_12
1537 * @arg @ref LL_FLASH_LATENCY_13
1538 * @arg @ref LL_FLASH_LATENCY_14
1539 * @arg @ref LL_FLASH_LATENCY_15
1540 * @retval None
1541 */
1542__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1543{
1544 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1545}
1546
1547/**
1548 * @brief Get FLASH Latency
1549 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1550 * @retval Returned value can be one of the following values:
1551 * @arg @ref LL_FLASH_LATENCY_0
1552 * @arg @ref LL_FLASH_LATENCY_1
1553 * @arg @ref LL_FLASH_LATENCY_2
1554 * @arg @ref LL_FLASH_LATENCY_3
1555 * @arg @ref LL_FLASH_LATENCY_4
1556 * @arg @ref LL_FLASH_LATENCY_5
1557 * @arg @ref LL_FLASH_LATENCY_6
1558 * @arg @ref LL_FLASH_LATENCY_7
1559 * @arg @ref LL_FLASH_LATENCY_8
1560 * @arg @ref LL_FLASH_LATENCY_9
1561 * @arg @ref LL_FLASH_LATENCY_10
1562 * @arg @ref LL_FLASH_LATENCY_11
1563 * @arg @ref LL_FLASH_LATENCY_12
1564 * @arg @ref LL_FLASH_LATENCY_13
1565 * @arg @ref LL_FLASH_LATENCY_14
1566 * @arg @ref LL_FLASH_LATENCY_15
1567 */
1568__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1569{
1570 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1571}
1572
1573/**
1574 * @brief Enable Prefetch
1575 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
1576 * @retval None
1577 */
1578__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1579{
1580 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1581}
1582
1583/**
1584 * @brief Disable Prefetch
1585 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
1586 * @retval None
1587 */
1588__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1589{
1590 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1591}
1592
1593/**
1594 * @brief Check if Prefetch buffer is enabled
1595 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
1596 * @retval State of bit (1 or 0).
1597 */
1598__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1599{
1600 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
1601}
1602
1603/**
1604 * @brief Enable Instruction cache
1605 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
1606 * @retval None
1607 */
1608__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1609{
1610 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1611}
1612
1613/**
1614 * @brief Disable Instruction cache
1615 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
1616 * @retval None
1617 */
1618__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1619{
1620 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1621}
1622
1623/**
1624 * @brief Enable Data cache
1625 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
1626 * @retval None
1627 */
1628__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
1629{
1630 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1631}
1632
1633/**
1634 * @brief Disable Data cache
1635 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
1636 * @retval None
1637 */
1638__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
1639{
1640 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1641}
1642
1643/**
1644 * @brief Enable Instruction cache reset
1645 * @note bit can be written only when the instruction cache is disabled
1646 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
1647 * @retval None
1648 */
1649__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1650{
1651 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1652}
1653
1654/**
1655 * @brief Disable Instruction cache reset
1656 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
1657 * @retval None
1658 */
1659__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1660{
1661 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1662}
1663
1664/**
1665 * @brief Enable Data cache reset
1666 * @note bit can be written only when the data cache is disabled
1667 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
1668 * @retval None
1669 */
1670__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
1671{
1672 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1673}
1674
1675/**
1676 * @brief Disable Data cache reset
1677 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
1678 * @retval None
1679 */
1680__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
1681{
1682 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1683}
1684
1685
1686/**
1687 * @}
1688 */
1689
1690/**
1691 * @}
1692 */
1693
1694/**
1695 * @}
1696 */
1697
1698#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1699
1700/**
1701 * @}
1702 */
1703
1704#ifdef __cplusplus
1705}
1706#endif
1707
1708#endif /* __STM32F4xx_LL_SYSTEM_H */
1709
1710/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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