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stm32f4xx_ll_tim.h

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_ll_tim.h
4	* @author MCD Application Team
5	* @brief Header file of TIM LL module.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19
20	/* Define to prevent recursive inclusion -------------------------------------*/
21	#ifndef __STM32F4xx_LL_TIM_H
22	#define __STM32F4xx_LL_TIM_H
23
24	#ifdef __cplusplus
25	extern "C" {
26	#endif
27
28	/* Includes ------------------------------------------------------------------*/
29	#include "stm32f4xx.h"
30
31	/** @addtogroup STM32F4xx_LL_Driver
32	* @{
33	*/
34
35	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14)
36
37	/** @defgroup TIM_LL TIM
38	* @{
39	*/
40
41	/* Private types -------------------------------------------------------------*/
42	/* Private variables ---------------------------------------------------------*/
43	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
44	* @{
45	*/
46	static const uint8_t OFFSET_TAB_CCMRx[] =
47	{
48	0x00U, /* 0: TIMx_CH1 */
49	0x00U, /* 1: TIMx_CH1N */
50	0x00U, /* 2: TIMx_CH2 */
51	0x00U, /* 3: TIMx_CH2N */
52	0x04U, /* 4: TIMx_CH3 */
53	0x04U, /* 5: TIMx_CH3N */
54	0x04U /* 6: TIMx_CH4 */
55	};
56
57	static const uint8_t SHIFT_TAB_OCxx[] =
58	{
59	0U, /* 0: OC1M, OC1FE, OC1PE */
60	0U, /* 1: - NA */
61	8U, /* 2: OC2M, OC2FE, OC2PE */
62	0U, /* 3: - NA */
63	0U, /* 4: OC3M, OC3FE, OC3PE */
64	0U, /* 5: - NA */
65	8U /* 6: OC4M, OC4FE, OC4PE */
66	};
67
68	static const uint8_t SHIFT_TAB_ICxx[] =
69	{
70	0U, /* 0: CC1S, IC1PSC, IC1F */
71	0U, /* 1: - NA */
72	8U, /* 2: CC2S, IC2PSC, IC2F */
73	0U, /* 3: - NA */
74	0U, /* 4: CC3S, IC3PSC, IC3F */
75	0U, /* 5: - NA */
76	8U /* 6: CC4S, IC4PSC, IC4F */
77	};
78
79	static const uint8_t SHIFT_TAB_CCxP[] =
80	{
81	0U, /* 0: CC1P */
82	2U, /* 1: CC1NP */
83	4U, /* 2: CC2P */
84	6U, /* 3: CC2NP */
85	8U, /* 4: CC3P */
86	10U, /* 5: CC3NP */
87	12U /* 6: CC4P */
88	};
89
90	static const uint8_t SHIFT_TAB_OISx[] =
91	{
92	0U, /* 0: OIS1 */
93	1U, /* 1: OIS1N */
94	2U, /* 2: OIS2 */
95	3U, /* 3: OIS2N */
96	4U, /* 4: OIS3 */
97	5U, /* 5: OIS3N */
98	6U /* 6: OIS4 */
99	};
100	/**
101	* @}
102	*/
103
104	/* Private constants ---------------------------------------------------------*/
105	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
106	* @{
107	*/
108
109
110	/* Remap mask definitions */
111	#define TIMx_OR_RMP_SHIFT 16U
112	#define TIMx_OR_RMP_MASK 0x0000FFFFU
113	#define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
114	#define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
115	#define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
116
117	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
118	#define DT_DELAY_1 ((uint8_t)0x7F)
119	#define DT_DELAY_2 ((uint8_t)0x3F)
120	#define DT_DELAY_3 ((uint8_t)0x1F)
121	#define DT_DELAY_4 ((uint8_t)0x1F)
122
123	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
124	#define DT_RANGE_1 ((uint8_t)0x00)
125	#define DT_RANGE_2 ((uint8_t)0x80)
126	#define DT_RANGE_3 ((uint8_t)0xC0)
127	#define DT_RANGE_4 ((uint8_t)0xE0)
128
129
130	/**
131	* @}
132	*/
133
134	/* Private macros ------------------------------------------------------------*/
135	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
136	* @{
137	*/
138	/** @brief Convert channel id into channel index.
139	* @param __CHANNEL__ This parameter can be one of the following values:
140	* @arg @ref LL_TIM_CHANNEL_CH1
141	* @arg @ref LL_TIM_CHANNEL_CH1N
142	* @arg @ref LL_TIM_CHANNEL_CH2
143	* @arg @ref LL_TIM_CHANNEL_CH2N
144	* @arg @ref LL_TIM_CHANNEL_CH3
145	* @arg @ref LL_TIM_CHANNEL_CH3N
146	* @arg @ref LL_TIM_CHANNEL_CH4
147	* @retval none
148	*/
149	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
150	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
151	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
152	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
153	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
154	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
155	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
156
157	/** @brief Calculate the deadtime sampling period(in ps).
158	* @param __TIMCLK__ timer input clock frequency (in Hz).
159	* @param __CKD__ This parameter can be one of the following values:
160	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
161	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
162	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
163	* @retval none
164	*/
165	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
166	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
167	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
168	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
169	/**
170	* @}
171	*/
172
173
174	/* Exported types ------------------------------------------------------------*/
175	#if defined(USE_FULL_LL_DRIVER)
176	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
177	* @{
178	*/
179
180	/**
181	* @brief TIM Time Base configuration structure definition.
182	*/
183	typedef struct
184	{
185	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
186	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
187
188	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
189
190	uint32_t CounterMode; /*!< Specifies the counter mode.
191	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
192
193	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
194
195	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
196	Auto-Reload Register at the next update event.
197	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
198	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
199
200	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
201
202	uint32_t ClockDivision; /*!< Specifies the clock division.
203	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
204
205	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
206
207	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
208	reaches zero, an update event is generated and counting restarts
209	from the RCR value (N).
210	This means in PWM mode that (N+1) corresponds to:
211	- the number of PWM periods in edge-aligned mode
212	- the number of half PWM period in center-aligned mode
213	GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
214	Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
215
216	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
217	} LL_TIM_InitTypeDef;
218
219	/**
220	* @brief TIM Output Compare configuration structure definition.
221	*/
222	typedef struct
223	{
224	uint32_t OCMode; /*!< Specifies the output mode.
225	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
226
227	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
228
229	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
230	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
231
232	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
233
234	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
235	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
236
237	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
238
239	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
240	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
241
242	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
243
244	uint32_t OCPolarity; /*!< Specifies the output polarity.
245	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
246
247	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
248
249	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
250	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
251
252	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
253
254
255	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
256	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
257
258	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
259
260	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
261	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
262
263	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
264	} LL_TIM_OC_InitTypeDef;
265
266	/**
267	* @brief TIM Input Capture configuration structure definition.
268	*/
269
270	typedef struct
271	{
272
273	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
274	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
275
276	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
277
278	uint32_t ICActiveInput; /*!< Specifies the input.
279	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
280
281	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
282
283	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
284	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
285
286	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
287
288	uint32_t ICFilter; /*!< Specifies the input capture filter.
289	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
290
291	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
292	} LL_TIM_IC_InitTypeDef;
293
294
295	/**
296	* @brief TIM Encoder interface configuration structure definition.
297	*/
298	typedef struct
299	{
300	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
301	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
302
303	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
304
305	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
306	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
307
308	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
309
310	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
311	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
312
313	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
314
315	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
316	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
317
318	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
319
320	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
321	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
322
323	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
324
325	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
326	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
327
328	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
329
330	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
331	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
332
333	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
334
335	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
336	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
337
338	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
339
340	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
341	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
342
343	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
344
345	} LL_TIM_ENCODER_InitTypeDef;
346
347	/**
348	* @brief TIM Hall sensor interface configuration structure definition.
349	*/
350	typedef struct
351	{
352
353	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
354	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
355
356	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
357
358	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
359	Prescaler must be set to get a maximum counter period longer than the
360	time interval between 2 consecutive changes on the Hall inputs.
361	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
362
363	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
364
365	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
366	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
367
368	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
369
370	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
371	A positive pulse (TRGO event) is generated with a programmable delay every time
372	a change occurs on the Hall inputs.
373	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
374
375	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
376	} LL_TIM_HALLSENSOR_InitTypeDef;
377
378	/**
379	* @brief BDTR (Break and Dead Time) structure definition
380	*/
381	typedef struct
382	{
383	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
384	This parameter can be a value of @ref TIM_LL_EC_OSSR
385
386	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
387
388	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
389
390	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
391	This parameter can be a value of @ref TIM_LL_EC_OSSI
392
393	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
394
395	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
396
397	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
398	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
399
400	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
401	has been written, their content is frozen until the next reset.*/
402
403	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
404	switching-on of the outputs.
405	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
406
407	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
408
409	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
410
411	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
412	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
413
414	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
415
416	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
417
418	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
419	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
420
421	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
422
423	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
424
425	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
426	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
427
428	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
429
430	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
431	} LL_TIM_BDTR_InitTypeDef;
432
433	/**
434	* @}
435	*/
436	#endif /* USE_FULL_LL_DRIVER */
437
438	/* Exported constants --------------------------------------------------------*/
439	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
440	* @{
441	*/
442
443	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
444	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
445	* @{
446	*/
447	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
448	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
449	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
450	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
451	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
452	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
453	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
454	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
455	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
456	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
457	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
458	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
459	/**
460	* @}
461	*/
462
463	#if defined(USE_FULL_LL_DRIVER)
464	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
465	* @{
466	*/
467	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
468	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
469	/**
470	* @}
471	*/
472
473	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
474	* @{
475	*/
476	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
477	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
478	/**
479	* @}
480	*/
481	#endif /* USE_FULL_LL_DRIVER */
482
483	/** @defgroup TIM_LL_EC_IT IT Defines
484	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
485	* @{
486	*/
487	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
488	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
489	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
490	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
491	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
492	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
493	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
494	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
495	/**
496	* @}
497	*/
498
499	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
500	* @{
501	*/
502	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
503	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
504	/**
505	* @}
506	*/
507
508	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
509	* @{
510	*/
511	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter stops counting at the next update event /
512	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter is not stopped at update event /
513	/**
514	* @}
515	*/
516
517	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
518	* @{
519	*/
520	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
521	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
522	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
523	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
524	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
525	/**
526	* @}
527	*/
528
529	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
530	* @{
531	*/
532	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
533	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
534	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
535	/**
536	* @}
537	*/
538
539	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
540	* @{
541	*/
542	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
543	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
544	/**
545	* @}
546	*/
547
548	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
549	* @{
550	*/
551	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
552	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
553	/**
554	* @}
555	*/
556
557	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
558	* @{
559	*/
560	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
561	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
562	/**
563	* @}
564	*/
565
566	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
567	* @{
568	*/
569	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
570	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
571	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
572	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
573	/**
574	* @}
575	*/
576
577	/** @defgroup TIM_LL_EC_CHANNEL Channel
578	* @{
579	*/
580	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
581	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
582	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
583	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
584	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
585	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
586	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
587	/**
588	* @}
589	*/
590
591	#if defined(USE_FULL_LL_DRIVER)
592	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
593	* @{
594	*/
595	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
596	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
597	/**
598	* @}
599	*/
600	#endif /* USE_FULL_LL_DRIVER */
601
602	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
603	* @{
604	*/
605	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
606	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
607	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
608	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
609	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
610	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
611	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
612	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
613	/**
614	* @}
615	*/
616
617	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
618	* @{
619	*/
620	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
621	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
622	/**
623	* @}
624	*/
625
626	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
627	* @{
628	*/
629	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
630	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
631	/**
632	* @}
633	*/
634
635
636	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
637	* @{
638	*/
639	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
640	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
641	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
642	/**
643	* @}
644	*/
645
646	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
647	* @{
648	*/
649	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
650	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
651	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
652	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
653	/**
654	* @}
655	*/
656
657	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
658	* @{
659	*/
660	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
661	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
662	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
663	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
664	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
665	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
666	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
667	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
668	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
669	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
670	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
671	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
672	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
673	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
674	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
675	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
676	/**
677	* @}
678	*/
679
680	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
681	* @{
682	*/
683	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
684	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
685	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
686	/**
687	* @}
688	*/
689
690	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
691	* @{
692	*/
693	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
694	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected input/
695	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
696	/**
697	* @}
698	*/
699
700	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
701	* @{
702	*/
703	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
704	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
705	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input /
706	/**
707	* @}
708	*/
709
710	/** @defgroup TIM_LL_EC_TRGO Trigger Output
711	* @{
712	*/
713	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
714	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
715	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
716	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
717	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
718	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
719	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
720	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
721	/**
722	* @}
723	*/
724
725
726	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
727	* @{
728	*/
729	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
730	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
731	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
732	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
733	/**
734	* @}
735	*/
736
737	/** @defgroup TIM_LL_EC_TS Trigger Selection
738	* @{
739	*/
740	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
741	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
742	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
743	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
744	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
745	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
746	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
747	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
748	/**
749	* @}
750	*/
751
752	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
753	* @{
754	*/
755	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
756	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
757	/**
758	* @}
759	*/
760
761	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
762	* @{
763	*/
764	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
765	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
766	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
767	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
768	/**
769	* @}
770	*/
771
772	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
773	* @{
774	*/
775	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
776	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
777	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
778	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
779	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
780	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
781	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
782	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
783	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
784	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
785	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
786	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
787	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
788	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
789	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
790	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
791	/**
792	* @}
793	*/
794
795
796	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
797	* @{
798	*/
799	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
800	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
801	/**
802	* @}
803	*/
804
805
806
807
808	/** @defgroup TIM_LL_EC_OSSI OSSI
809	* @{
810	*/
811	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
812	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
813	/**
814	* @}
815	*/
816
817	/** @defgroup TIM_LL_EC_OSSR OSSR
818	* @{
819	*/
820	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
821	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
822	/**
823	* @}
824	*/
825
826
827	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
828	* @{
829	*/
830	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
831	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
832	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
833	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
834	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
835	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
836	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
837	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
838	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
839	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
840	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
841	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
842	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
843	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
844	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
845	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
846	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
847	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
848	/**
849	* @}
850	*/
851
852	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
853	* @{
854	*/
855	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
856	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
857	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
858	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
859	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
860	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
861	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
862	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
863	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
864	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
865	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
866	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
867	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
868	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
869	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
870	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
871	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
872	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
873	/**
874	* @}
875	*/
876
877
878	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
879	* @{
880	*/
881	#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /!< TIM2_ITR1 is connected to TIM8_TRGO /
882	#define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM_OR_ITR1_RMP_0 \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to ETH_PTP /
883	#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_FS SOF /
884	#define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_HS SOF /
885	/**
886	* @}
887	*/
888
889	/** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
890	* @{
891	*/
892	#define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /!< TIM5 channel 4 is connected to GPIO /
893	#define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to LSI internal clock /
894	#define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to LSE /
895	#define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to RTC wakeup interrupt /
896	/**
897	* @}
898	*/
899
900	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
901	* @{
902	*/
903	#define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /!< TIM11 channel 1 is connected to GPIO /
904	#if defined(SPDIFRX)
905	#define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM_OR_TI1_RMP_0 \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to SPDIFRX /
906
907	/* Legacy define */
908	#define LL_TIM_TIM11_TI1_RMP_GPIO1 LL_TIM_TIM11_TI1_RMP_SPDIFRX /!< Legacy define for LL_TIM_TIM11_TI1_RMP_SPDIFRX /
909
910	#else
911	#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to GPIO /
912	#endif /* SPDIFRX */
913	#define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to GPIO /
914	#define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to HSE_RTC /
915	/**
916	* @}
917	*/
918	#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
919
920	#define LL_TIM_LPTIM_REMAP_MASK 0x10000000U
921
922	#define LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /!< TIM9_ITR1 is connected to TIM3 TRGO /
923	#define LL_TIM_TIM9_ITR1_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK \| LPTIM_OR_TIM9_ITR1_RMP) /!< TIM9_ITR1 is connected to LPTIM1 output /
924
925	#define LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /!< TIM5_ITR1 is connected to TIM3 TRGO /
926	#define LL_TIM_TIM5_ITR1_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK \| LPTIM_OR_TIM5_ITR1_RMP) /!< TIM5_ITR1 is connected to LPTIM1 output /
927
928	#define LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /!< TIM1_ITR2 is connected to TIM3 TRGO /
929	#define LL_TIM_TIM1_ITR2_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK \| LPTIM_OR_TIM1_ITR2_RMP) /!< TIM1_ITR2 is connected to LPTIM1 output /
930
931	#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
932
933	/**
934	* @}
935	*/
936
937	/* Exported macro ------------------------------------------------------------*/
938	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
939	* @{
940	*/
941
942	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
943	* @{
944	*/
945	/**
946	* @brief Write a value in TIM register.
947	* @param __INSTANCE__ TIM Instance
948	* @param __REG__ Register to be written
949	* @param __VALUE__ Value to be written in the register
950	* @retval None
951	*/
952	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
953
954	/**
955	* @brief Read a value in TIM register.
956	* @param __INSTANCE__ TIM Instance
957	* @param __REG__ Register to be read
958	* @retval Register value
959	*/
960	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
961	/**
962	* @}
963	*/
964
965	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
966	* @{
967	*/
968
969	/**
970	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
971	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
972	* @param __TIMCLK__ timer input clock frequency (in Hz)
973	* @param __CKD__ This parameter can be one of the following values:
974	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
975	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
976	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
977	* @param __DT__ deadtime duration (in ns)
978	* @retval DTG[0:7]
979	*/
980	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
981	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
982	(((uint64_t)((__DT__)1000U)) < ((64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
983	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
984	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
985	0U)
986
987	/**
988	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
989	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
990	* @param __TIMCLK__ timer input clock frequency (in Hz)
991	* @param __CNTCLK__ counter clock frequency (in Hz)
992	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
993	*/
994	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
995	(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
996
997	/**
998	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
999	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1000	* @param __TIMCLK__ timer input clock frequency (in Hz)
1001	* @param __PSC__ prescaler
1002	* @param __FREQ__ output signal frequency (in Hz)
1003	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1004	*/
1005	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1006	((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1007
1008	/**
1009	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
1010	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1011	* @param __TIMCLK__ timer input clock frequency (in Hz)
1012	* @param __PSC__ prescaler
1013	* @param __DELAY__ timer output compare active/inactive delay (in us)
1014	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
1015	*/
1016	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1017	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1018	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1019
1020	/**
1021	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
1022	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1023	* @param __TIMCLK__ timer input clock frequency (in Hz)
1024	* @param __PSC__ prescaler
1025	* @param __DELAY__ timer output compare active/inactive delay (in us)
1026	* @param __PULSE__ pulse duration (in us)
1027	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1028	*/
1029	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1030	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1031	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1032
1033	/**
1034	* @brief HELPER macro retrieving the ratio of the input capture prescaler
1035	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1036	* @param __ICPSC__ This parameter can be one of the following values:
1037	* @arg @ref LL_TIM_ICPSC_DIV1
1038	* @arg @ref LL_TIM_ICPSC_DIV2
1039	* @arg @ref LL_TIM_ICPSC_DIV4
1040	* @arg @ref LL_TIM_ICPSC_DIV8
1041	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
1042	*/
1043	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1044	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1045
1046
1047	/**
1048	* @}
1049	*/
1050
1051
1052	/**
1053	* @}
1054	*/
1055
1056	/* Exported functions --------------------------------------------------------*/
1057	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1058	* @{
1059	*/
1060
1061	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1062	* @{
1063	*/
1064	/**
1065	* @brief Enable timer counter.
1066	* @rmtoll CR1 CEN LL_TIM_EnableCounter
1067	* @param TIMx Timer instance
1068	* @retval None
1069	*/
1070	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1071	{
1072	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1073	}
1074
1075	/**
1076	* @brief Disable timer counter.
1077	* @rmtoll CR1 CEN LL_TIM_DisableCounter
1078	* @param TIMx Timer instance
1079	* @retval None
1080	*/
1081	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1082	{
1083	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1084	}
1085
1086	/**
1087	* @brief Indicates whether the timer counter is enabled.
1088	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1089	* @param TIMx Timer instance
1090	* @retval State of bit (1 or 0).
1091	*/
1092	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1093	{
1094	return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1095	}
1096
1097	/**
1098	* @brief Enable update event generation.
1099	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1100	* @param TIMx Timer instance
1101	* @retval None
1102	*/
1103	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1104	{
1105	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1106	}
1107
1108	/**
1109	* @brief Disable update event generation.
1110	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1111	* @param TIMx Timer instance
1112	* @retval None
1113	*/
1114	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1115	{
1116	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1117	}
1118
1119	/**
1120	* @brief Indicates whether update event generation is enabled.
1121	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1122	* @param TIMx Timer instance
1123	* @retval Inverted state of bit (0 or 1).
1124	*/
1125	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1126	{
1127	return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1128	}
1129
1130	/**
1131	* @brief Set update event source
1132	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1133	* generate an update interrupt or DMA request if enabled:
1134	* - Counter overflow/underflow
1135	* - Setting the UG bit
1136	* - Update generation through the slave mode controller
1137	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1138	* overflow/underflow generates an update interrupt or DMA request if enabled.
1139	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
1140	* @param TIMx Timer instance
1141	* @param UpdateSource This parameter can be one of the following values:
1142	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1143	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1144	* @retval None
1145	*/
1146	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1147	{
1148	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1149	}
1150
1151	/**
1152	* @brief Get actual event update source
1153	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
1154	* @param TIMx Timer instance
1155	* @retval Returned value can be one of the following values:
1156	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1157	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1158	*/
1159	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1160	{
1161	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1162	}
1163
1164	/**
1165	* @brief Set one pulse mode (one shot v.s. repetitive).
1166	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1167	* @param TIMx Timer instance
1168	* @param OnePulseMode This parameter can be one of the following values:
1169	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1170	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1171	* @retval None
1172	*/
1173	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1174	{
1175	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1176	}
1177
1178	/**
1179	* @brief Get actual one pulse mode.
1180	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1181	* @param TIMx Timer instance
1182	* @retval Returned value can be one of the following values:
1183	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1184	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1185	*/
1186	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1187	{
1188	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1189	}
1190
1191	/**
1192	* @brief Set the timer counter counting mode.
1193	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1194	* check whether or not the counter mode selection feature is supported
1195	* by a timer instance.
1196	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1197	* requires a timer reset to avoid unexpected direction
1198	* due to DIR bit readonly in center aligned mode.
1199	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1200	* CR1 CMS LL_TIM_SetCounterMode
1201	* @param TIMx Timer instance
1202	* @param CounterMode This parameter can be one of the following values:
1203	* @arg @ref LL_TIM_COUNTERMODE_UP
1204	* @arg @ref LL_TIM_COUNTERMODE_DOWN
1205	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1206	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1207	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1208	* @retval None
1209	*/
1210	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1211	{
1212	MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR \| TIM_CR1_CMS), CounterMode);
1213	}
1214
1215	/**
1216	* @brief Get actual counter mode.
1217	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1218	* check whether or not the counter mode selection feature is supported
1219	* by a timer instance.
1220	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1221	* CR1 CMS LL_TIM_GetCounterMode
1222	* @param TIMx Timer instance
1223	* @retval Returned value can be one of the following values:
1224	* @arg @ref LL_TIM_COUNTERMODE_UP
1225	* @arg @ref LL_TIM_COUNTERMODE_DOWN
1226	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1227	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1228	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1229	*/
1230	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1231	{
1232	uint32_t counter_mode;
1233
1234	counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1235
1236	if (counter_mode == 0U)
1237	{
1238	counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1239	}
1240
1241	return counter_mode;
1242	}
1243
1244	/**
1245	* @brief Enable auto-reload (ARR) preload.
1246	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1247	* @param TIMx Timer instance
1248	* @retval None
1249	*/
1250	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1251	{
1252	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1253	}
1254
1255	/**
1256	* @brief Disable auto-reload (ARR) preload.
1257	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1258	* @param TIMx Timer instance
1259	* @retval None
1260	*/
1261	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1262	{
1263	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1264	}
1265
1266	/**
1267	* @brief Indicates whether auto-reload (ARR) preload is enabled.
1268	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1269	* @param TIMx Timer instance
1270	* @retval State of bit (1 or 0).
1271	*/
1272	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1273	{
1274	return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1275	}
1276
1277	/**
1278	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1279	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1280	* whether or not the clock division feature is supported by the timer
1281	* instance.
1282	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
1283	* @param TIMx Timer instance
1284	* @param ClockDivision This parameter can be one of the following values:
1285	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1286	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1287	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1288	* @retval None
1289	*/
1290	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1291	{
1292	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1293	}
1294
1295	/**
1296	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1297	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1298	* whether or not the clock division feature is supported by the timer
1299	* instance.
1300	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
1301	* @param TIMx Timer instance
1302	* @retval Returned value can be one of the following values:
1303	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1304	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1305	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1306	*/
1307	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1308	{
1309	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1310	}
1311
1312	/**
1313	* @brief Set the counter value.
1314	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1315	* whether or not a timer instance supports a 32 bits counter.
1316	* @rmtoll CNT CNT LL_TIM_SetCounter
1317	* @param TIMx Timer instance
1318	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1319	* @retval None
1320	*/
1321	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1322	{
1323	WRITE_REG(TIMx->CNT, Counter);
1324	}
1325
1326	/**
1327	* @brief Get the counter value.
1328	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1329	* whether or not a timer instance supports a 32 bits counter.
1330	* @rmtoll CNT CNT LL_TIM_GetCounter
1331	* @param TIMx Timer instance
1332	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1333	*/
1334	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1335	{
1336	return (uint32_t)(READ_REG(TIMx->CNT));
1337	}
1338
1339	/**
1340	* @brief Get the current direction of the counter
1341	* @rmtoll CR1 DIR LL_TIM_GetDirection
1342	* @param TIMx Timer instance
1343	* @retval Returned value can be one of the following values:
1344	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
1345	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1346	*/
1347	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1348	{
1349	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1350	}
1351
1352	/**
1353	* @brief Set the prescaler value.
1354	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1355	* @note The prescaler can be changed on the fly as this control register is buffered. The new
1356	* prescaler ratio is taken into account at the next update event.
1357	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1358	* @rmtoll PSC PSC LL_TIM_SetPrescaler
1359	* @param TIMx Timer instance
1360	* @param Prescaler between Min_Data=0 and Max_Data=65535
1361	* @retval None
1362	*/
1363	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1364	{
1365	WRITE_REG(TIMx->PSC, Prescaler);
1366	}
1367
1368	/**
1369	* @brief Get the prescaler value.
1370	* @rmtoll PSC PSC LL_TIM_GetPrescaler
1371	* @param TIMx Timer instance
1372	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
1373	*/
1374	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1375	{
1376	return (uint32_t)(READ_REG(TIMx->PSC));
1377	}
1378
1379	/**
1380	* @brief Set the auto-reload value.
1381	* @note The counter is blocked while the auto-reload value is null.
1382	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1383	* whether or not a timer instance supports a 32 bits counter.
1384	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1385	* @rmtoll ARR ARR LL_TIM_SetAutoReload
1386	* @param TIMx Timer instance
1387	* @param AutoReload between Min_Data=0 and Max_Data=65535
1388	* @retval None
1389	*/
1390	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1391	{
1392	WRITE_REG(TIMx->ARR, AutoReload);
1393	}
1394
1395	/**
1396	* @brief Get the auto-reload value.
1397	* @rmtoll ARR ARR LL_TIM_GetAutoReload
1398	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1399	* whether or not a timer instance supports a 32 bits counter.
1400	* @param TIMx Timer instance
1401	* @retval Auto-reload value
1402	*/
1403	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1404	{
1405	return (uint32_t)(READ_REG(TIMx->ARR));
1406	}
1407
1408	/**
1409	* @brief Set the repetition counter value.
1410	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1411	* whether or not a timer instance supports a repetition counter.
1412	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1413	* @param TIMx Timer instance
1414	* @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1415	* @retval None
1416	*/
1417	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1418	{
1419	WRITE_REG(TIMx->RCR, RepetitionCounter);
1420	}
1421
1422	/**
1423	* @brief Get the repetition counter value.
1424	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1425	* whether or not a timer instance supports a repetition counter.
1426	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1427	* @param TIMx Timer instance
1428	* @retval Repetition counter value
1429	*/
1430	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1431	{
1432	return (uint32_t)(READ_REG(TIMx->RCR));
1433	}
1434
1435	/**
1436	* @}
1437	*/
1438
1439	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1440	* @{
1441	*/
1442	/**
1443	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1444	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1445	* they are updated only when a commutation event (COM) occurs.
1446	* @note Only on channels that have a complementary output.
1447	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1448	* whether or not a timer instance is able to generate a commutation event.
1449	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1450	* @param TIMx Timer instance
1451	* @retval None
1452	*/
1453	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1454	{
1455	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1456	}
1457
1458	/**
1459	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1460	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1461	* whether or not a timer instance is able to generate a commutation event.
1462	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1463	* @param TIMx Timer instance
1464	* @retval None
1465	*/
1466	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1467	{
1468	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1469	}
1470
1471	/**
1472	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1473	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1474	* whether or not a timer instance is able to generate a commutation event.
1475	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1476	* @param TIMx Timer instance
1477	* @param CCUpdateSource This parameter can be one of the following values:
1478	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1479	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1480	* @retval None
1481	*/
1482	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1483	{
1484	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1485	}
1486
1487	/**
1488	* @brief Set the trigger of the capture/compare DMA request.
1489	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1490	* @param TIMx Timer instance
1491	* @param DMAReqTrigger This parameter can be one of the following values:
1492	* @arg @ref LL_TIM_CCDMAREQUEST_CC
1493	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1494	* @retval None
1495	*/
1496	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1497	{
1498	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1499	}
1500
1501	/**
1502	* @brief Get actual trigger of the capture/compare DMA request.
1503	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1504	* @param TIMx Timer instance
1505	* @retval Returned value can be one of the following values:
1506	* @arg @ref LL_TIM_CCDMAREQUEST_CC
1507	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1508	*/
1509	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1510	{
1511	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1512	}
1513
1514	/**
1515	* @brief Set the lock level to freeze the
1516	* configuration of several capture/compare parameters.
1517	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1518	* the lock mechanism is supported by a timer instance.
1519	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1520	* @param TIMx Timer instance
1521	* @param LockLevel This parameter can be one of the following values:
1522	* @arg @ref LL_TIM_LOCKLEVEL_OFF
1523	* @arg @ref LL_TIM_LOCKLEVEL_1
1524	* @arg @ref LL_TIM_LOCKLEVEL_2
1525	* @arg @ref LL_TIM_LOCKLEVEL_3
1526	* @retval None
1527	*/
1528	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1529	{
1530	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1531	}
1532
1533	/**
1534	* @brief Enable capture/compare channels.
1535	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1536	* CCER CC1NE LL_TIM_CC_EnableChannel\n
1537	* CCER CC2E LL_TIM_CC_EnableChannel\n
1538	* CCER CC2NE LL_TIM_CC_EnableChannel\n
1539	* CCER CC3E LL_TIM_CC_EnableChannel\n
1540	* CCER CC3NE LL_TIM_CC_EnableChannel\n
1541	* CCER CC4E LL_TIM_CC_EnableChannel
1542	* @param TIMx Timer instance
1543	* @param Channels This parameter can be a combination of the following values:
1544	* @arg @ref LL_TIM_CHANNEL_CH1
1545	* @arg @ref LL_TIM_CHANNEL_CH1N
1546	* @arg @ref LL_TIM_CHANNEL_CH2
1547	* @arg @ref LL_TIM_CHANNEL_CH2N
1548	* @arg @ref LL_TIM_CHANNEL_CH3
1549	* @arg @ref LL_TIM_CHANNEL_CH3N
1550	* @arg @ref LL_TIM_CHANNEL_CH4
1551	* @retval None
1552	*/
1553	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1554	{
1555	SET_BIT(TIMx->CCER, Channels);
1556	}
1557
1558	/**
1559	* @brief Disable capture/compare channels.
1560	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1561	* CCER CC1NE LL_TIM_CC_DisableChannel\n
1562	* CCER CC2E LL_TIM_CC_DisableChannel\n
1563	* CCER CC2NE LL_TIM_CC_DisableChannel\n
1564	* CCER CC3E LL_TIM_CC_DisableChannel\n
1565	* CCER CC3NE LL_TIM_CC_DisableChannel\n
1566	* CCER CC4E LL_TIM_CC_DisableChannel
1567	* @param TIMx Timer instance
1568	* @param Channels This parameter can be a combination of the following values:
1569	* @arg @ref LL_TIM_CHANNEL_CH1
1570	* @arg @ref LL_TIM_CHANNEL_CH1N
1571	* @arg @ref LL_TIM_CHANNEL_CH2
1572	* @arg @ref LL_TIM_CHANNEL_CH2N
1573	* @arg @ref LL_TIM_CHANNEL_CH3
1574	* @arg @ref LL_TIM_CHANNEL_CH3N
1575	* @arg @ref LL_TIM_CHANNEL_CH4
1576	* @retval None
1577	*/
1578	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1579	{
1580	CLEAR_BIT(TIMx->CCER, Channels);
1581	}
1582
1583	/**
1584	* @brief Indicate whether channel(s) is(are) enabled.
1585	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1586	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1587	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1588	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1589	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1590	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1591	* CCER CC4E LL_TIM_CC_IsEnabledChannel
1592	* @param TIMx Timer instance
1593	* @param Channels This parameter can be a combination of the following values:
1594	* @arg @ref LL_TIM_CHANNEL_CH1
1595	* @arg @ref LL_TIM_CHANNEL_CH1N
1596	* @arg @ref LL_TIM_CHANNEL_CH2
1597	* @arg @ref LL_TIM_CHANNEL_CH2N
1598	* @arg @ref LL_TIM_CHANNEL_CH3
1599	* @arg @ref LL_TIM_CHANNEL_CH3N
1600	* @arg @ref LL_TIM_CHANNEL_CH4
1601	* @retval State of bit (1 or 0).
1602	*/
1603	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1604	{
1605	return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1606	}
1607
1608	/**
1609	* @}
1610	*/
1611
1612	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1613	* @{
1614	*/
1615	/**
1616	* @brief Configure an output channel.
1617	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1618	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1619	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1620	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1621	* CCER CC1P LL_TIM_OC_ConfigOutput\n
1622	* CCER CC2P LL_TIM_OC_ConfigOutput\n
1623	* CCER CC3P LL_TIM_OC_ConfigOutput\n
1624	* CCER CC4P LL_TIM_OC_ConfigOutput\n
1625	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1626	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1627	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1628	* CR2 OIS4 LL_TIM_OC_ConfigOutput
1629	* @param TIMx Timer instance
1630	* @param Channel This parameter can be one of the following values:
1631	* @arg @ref LL_TIM_CHANNEL_CH1
1632	* @arg @ref LL_TIM_CHANNEL_CH2
1633	* @arg @ref LL_TIM_CHANNEL_CH3
1634	* @arg @ref LL_TIM_CHANNEL_CH4
1635	* @param Configuration This parameter must be a combination of all the following values:
1636	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1637	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1638	* @retval None
1639	*/
1640	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1641	{
1642	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1643	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1644	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1645	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1646	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1647	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1648	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1649	}
1650
1651	/**
1652	* @brief Define the behavior of the output reference signal OCxREF from which
1653	* OCx and OCxN (when relevant) are derived.
1654	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1655	* CCMR1 OC2M LL_TIM_OC_SetMode\n
1656	* CCMR2 OC3M LL_TIM_OC_SetMode\n
1657	* CCMR2 OC4M LL_TIM_OC_SetMode
1658	* @param TIMx Timer instance
1659	* @param Channel This parameter can be one of the following values:
1660	* @arg @ref LL_TIM_CHANNEL_CH1
1661	* @arg @ref LL_TIM_CHANNEL_CH2
1662	* @arg @ref LL_TIM_CHANNEL_CH3
1663	* @arg @ref LL_TIM_CHANNEL_CH4
1664	* @param Mode This parameter can be one of the following values:
1665	* @arg @ref LL_TIM_OCMODE_FROZEN
1666	* @arg @ref LL_TIM_OCMODE_ACTIVE
1667	* @arg @ref LL_TIM_OCMODE_INACTIVE
1668	* @arg @ref LL_TIM_OCMODE_TOGGLE
1669	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1670	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1671	* @arg @ref LL_TIM_OCMODE_PWM1
1672	* @arg @ref LL_TIM_OCMODE_PWM2
1673	* @retval None
1674	*/
1675	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1676	{
1677	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1678	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1679	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1680	}
1681
1682	/**
1683	* @brief Get the output compare mode of an output channel.
1684	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1685	* CCMR1 OC2M LL_TIM_OC_GetMode\n
1686	* CCMR2 OC3M LL_TIM_OC_GetMode\n
1687	* CCMR2 OC4M LL_TIM_OC_GetMode
1688	* @param TIMx Timer instance
1689	* @param Channel This parameter can be one of the following values:
1690	* @arg @ref LL_TIM_CHANNEL_CH1
1691	* @arg @ref LL_TIM_CHANNEL_CH2
1692	* @arg @ref LL_TIM_CHANNEL_CH3
1693	* @arg @ref LL_TIM_CHANNEL_CH4
1694	* @retval Returned value can be one of the following values:
1695	* @arg @ref LL_TIM_OCMODE_FROZEN
1696	* @arg @ref LL_TIM_OCMODE_ACTIVE
1697	* @arg @ref LL_TIM_OCMODE_INACTIVE
1698	* @arg @ref LL_TIM_OCMODE_TOGGLE
1699	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1700	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1701	* @arg @ref LL_TIM_OCMODE_PWM1
1702	* @arg @ref LL_TIM_OCMODE_PWM2
1703	*/
1704	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
1705	{
1706	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1707	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1708	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1709	}
1710
1711	/**
1712	* @brief Set the polarity of an output channel.
1713	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1714	* CCER CC1NP LL_TIM_OC_SetPolarity\n
1715	* CCER CC2P LL_TIM_OC_SetPolarity\n
1716	* CCER CC2NP LL_TIM_OC_SetPolarity\n
1717	* CCER CC3P LL_TIM_OC_SetPolarity\n
1718	* CCER CC3NP LL_TIM_OC_SetPolarity\n
1719	* CCER CC4P LL_TIM_OC_SetPolarity
1720	* @param TIMx Timer instance
1721	* @param Channel This parameter can be one of the following values:
1722	* @arg @ref LL_TIM_CHANNEL_CH1
1723	* @arg @ref LL_TIM_CHANNEL_CH1N
1724	* @arg @ref LL_TIM_CHANNEL_CH2
1725	* @arg @ref LL_TIM_CHANNEL_CH2N
1726	* @arg @ref LL_TIM_CHANNEL_CH3
1727	* @arg @ref LL_TIM_CHANNEL_CH3N
1728	* @arg @ref LL_TIM_CHANNEL_CH4
1729	* @param Polarity This parameter can be one of the following values:
1730	* @arg @ref LL_TIM_OCPOLARITY_HIGH
1731	* @arg @ref LL_TIM_OCPOLARITY_LOW
1732	* @retval None
1733	*/
1734	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
1735	{
1736	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1737	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
1738	}
1739
1740	/**
1741	* @brief Get the polarity of an output channel.
1742	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
1743	* CCER CC1NP LL_TIM_OC_GetPolarity\n
1744	* CCER CC2P LL_TIM_OC_GetPolarity\n
1745	* CCER CC2NP LL_TIM_OC_GetPolarity\n
1746	* CCER CC3P LL_TIM_OC_GetPolarity\n
1747	* CCER CC3NP LL_TIM_OC_GetPolarity\n
1748	* CCER CC4P LL_TIM_OC_GetPolarity
1749	* @param TIMx Timer instance
1750	* @param Channel This parameter can be one of the following values:
1751	* @arg @ref LL_TIM_CHANNEL_CH1
1752	* @arg @ref LL_TIM_CHANNEL_CH1N
1753	* @arg @ref LL_TIM_CHANNEL_CH2
1754	* @arg @ref LL_TIM_CHANNEL_CH2N
1755	* @arg @ref LL_TIM_CHANNEL_CH3
1756	* @arg @ref LL_TIM_CHANNEL_CH3N
1757	* @arg @ref LL_TIM_CHANNEL_CH4
1758	* @retval Returned value can be one of the following values:
1759	* @arg @ref LL_TIM_OCPOLARITY_HIGH
1760	* @arg @ref LL_TIM_OCPOLARITY_LOW
1761	*/
1762	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
1763	{
1764	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1765	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
1766	}
1767
1768	/**
1769	* @brief Set the IDLE state of an output channel
1770	* @note This function is significant only for the timer instances
1771	* supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
1772	* can be used to check whether or not a timer instance provides
1773	* a break input.
1774	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
1775	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
1776	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
1777	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
1778	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
1779	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
1780	* CR2 OIS4 LL_TIM_OC_SetIdleState
1781	* @param TIMx Timer instance
1782	* @param Channel This parameter can be one of the following values:
1783	* @arg @ref LL_TIM_CHANNEL_CH1
1784	* @arg @ref LL_TIM_CHANNEL_CH1N
1785	* @arg @ref LL_TIM_CHANNEL_CH2
1786	* @arg @ref LL_TIM_CHANNEL_CH2N
1787	* @arg @ref LL_TIM_CHANNEL_CH3
1788	* @arg @ref LL_TIM_CHANNEL_CH3N
1789	* @arg @ref LL_TIM_CHANNEL_CH4
1790	* @param IdleState This parameter can be one of the following values:
1791	* @arg @ref LL_TIM_OCIDLESTATE_LOW
1792	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
1793	* @retval None
1794	*/
1795	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
1796	{
1797	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1798	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
1799	}
1800
1801	/**
1802	* @brief Get the IDLE state of an output channel
1803	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
1804	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
1805	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
1806	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
1807	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
1808	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
1809	* CR2 OIS4 LL_TIM_OC_GetIdleState
1810	* @param TIMx Timer instance
1811	* @param Channel This parameter can be one of the following values:
1812	* @arg @ref LL_TIM_CHANNEL_CH1
1813	* @arg @ref LL_TIM_CHANNEL_CH1N
1814	* @arg @ref LL_TIM_CHANNEL_CH2
1815	* @arg @ref LL_TIM_CHANNEL_CH2N
1816	* @arg @ref LL_TIM_CHANNEL_CH3
1817	* @arg @ref LL_TIM_CHANNEL_CH3N
1818	* @arg @ref LL_TIM_CHANNEL_CH4
1819	* @retval Returned value can be one of the following values:
1820	* @arg @ref LL_TIM_OCIDLESTATE_LOW
1821	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
1822	*/
1823	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
1824	{
1825	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1826	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
1827	}
1828
1829	/**
1830	* @brief Enable fast mode for the output channel.
1831	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
1832	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
1833	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
1834	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
1835	* CCMR2 OC4FE LL_TIM_OC_EnableFast
1836	* @param TIMx Timer instance
1837	* @param Channel This parameter can be one of the following values:
1838	* @arg @ref LL_TIM_CHANNEL_CH1
1839	* @arg @ref LL_TIM_CHANNEL_CH2
1840	* @arg @ref LL_TIM_CHANNEL_CH3
1841	* @arg @ref LL_TIM_CHANNEL_CH4
1842	* @retval None
1843	*/
1844	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1845	{
1846	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1847	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1848	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1849
1850	}
1851
1852	/**
1853	* @brief Disable fast mode for the output channel.
1854	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
1855	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
1856	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
1857	* CCMR2 OC4FE LL_TIM_OC_DisableFast
1858	* @param TIMx Timer instance
1859	* @param Channel This parameter can be one of the following values:
1860	* @arg @ref LL_TIM_CHANNEL_CH1
1861	* @arg @ref LL_TIM_CHANNEL_CH2
1862	* @arg @ref LL_TIM_CHANNEL_CH3
1863	* @arg @ref LL_TIM_CHANNEL_CH4
1864	* @retval None
1865	*/
1866	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1867	{
1868	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1869	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1870	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1871
1872	}
1873
1874	/**
1875	* @brief Indicates whether fast mode is enabled for the output channel.
1876	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
1877	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
1878	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
1879	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
1880	* @param TIMx Timer instance
1881	* @param Channel This parameter can be one of the following values:
1882	* @arg @ref LL_TIM_CHANNEL_CH1
1883	* @arg @ref LL_TIM_CHANNEL_CH2
1884	* @arg @ref LL_TIM_CHANNEL_CH3
1885	* @arg @ref LL_TIM_CHANNEL_CH4
1886	* @retval State of bit (1 or 0).
1887	*/
1888	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
1889	{
1890	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1891	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1892	uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
1893	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1894	}
1895
1896	/**
1897	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
1898	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
1899	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
1900	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
1901	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
1902	* @param TIMx Timer instance
1903	* @param Channel This parameter can be one of the following values:
1904	* @arg @ref LL_TIM_CHANNEL_CH1
1905	* @arg @ref LL_TIM_CHANNEL_CH2
1906	* @arg @ref LL_TIM_CHANNEL_CH3
1907	* @arg @ref LL_TIM_CHANNEL_CH4
1908	* @retval None
1909	*/
1910	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1911	{
1912	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1913	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1914	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1915	}
1916
1917	/**
1918	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
1919	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
1920	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
1921	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
1922	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
1923	* @param TIMx Timer instance
1924	* @param Channel This parameter can be one of the following values:
1925	* @arg @ref LL_TIM_CHANNEL_CH1
1926	* @arg @ref LL_TIM_CHANNEL_CH2
1927	* @arg @ref LL_TIM_CHANNEL_CH3
1928	* @arg @ref LL_TIM_CHANNEL_CH4
1929	* @retval None
1930	*/
1931	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1932	{
1933	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1934	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1935	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1936	}
1937
1938	/**
1939	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
1940	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
1941	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
1942	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
1943	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
1944	* @param TIMx Timer instance
1945	* @param Channel This parameter can be one of the following values:
1946	* @arg @ref LL_TIM_CHANNEL_CH1
1947	* @arg @ref LL_TIM_CHANNEL_CH2
1948	* @arg @ref LL_TIM_CHANNEL_CH3
1949	* @arg @ref LL_TIM_CHANNEL_CH4
1950	* @retval State of bit (1 or 0).
1951	*/
1952	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
1953	{
1954	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1955	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1956	uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
1957	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1958	}
1959
1960	/**
1961	* @brief Enable clearing the output channel on an external event.
1962	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
1963	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1964	* or not a timer instance can clear the OCxREF signal on an external event.
1965	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
1966	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
1967	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
1968	* CCMR2 OC4CE LL_TIM_OC_EnableClear
1969	* @param TIMx Timer instance
1970	* @param Channel This parameter can be one of the following values:
1971	* @arg @ref LL_TIM_CHANNEL_CH1
1972	* @arg @ref LL_TIM_CHANNEL_CH2
1973	* @arg @ref LL_TIM_CHANNEL_CH3
1974	* @arg @ref LL_TIM_CHANNEL_CH4
1975	* @retval None
1976	*/
1977	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1978	{
1979	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1980	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1981	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1982	}
1983
1984	/**
1985	* @brief Disable clearing the output channel on an external event.
1986	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1987	* or not a timer instance can clear the OCxREF signal on an external event.
1988	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
1989	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
1990	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
1991	* CCMR2 OC4CE LL_TIM_OC_DisableClear
1992	* @param TIMx Timer instance
1993	* @param Channel This parameter can be one of the following values:
1994	* @arg @ref LL_TIM_CHANNEL_CH1
1995	* @arg @ref LL_TIM_CHANNEL_CH2
1996	* @arg @ref LL_TIM_CHANNEL_CH3
1997	* @arg @ref LL_TIM_CHANNEL_CH4
1998	* @retval None
1999	*/
2000	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2001	{
2002	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2003	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2004	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2005	}
2006
2007	/**
2008	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2009	* @note This function enables clearing the output channel on an external event.
2010	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2011	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2012	* or not a timer instance can clear the OCxREF signal on an external event.
2013	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2014	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2015	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2016	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2017	* @param TIMx Timer instance
2018	* @param Channel This parameter can be one of the following values:
2019	* @arg @ref LL_TIM_CHANNEL_CH1
2020	* @arg @ref LL_TIM_CHANNEL_CH2
2021	* @arg @ref LL_TIM_CHANNEL_CH3
2022	* @arg @ref LL_TIM_CHANNEL_CH4
2023	* @retval State of bit (1 or 0).
2024	*/
2025	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2026	{
2027	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2028	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2029	uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2030	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2031	}
2032
2033	/**
2034	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
2035	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2036	* dead-time insertion feature is supported by a timer instance.
2037	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2038	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2039	* @param TIMx Timer instance
2040	* @param DeadTime between Min_Data=0 and Max_Data=255
2041	* @retval None
2042	*/
2043	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2044	{
2045	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2046	}
2047
2048	/**
2049	* @brief Set compare value for output channel 1 (TIMx_CCR1).
2050	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2051	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2052	* whether or not a timer instance supports a 32 bits counter.
2053	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2054	* output channel 1 is supported by a timer instance.
2055	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2056	* @param TIMx Timer instance
2057	* @param CompareValue between Min_Data=0 and Max_Data=65535
2058	* @retval None
2059	*/
2060	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2061	{
2062	WRITE_REG(TIMx->CCR1, CompareValue);
2063	}
2064
2065	/**
2066	* @brief Set compare value for output channel 2 (TIMx_CCR2).
2067	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2068	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2069	* whether or not a timer instance supports a 32 bits counter.
2070	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2071	* output channel 2 is supported by a timer instance.
2072	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2073	* @param TIMx Timer instance
2074	* @param CompareValue between Min_Data=0 and Max_Data=65535
2075	* @retval None
2076	*/
2077	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2078	{
2079	WRITE_REG(TIMx->CCR2, CompareValue);
2080	}
2081
2082	/**
2083	* @brief Set compare value for output channel 3 (TIMx_CCR3).
2084	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2085	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2086	* whether or not a timer instance supports a 32 bits counter.
2087	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2088	* output channel is supported by a timer instance.
2089	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2090	* @param TIMx Timer instance
2091	* @param CompareValue between Min_Data=0 and Max_Data=65535
2092	* @retval None
2093	*/
2094	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2095	{
2096	WRITE_REG(TIMx->CCR3, CompareValue);
2097	}
2098
2099	/**
2100	* @brief Set compare value for output channel 4 (TIMx_CCR4).
2101	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2102	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2103	* whether or not a timer instance supports a 32 bits counter.
2104	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2105	* output channel 4 is supported by a timer instance.
2106	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2107	* @param TIMx Timer instance
2108	* @param CompareValue between Min_Data=0 and Max_Data=65535
2109	* @retval None
2110	*/
2111	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2112	{
2113	WRITE_REG(TIMx->CCR4, CompareValue);
2114	}
2115
2116	/**
2117	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
2118	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2119	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2120	* whether or not a timer instance supports a 32 bits counter.
2121	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2122	* output channel 1 is supported by a timer instance.
2123	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2124	* @param TIMx Timer instance
2125	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2126	*/
2127	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2128	{
2129	return (uint32_t)(READ_REG(TIMx->CCR1));
2130	}
2131
2132	/**
2133	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
2134	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2135	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2136	* whether or not a timer instance supports a 32 bits counter.
2137	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2138	* output channel 2 is supported by a timer instance.
2139	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2140	* @param TIMx Timer instance
2141	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2142	*/
2143	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2144	{
2145	return (uint32_t)(READ_REG(TIMx->CCR2));
2146	}
2147
2148	/**
2149	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
2150	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2151	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2152	* whether or not a timer instance supports a 32 bits counter.
2153	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2154	* output channel 3 is supported by a timer instance.
2155	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2156	* @param TIMx Timer instance
2157	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2158	*/
2159	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2160	{
2161	return (uint32_t)(READ_REG(TIMx->CCR3));
2162	}
2163
2164	/**
2165	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
2166	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2167	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2168	* whether or not a timer instance supports a 32 bits counter.
2169	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2170	* output channel 4 is supported by a timer instance.
2171	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2172	* @param TIMx Timer instance
2173	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2174	*/
2175	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2176	{
2177	return (uint32_t)(READ_REG(TIMx->CCR4));
2178	}
2179
2180	/**
2181	* @}
2182	*/
2183
2184	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2185	* @{
2186	*/
2187	/**
2188	* @brief Configure input channel.
2189	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2190	* CCMR1 IC1PSC LL_TIM_IC_Config\n
2191	* CCMR1 IC1F LL_TIM_IC_Config\n
2192	* CCMR1 CC2S LL_TIM_IC_Config\n
2193	* CCMR1 IC2PSC LL_TIM_IC_Config\n
2194	* CCMR1 IC2F LL_TIM_IC_Config\n
2195	* CCMR2 CC3S LL_TIM_IC_Config\n
2196	* CCMR2 IC3PSC LL_TIM_IC_Config\n
2197	* CCMR2 IC3F LL_TIM_IC_Config\n
2198	* CCMR2 CC4S LL_TIM_IC_Config\n
2199	* CCMR2 IC4PSC LL_TIM_IC_Config\n
2200	* CCMR2 IC4F LL_TIM_IC_Config\n
2201	* CCER CC1P LL_TIM_IC_Config\n
2202	* CCER CC1NP LL_TIM_IC_Config\n
2203	* CCER CC2P LL_TIM_IC_Config\n
2204	* CCER CC2NP LL_TIM_IC_Config\n
2205	* CCER CC3P LL_TIM_IC_Config\n
2206	* CCER CC3NP LL_TIM_IC_Config\n
2207	* CCER CC4P LL_TIM_IC_Config\n
2208	* CCER CC4NP LL_TIM_IC_Config
2209	* @param TIMx Timer instance
2210	* @param Channel This parameter can be one of the following values:
2211	* @arg @ref LL_TIM_CHANNEL_CH1
2212	* @arg @ref LL_TIM_CHANNEL_CH2
2213	* @arg @ref LL_TIM_CHANNEL_CH3
2214	* @arg @ref LL_TIM_CHANNEL_CH4
2215	* @param Configuration This parameter must be a combination of all the following values:
2216	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2217	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2218	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2219	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2220	* @retval None
2221	*/
2222	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2223	{
2224	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2225	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2226	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2227	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
2228	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2229	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2230	}
2231
2232	/**
2233	* @brief Set the active input.
2234	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2235	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2236	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2237	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
2238	* @param TIMx Timer instance
2239	* @param Channel This parameter can be one of the following values:
2240	* @arg @ref LL_TIM_CHANNEL_CH1
2241	* @arg @ref LL_TIM_CHANNEL_CH2
2242	* @arg @ref LL_TIM_CHANNEL_CH3
2243	* @arg @ref LL_TIM_CHANNEL_CH4
2244	* @param ICActiveInput This parameter can be one of the following values:
2245	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2246	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2247	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
2248	* @retval None
2249	*/
2250	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2251	{
2252	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2253	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2254	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2255	}
2256
2257	/**
2258	* @brief Get the current active input.
2259	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2260	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2261	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2262	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
2263	* @param TIMx Timer instance
2264	* @param Channel This parameter can be one of the following values:
2265	* @arg @ref LL_TIM_CHANNEL_CH1
2266	* @arg @ref LL_TIM_CHANNEL_CH2
2267	* @arg @ref LL_TIM_CHANNEL_CH3
2268	* @arg @ref LL_TIM_CHANNEL_CH4
2269	* @retval Returned value can be one of the following values:
2270	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2271	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2272	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
2273	*/
2274	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2275	{
2276	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2277	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2278	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2279	}
2280
2281	/**
2282	* @brief Set the prescaler of input channel.
2283	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2284	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2285	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2286	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2287	* @param TIMx Timer instance
2288	* @param Channel This parameter can be one of the following values:
2289	* @arg @ref LL_TIM_CHANNEL_CH1
2290	* @arg @ref LL_TIM_CHANNEL_CH2
2291	* @arg @ref LL_TIM_CHANNEL_CH3
2292	* @arg @ref LL_TIM_CHANNEL_CH4
2293	* @param ICPrescaler This parameter can be one of the following values:
2294	* @arg @ref LL_TIM_ICPSC_DIV1
2295	* @arg @ref LL_TIM_ICPSC_DIV2
2296	* @arg @ref LL_TIM_ICPSC_DIV4
2297	* @arg @ref LL_TIM_ICPSC_DIV8
2298	* @retval None
2299	*/
2300	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2301	{
2302	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2303	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2304	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2305	}
2306
2307	/**
2308	* @brief Get the current prescaler value acting on an input channel.
2309	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2310	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2311	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2312	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2313	* @param TIMx Timer instance
2314	* @param Channel This parameter can be one of the following values:
2315	* @arg @ref LL_TIM_CHANNEL_CH1
2316	* @arg @ref LL_TIM_CHANNEL_CH2
2317	* @arg @ref LL_TIM_CHANNEL_CH3
2318	* @arg @ref LL_TIM_CHANNEL_CH4
2319	* @retval Returned value can be one of the following values:
2320	* @arg @ref LL_TIM_ICPSC_DIV1
2321	* @arg @ref LL_TIM_ICPSC_DIV2
2322	* @arg @ref LL_TIM_ICPSC_DIV4
2323	* @arg @ref LL_TIM_ICPSC_DIV8
2324	*/
2325	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2326	{
2327	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2328	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2329	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2330	}
2331
2332	/**
2333	* @brief Set the input filter duration.
2334	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2335	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
2336	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
2337	* CCMR2 IC4F LL_TIM_IC_SetFilter
2338	* @param TIMx Timer instance
2339	* @param Channel This parameter can be one of the following values:
2340	* @arg @ref LL_TIM_CHANNEL_CH1
2341	* @arg @ref LL_TIM_CHANNEL_CH2
2342	* @arg @ref LL_TIM_CHANNEL_CH3
2343	* @arg @ref LL_TIM_CHANNEL_CH4
2344	* @param ICFilter This parameter can be one of the following values:
2345	* @arg @ref LL_TIM_IC_FILTER_FDIV1
2346	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2347	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2348	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2349	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2350	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2351	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2352	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2353	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2354	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2355	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2356	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2357	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2358	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2359	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2360	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2361	* @retval None
2362	*/
2363	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2364	{
2365	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2366	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2367	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2368	}
2369
2370	/**
2371	* @brief Get the input filter duration.
2372	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2373	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
2374	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
2375	* CCMR2 IC4F LL_TIM_IC_GetFilter
2376	* @param TIMx Timer instance
2377	* @param Channel This parameter can be one of the following values:
2378	* @arg @ref LL_TIM_CHANNEL_CH1
2379	* @arg @ref LL_TIM_CHANNEL_CH2
2380	* @arg @ref LL_TIM_CHANNEL_CH3
2381	* @arg @ref LL_TIM_CHANNEL_CH4
2382	* @retval Returned value can be one of the following values:
2383	* @arg @ref LL_TIM_IC_FILTER_FDIV1
2384	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2385	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2386	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2387	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2388	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2389	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2390	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2391	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2392	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2393	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2394	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2395	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2396	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2397	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2398	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2399	*/
2400	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2401	{
2402	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2403	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2404	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2405	}
2406
2407	/**
2408	* @brief Set the input channel polarity.
2409	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2410	* CCER CC1NP LL_TIM_IC_SetPolarity\n
2411	* CCER CC2P LL_TIM_IC_SetPolarity\n
2412	* CCER CC2NP LL_TIM_IC_SetPolarity\n
2413	* CCER CC3P LL_TIM_IC_SetPolarity\n
2414	* CCER CC3NP LL_TIM_IC_SetPolarity\n
2415	* CCER CC4P LL_TIM_IC_SetPolarity\n
2416	* CCER CC4NP LL_TIM_IC_SetPolarity
2417	* @param TIMx Timer instance
2418	* @param Channel This parameter can be one of the following values:
2419	* @arg @ref LL_TIM_CHANNEL_CH1
2420	* @arg @ref LL_TIM_CHANNEL_CH2
2421	* @arg @ref LL_TIM_CHANNEL_CH3
2422	* @arg @ref LL_TIM_CHANNEL_CH4
2423	* @param ICPolarity This parameter can be one of the following values:
2424	* @arg @ref LL_TIM_IC_POLARITY_RISING
2425	* @arg @ref LL_TIM_IC_POLARITY_FALLING
2426	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2427	* @retval None
2428	*/
2429	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2430	{
2431	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2432	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2433	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2434	}
2435
2436	/**
2437	* @brief Get the current input channel polarity.
2438	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2439	* CCER CC1NP LL_TIM_IC_GetPolarity\n
2440	* CCER CC2P LL_TIM_IC_GetPolarity\n
2441	* CCER CC2NP LL_TIM_IC_GetPolarity\n
2442	* CCER CC3P LL_TIM_IC_GetPolarity\n
2443	* CCER CC3NP LL_TIM_IC_GetPolarity\n
2444	* CCER CC4P LL_TIM_IC_GetPolarity\n
2445	* CCER CC4NP LL_TIM_IC_GetPolarity
2446	* @param TIMx Timer instance
2447	* @param Channel This parameter can be one of the following values:
2448	* @arg @ref LL_TIM_CHANNEL_CH1
2449	* @arg @ref LL_TIM_CHANNEL_CH2
2450	* @arg @ref LL_TIM_CHANNEL_CH3
2451	* @arg @ref LL_TIM_CHANNEL_CH4
2452	* @retval Returned value can be one of the following values:
2453	* @arg @ref LL_TIM_IC_POLARITY_RISING
2454	* @arg @ref LL_TIM_IC_POLARITY_FALLING
2455	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2456	*/
2457	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2458	{
2459	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2460	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2461	SHIFT_TAB_CCxP[iChannel]);
2462	}
2463
2464	/**
2465	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2466	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2467	* a timer instance provides an XOR input.
2468	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2469	* @param TIMx Timer instance
2470	* @retval None
2471	*/
2472	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2473	{
2474	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2475	}
2476
2477	/**
2478	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2479	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2480	* a timer instance provides an XOR input.
2481	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2482	* @param TIMx Timer instance
2483	* @retval None
2484	*/
2485	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2486	{
2487	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2488	}
2489
2490	/**
2491	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2492	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2493	* a timer instance provides an XOR input.
2494	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2495	* @param TIMx Timer instance
2496	* @retval State of bit (1 or 0).
2497	*/
2498	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
2499	{
2500	return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2501	}
2502
2503	/**
2504	* @brief Get captured value for input channel 1.
2505	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2506	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2507	* whether or not a timer instance supports a 32 bits counter.
2508	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2509	* input channel 1 is supported by a timer instance.
2510	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2511	* @param TIMx Timer instance
2512	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2513	*/
2514	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
2515	{
2516	return (uint32_t)(READ_REG(TIMx->CCR1));
2517	}
2518
2519	/**
2520	* @brief Get captured value for input channel 2.
2521	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2522	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2523	* whether or not a timer instance supports a 32 bits counter.
2524	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2525	* input channel 2 is supported by a timer instance.
2526	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2527	* @param TIMx Timer instance
2528	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2529	*/
2530	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
2531	{
2532	return (uint32_t)(READ_REG(TIMx->CCR2));
2533	}
2534
2535	/**
2536	* @brief Get captured value for input channel 3.
2537	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2538	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2539	* whether or not a timer instance supports a 32 bits counter.
2540	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2541	* input channel 3 is supported by a timer instance.
2542	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2543	* @param TIMx Timer instance
2544	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2545	*/
2546	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
2547	{
2548	return (uint32_t)(READ_REG(TIMx->CCR3));
2549	}
2550
2551	/**
2552	* @brief Get captured value for input channel 4.
2553	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2554	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2555	* whether or not a timer instance supports a 32 bits counter.
2556	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2557	* input channel 4 is supported by a timer instance.
2558	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2559	* @param TIMx Timer instance
2560	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2561	*/
2562	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
2563	{
2564	return (uint32_t)(READ_REG(TIMx->CCR4));
2565	}
2566
2567	/**
2568	* @}
2569	*/
2570
2571	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2572	* @{
2573	*/
2574	/**
2575	* @brief Enable external clock mode 2.
2576	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2577	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2578	* whether or not a timer instance supports external clock mode2.
2579	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2580	* @param TIMx Timer instance
2581	* @retval None
2582	*/
2583	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2584	{
2585	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2586	}
2587
2588	/**
2589	* @brief Disable external clock mode 2.
2590	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2591	* whether or not a timer instance supports external clock mode2.
2592	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2593	* @param TIMx Timer instance
2594	* @retval None
2595	*/
2596	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2597	{
2598	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2599	}
2600
2601	/**
2602	* @brief Indicate whether external clock mode 2 is enabled.
2603	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2604	* whether or not a timer instance supports external clock mode2.
2605	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2606	* @param TIMx Timer instance
2607	* @retval State of bit (1 or 0).
2608	*/
2609	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
2610	{
2611	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
2612	}
2613
2614	/**
2615	* @brief Set the clock source of the counter clock.
2616	* @note when selected clock source is external clock mode 1, the timer input
2617	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2618	* function. This timer input must be configured by calling
2619	* the @ref LL_TIM_IC_Config() function.
2620	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2621	* whether or not a timer instance supports external clock mode1.
2622	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2623	* whether or not a timer instance supports external clock mode2.
2624	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
2625	* SMCR ECE LL_TIM_SetClockSource
2626	* @param TIMx Timer instance
2627	* @param ClockSource This parameter can be one of the following values:
2628	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
2629	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
2630	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
2631	* @retval None
2632	*/
2633	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
2634	{
2635	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
2636	}
2637
2638	/**
2639	* @brief Set the encoder interface mode.
2640	* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2641	* whether or not a timer instance supports the encoder mode.
2642	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
2643	* @param TIMx Timer instance
2644	* @param EncoderMode This parameter can be one of the following values:
2645	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
2646	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
2647	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
2648	* @retval None
2649	*/
2650	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
2651	{
2652	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
2653	}
2654
2655	/**
2656	* @}
2657	*/
2658
2659	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
2660	* @{
2661	*/
2662	/**
2663	* @brief Set the trigger output (TRGO) used for timer synchronization .
2664	* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2665	* whether or not a timer instance can operate as a master timer.
2666	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
2667	* @param TIMx Timer instance
2668	* @param TimerSynchronization This parameter can be one of the following values:
2669	* @arg @ref LL_TIM_TRGO_RESET
2670	* @arg @ref LL_TIM_TRGO_ENABLE
2671	* @arg @ref LL_TIM_TRGO_UPDATE
2672	* @arg @ref LL_TIM_TRGO_CC1IF
2673	* @arg @ref LL_TIM_TRGO_OC1REF
2674	* @arg @ref LL_TIM_TRGO_OC2REF
2675	* @arg @ref LL_TIM_TRGO_OC3REF
2676	* @arg @ref LL_TIM_TRGO_OC4REF
2677	* @retval None
2678	*/
2679	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
2680	{
2681	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
2682	}
2683
2684	/**
2685	* @brief Set the synchronization mode of a slave timer.
2686	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2687	* a timer instance can operate as a slave timer.
2688	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
2689	* @param TIMx Timer instance
2690	* @param SlaveMode This parameter can be one of the following values:
2691	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
2692	* @arg @ref LL_TIM_SLAVEMODE_RESET
2693	* @arg @ref LL_TIM_SLAVEMODE_GATED
2694	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
2695	* @retval None
2696	*/
2697	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
2698	{
2699	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
2700	}
2701
2702	/**
2703	* @brief Set the selects the trigger input to be used to synchronize the counter.
2704	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2705	* a timer instance can operate as a slave timer.
2706	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
2707	* @param TIMx Timer instance
2708	* @param TriggerInput This parameter can be one of the following values:
2709	* @arg @ref LL_TIM_TS_ITR0
2710	* @arg @ref LL_TIM_TS_ITR1
2711	* @arg @ref LL_TIM_TS_ITR2
2712	* @arg @ref LL_TIM_TS_ITR3
2713	* @arg @ref LL_TIM_TS_TI1F_ED
2714	* @arg @ref LL_TIM_TS_TI1FP1
2715	* @arg @ref LL_TIM_TS_TI2FP2
2716	* @arg @ref LL_TIM_TS_ETRF
2717	* @retval None
2718	*/
2719	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
2720	{
2721	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
2722	}
2723
2724	/**
2725	* @brief Enable the Master/Slave mode.
2726	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2727	* a timer instance can operate as a slave timer.
2728	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
2729	* @param TIMx Timer instance
2730	* @retval None
2731	*/
2732	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
2733	{
2734	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2735	}
2736
2737	/**
2738	* @brief Disable the Master/Slave mode.
2739	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2740	* a timer instance can operate as a slave timer.
2741	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
2742	* @param TIMx Timer instance
2743	* @retval None
2744	*/
2745	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
2746	{
2747	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2748	}
2749
2750	/**
2751	* @brief Indicates whether the Master/Slave mode is enabled.
2752	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2753	* a timer instance can operate as a slave timer.
2754	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
2755	* @param TIMx Timer instance
2756	* @retval State of bit (1 or 0).
2757	*/
2758	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
2759	{
2760	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
2761	}
2762
2763	/**
2764	* @brief Configure the external trigger (ETR) input.
2765	* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2766	* a timer instance provides an external trigger input.
2767	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
2768	* SMCR ETPS LL_TIM_ConfigETR\n
2769	* SMCR ETF LL_TIM_ConfigETR
2770	* @param TIMx Timer instance
2771	* @param ETRPolarity This parameter can be one of the following values:
2772	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
2773	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
2774	* @param ETRPrescaler This parameter can be one of the following values:
2775	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
2776	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
2777	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
2778	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
2779	* @param ETRFilter This parameter can be one of the following values:
2780	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
2781	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
2782	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
2783	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
2784	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
2785	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
2786	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
2787	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
2788	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
2789	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
2790	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
2791	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
2792	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
2793	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
2794	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
2795	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
2796	* @retval None
2797	*/
2798	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
2799	uint32_t ETRFilter)
2800	{
2801	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
2802	}
2803
2804	/**
2805	* @}
2806	*/
2807
2808	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
2809	* @{
2810	*/
2811	/**
2812	* @brief Enable the break function.
2813	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2814	* a timer instance provides a break input.
2815	* @rmtoll BDTR BKE LL_TIM_EnableBRK
2816	* @param TIMx Timer instance
2817	* @retval None
2818	*/
2819	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
2820	{
2821	__IO uint32_t tmpreg;
2822	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2823	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2824	tmpreg = READ_REG(TIMx->BDTR);
2825	(void)(tmpreg);
2826	}
2827
2828	/**
2829	* @brief Disable the break function.
2830	* @rmtoll BDTR BKE LL_TIM_DisableBRK
2831	* @param TIMx Timer instance
2832	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2833	* a timer instance provides a break input.
2834	* @retval None
2835	*/
2836	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
2837	{
2838	__IO uint32_t tmpreg;
2839	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2840	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2841	tmpreg = READ_REG(TIMx->BDTR);
2842	(void)(tmpreg);
2843	}
2844
2845	/**
2846	* @brief Configure the break input.
2847	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2848	* a timer instance provides a break input.
2849	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
2850	* @param TIMx Timer instance
2851	* @param BreakPolarity This parameter can be one of the following values:
2852	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
2853	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
2854	* @retval None
2855	*/
2856	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
2857	{
2858	__IO uint32_t tmpreg;
2859	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
2860	/* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
2861	tmpreg = READ_REG(TIMx->BDTR);
2862	(void)(tmpreg);
2863	}
2864
2865	/**
2866	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
2867	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2868	* a timer instance provides a break input.
2869	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
2870	* BDTR OSSR LL_TIM_SetOffStates
2871	* @param TIMx Timer instance
2872	* @param OffStateIdle This parameter can be one of the following values:
2873	* @arg @ref LL_TIM_OSSI_DISABLE
2874	* @arg @ref LL_TIM_OSSI_ENABLE
2875	* @param OffStateRun This parameter can be one of the following values:
2876	* @arg @ref LL_TIM_OSSR_DISABLE
2877	* @arg @ref LL_TIM_OSSR_ENABLE
2878	* @retval None
2879	*/
2880	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
2881	{
2882	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
2883	}
2884
2885	/**
2886	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
2887	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2888	* a timer instance provides a break input.
2889	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
2890	* @param TIMx Timer instance
2891	* @retval None
2892	*/
2893	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
2894	{
2895	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2896	}
2897
2898	/**
2899	* @brief Disable automatic output (MOE can be set only by software).
2900	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2901	* a timer instance provides a break input.
2902	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
2903	* @param TIMx Timer instance
2904	* @retval None
2905	*/
2906	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
2907	{
2908	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2909	}
2910
2911	/**
2912	* @brief Indicate whether automatic output is enabled.
2913	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2914	* a timer instance provides a break input.
2915	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
2916	* @param TIMx Timer instance
2917	* @retval State of bit (1 or 0).
2918	*/
2919	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
2920	{
2921	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
2922	}
2923
2924	/**
2925	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
2926	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2927	* software and is reset in case of break or break2 event
2928	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2929	* a timer instance provides a break input.
2930	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
2931	* @param TIMx Timer instance
2932	* @retval None
2933	*/
2934	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
2935	{
2936	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2937	}
2938
2939	/**
2940	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
2941	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2942	* software and is reset in case of break or break2 event.
2943	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2944	* a timer instance provides a break input.
2945	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
2946	* @param TIMx Timer instance
2947	* @retval None
2948	*/
2949	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
2950	{
2951	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2952	}
2953
2954	/**
2955	* @brief Indicates whether outputs are enabled.
2956	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2957	* a timer instance provides a break input.
2958	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
2959	* @param TIMx Timer instance
2960	* @retval State of bit (1 or 0).
2961	*/
2962	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
2963	{
2964	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
2965	}
2966
2967	/**
2968	* @}
2969	*/
2970
2971	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
2972	* @{
2973	*/
2974	/**
2975	* @brief Configures the timer DMA burst feature.
2976	* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
2977	* not a timer instance supports the DMA burst mode.
2978	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
2979	* DCR DBA LL_TIM_ConfigDMABurst
2980	* @param TIMx Timer instance
2981	* @param DMABurstBaseAddress This parameter can be one of the following values:
2982	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
2983	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
2984	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
2985	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
2986	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
2987	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
2988	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
2989	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
2990	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
2991	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
2992	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
2993	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
2994	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
2995	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
2996	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
2997	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
2998	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
2999	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3000	* @param DMABurstLength This parameter can be one of the following values:
3001	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3002	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3003	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3004	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3005	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3006	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3007	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3008	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3009	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3010	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3011	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3012	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3013	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3014	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3015	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3016	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3017	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3018	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3019	* @retval None
3020	*/
3021	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3022	{
3023	MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL \| TIM_DCR_DBA), (DMABurstBaseAddress \| DMABurstLength));
3024	}
3025
3026	/**
3027	* @}
3028	*/
3029
3030	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3031	* @{
3032	*/
3033	/**
3034	* @brief Remap TIM inputs (input channel, internal/external triggers).
3035	* @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3036	* a some timer inputs can be remapped.
3037	* @rmtoll TIM1_OR ITR2_RMP LL_TIM_SetRemap\n
3038	* TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
3039	* TIM5_OR ITR1_RMP LL_TIM_SetRemap\n
3040	* TIM5_OR TI4_RMP LL_TIM_SetRemap\n
3041	* TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
3042	* TIM11_OR TI1_RMP LL_TIM_SetRemap\n
3043	* LPTIM1_OR OR LL_TIM_SetRemap
3044	* @param TIMx Timer instance
3045	* @param Remap Remap param depends on the TIMx. Description available only
3046	* in CHM version of the User Manual (not in .pdf).
3047	* Otherwise see Reference Manual description of OR registers.
3048	*
3049	* Below description summarizes "Timer Instance" and "Remap" param combinations:
3050	*
3051	* TIM1: one of the following values
3052	*
3053	* ITR2_RMP can be one of the following values
3054	* @arg @ref LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO (*)
3055	* @arg @ref LL_TIM_TIM1_ITR2_RMP_LPTIM (*)
3056	*
3057	* TIM2: one of the following values
3058	*
3059	* ITR1_RMP can be one of the following values
3060	* @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3061	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3062	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
3063	*
3064	* TIM5: one of the following values
3065	*
3066	* @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
3067	* @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
3068	* @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
3069	* @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
3070	* @arg @ref LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO (*)
3071	* @arg @ref LL_TIM_TIM5_ITR1_RMP_LPTIM (*)
3072	*
3073	* TIM9: one of the following values
3074	*
3075	* ITR1_RMP can be one of the following values
3076	* @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO (*)
3077	* @arg @ref LL_TIM_TIM9_ITR1_RMP_LPTIM (*)
3078	*
3079	* TIM11: one of the following values
3080	*
3081	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
3082	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 (*)
3083	* @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
3084	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
3085	* @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX (*)
3086	*
3087	* (*) Value not defined in all devices. \n
3088	*
3089	* @retval None
3090	*/
3091	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3092	{
3093	#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
3094	if ((Remap & LL_TIM_LPTIM_REMAP_MASK) == LL_TIM_LPTIM_REMAP_MASK)
3095	{
3096	/* Connect TIMx internal trigger to LPTIM1 output */
3097	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);
3098	MODIFY_REG(LPTIM1->OR,
3099	(LPTIM_OR_TIM1_ITR2_RMP \| LPTIM_OR_TIM5_ITR1_RMP \| LPTIM_OR_TIM9_ITR1_RMP),
3100	Remap & ~(LL_TIM_LPTIM_REMAP_MASK));
3101	}
3102	else
3103	{
3104	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3105	}
3106	#else
3107	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3108	#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
3109	}
3110
3111	/**
3112	* @}
3113	*/
3114
3115	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3116	* @{
3117	*/
3118	/**
3119	* @brief Clear the update interrupt flag (UIF).
3120	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3121	* @param TIMx Timer instance
3122	* @retval None
3123	*/
3124	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3125	{
3126	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3127	}
3128
3129	/**
3130	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3131	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3132	* @param TIMx Timer instance
3133	* @retval State of bit (1 or 0).
3134	*/
3135	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
3136	{
3137	return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3138	}
3139
3140	/**
3141	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3142	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3143	* @param TIMx Timer instance
3144	* @retval None
3145	*/
3146	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3147	{
3148	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3149	}
3150
3151	/**
3152	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3153	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3154	* @param TIMx Timer instance
3155	* @retval State of bit (1 or 0).
3156	*/
3157	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
3158	{
3159	return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3160	}
3161
3162	/**
3163	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3164	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3165	* @param TIMx Timer instance
3166	* @retval None
3167	*/
3168	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3169	{
3170	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3171	}
3172
3173	/**
3174	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3175	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3176	* @param TIMx Timer instance
3177	* @retval State of bit (1 or 0).
3178	*/
3179	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
3180	{
3181	return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3182	}
3183
3184	/**
3185	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3186	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3187	* @param TIMx Timer instance
3188	* @retval None
3189	*/
3190	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3191	{
3192	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3193	}
3194
3195	/**
3196	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3197	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3198	* @param TIMx Timer instance
3199	* @retval State of bit (1 or 0).
3200	*/
3201	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
3202	{
3203	return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3204	}
3205
3206	/**
3207	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3208	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3209	* @param TIMx Timer instance
3210	* @retval None
3211	*/
3212	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3213	{
3214	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3215	}
3216
3217	/**
3218	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3219	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3220	* @param TIMx Timer instance
3221	* @retval State of bit (1 or 0).
3222	*/
3223	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
3224	{
3225	return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
3226	}
3227
3228	/**
3229	* @brief Clear the commutation interrupt flag (COMIF).
3230	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3231	* @param TIMx Timer instance
3232	* @retval None
3233	*/
3234	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3235	{
3236	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3237	}
3238
3239	/**
3240	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3241	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3242	* @param TIMx Timer instance
3243	* @retval State of bit (1 or 0).
3244	*/
3245	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
3246	{
3247	return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
3248	}
3249
3250	/**
3251	* @brief Clear the trigger interrupt flag (TIF).
3252	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3253	* @param TIMx Timer instance
3254	* @retval None
3255	*/
3256	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3257	{
3258	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3259	}
3260
3261	/**
3262	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3263	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3264	* @param TIMx Timer instance
3265	* @retval State of bit (1 or 0).
3266	*/
3267	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
3268	{
3269	return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
3270	}
3271
3272	/**
3273	* @brief Clear the break interrupt flag (BIF).
3274	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3275	* @param TIMx Timer instance
3276	* @retval None
3277	*/
3278	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3279	{
3280	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3281	}
3282
3283	/**
3284	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3285	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3286	* @param TIMx Timer instance
3287	* @retval State of bit (1 or 0).
3288	*/
3289	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
3290	{
3291	return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
3292	}
3293
3294	/**
3295	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3296	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3297	* @param TIMx Timer instance
3298	* @retval None
3299	*/
3300	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3301	{
3302	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3303	}
3304
3305	/**
3306	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
3307	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3308	* @param TIMx Timer instance
3309	* @retval State of bit (1 or 0).
3310	*/
3311	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
3312	{
3313	return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
3314	}
3315
3316	/**
3317	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3318	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3319	* @param TIMx Timer instance
3320	* @retval None
3321	*/
3322	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3323	{
3324	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3325	}
3326
3327	/**
3328	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
3329	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3330	* @param TIMx Timer instance
3331	* @retval State of bit (1 or 0).
3332	*/
3333	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
3334	{
3335	return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
3336	}
3337
3338	/**
3339	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
3340	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
3341	* @param TIMx Timer instance
3342	* @retval None
3343	*/
3344	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
3345	{
3346	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
3347	}
3348
3349	/**
3350	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
3351	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
3352	* @param TIMx Timer instance
3353	* @retval State of bit (1 or 0).
3354	*/
3355	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
3356	{
3357	return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
3358	}
3359
3360	/**
3361	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
3362	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
3363	* @param TIMx Timer instance
3364	* @retval None
3365	*/
3366	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
3367	{
3368	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
3369	}
3370
3371	/**
3372	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
3373	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
3374	* @param TIMx Timer instance
3375	* @retval State of bit (1 or 0).
3376	*/
3377	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
3378	{
3379	return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
3380	}
3381
3382	/**
3383	* @}
3384	*/
3385
3386	/** @defgroup TIM_LL_EF_IT_Management IT-Management
3387	* @{
3388	*/
3389	/**
3390	* @brief Enable update interrupt (UIE).
3391	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
3392	* @param TIMx Timer instance
3393	* @retval None
3394	*/
3395	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
3396	{
3397	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
3398	}
3399
3400	/**
3401	* @brief Disable update interrupt (UIE).
3402	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
3403	* @param TIMx Timer instance
3404	* @retval None
3405	*/
3406	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
3407	{
3408	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
3409	}
3410
3411	/**
3412	* @brief Indicates whether the update interrupt (UIE) is enabled.
3413	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
3414	* @param TIMx Timer instance
3415	* @retval State of bit (1 or 0).
3416	*/
3417	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
3418	{
3419	return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
3420	}
3421
3422	/**
3423	* @brief Enable capture/compare 1 interrupt (CC1IE).
3424	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
3425	* @param TIMx Timer instance
3426	* @retval None
3427	*/
3428	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
3429	{
3430	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3431	}
3432
3433	/**
3434	* @brief Disable capture/compare 1 interrupt (CC1IE).
3435	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
3436	* @param TIMx Timer instance
3437	* @retval None
3438	*/
3439	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
3440	{
3441	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3442	}
3443
3444	/**
3445	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
3446	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
3447	* @param TIMx Timer instance
3448	* @retval State of bit (1 or 0).
3449	*/
3450	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
3451	{
3452	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
3453	}
3454
3455	/**
3456	* @brief Enable capture/compare 2 interrupt (CC2IE).
3457	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
3458	* @param TIMx Timer instance
3459	* @retval None
3460	*/
3461	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
3462	{
3463	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3464	}
3465
3466	/**
3467	* @brief Disable capture/compare 2 interrupt (CC2IE).
3468	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
3469	* @param TIMx Timer instance
3470	* @retval None
3471	*/
3472	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
3473	{
3474	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3475	}
3476
3477	/**
3478	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
3479	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
3480	* @param TIMx Timer instance
3481	* @retval State of bit (1 or 0).
3482	*/
3483	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
3484	{
3485	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
3486	}
3487
3488	/**
3489	* @brief Enable capture/compare 3 interrupt (CC3IE).
3490	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
3491	* @param TIMx Timer instance
3492	* @retval None
3493	*/
3494	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
3495	{
3496	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3497	}
3498
3499	/**
3500	* @brief Disable capture/compare 3 interrupt (CC3IE).
3501	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
3502	* @param TIMx Timer instance
3503	* @retval None
3504	*/
3505	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
3506	{
3507	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3508	}
3509
3510	/**
3511	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
3512	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
3513	* @param TIMx Timer instance
3514	* @retval State of bit (1 or 0).
3515	*/
3516	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
3517	{
3518	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
3519	}
3520
3521	/**
3522	* @brief Enable capture/compare 4 interrupt (CC4IE).
3523	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
3524	* @param TIMx Timer instance
3525	* @retval None
3526	*/
3527	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
3528	{
3529	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3530	}
3531
3532	/**
3533	* @brief Disable capture/compare 4 interrupt (CC4IE).
3534	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
3535	* @param TIMx Timer instance
3536	* @retval None
3537	*/
3538	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
3539	{
3540	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3541	}
3542
3543	/**
3544	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
3545	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
3546	* @param TIMx Timer instance
3547	* @retval State of bit (1 or 0).
3548	*/
3549	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
3550	{
3551	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
3552	}
3553
3554	/**
3555	* @brief Enable commutation interrupt (COMIE).
3556	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
3557	* @param TIMx Timer instance
3558	* @retval None
3559	*/
3560	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
3561	{
3562	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
3563	}
3564
3565	/**
3566	* @brief Disable commutation interrupt (COMIE).
3567	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
3568	* @param TIMx Timer instance
3569	* @retval None
3570	*/
3571	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
3572	{
3573	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
3574	}
3575
3576	/**
3577	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
3578	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
3579	* @param TIMx Timer instance
3580	* @retval State of bit (1 or 0).
3581	*/
3582	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
3583	{
3584	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
3585	}
3586
3587	/**
3588	* @brief Enable trigger interrupt (TIE).
3589	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
3590	* @param TIMx Timer instance
3591	* @retval None
3592	*/
3593	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
3594	{
3595	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
3596	}
3597
3598	/**
3599	* @brief Disable trigger interrupt (TIE).
3600	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
3601	* @param TIMx Timer instance
3602	* @retval None
3603	*/
3604	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
3605	{
3606	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
3607	}
3608
3609	/**
3610	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
3611	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
3612	* @param TIMx Timer instance
3613	* @retval State of bit (1 or 0).
3614	*/
3615	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
3616	{
3617	return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
3618	}
3619
3620	/**
3621	* @brief Enable break interrupt (BIE).
3622	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
3623	* @param TIMx Timer instance
3624	* @retval None
3625	*/
3626	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
3627	{
3628	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
3629	}
3630
3631	/**
3632	* @brief Disable break interrupt (BIE).
3633	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
3634	* @param TIMx Timer instance
3635	* @retval None
3636	*/
3637	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
3638	{
3639	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
3640	}
3641
3642	/**
3643	* @brief Indicates whether the break interrupt (BIE) is enabled.
3644	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
3645	* @param TIMx Timer instance
3646	* @retval State of bit (1 or 0).
3647	*/
3648	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
3649	{
3650	return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
3651	}
3652
3653	/**
3654	* @}
3655	*/
3656
3657	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
3658	* @{
3659	*/
3660	/**
3661	* @brief Enable update DMA request (UDE).
3662	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
3663	* @param TIMx Timer instance
3664	* @retval None
3665	*/
3666	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3667	{
3668	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
3669	}
3670
3671	/**
3672	* @brief Disable update DMA request (UDE).
3673	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
3674	* @param TIMx Timer instance
3675	* @retval None
3676	*/
3677	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3678	{
3679	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
3680	}
3681
3682	/**
3683	* @brief Indicates whether the update DMA request (UDE) is enabled.
3684	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
3685	* @param TIMx Timer instance
3686	* @retval State of bit (1 or 0).
3687	*/
3688	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
3689	{
3690	return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
3691	}
3692
3693	/**
3694	* @brief Enable capture/compare 1 DMA request (CC1DE).
3695	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
3696	* @param TIMx Timer instance
3697	* @retval None
3698	*/
3699	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
3700	{
3701	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3702	}
3703
3704	/**
3705	* @brief Disable capture/compare 1 DMA request (CC1DE).
3706	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
3707	* @param TIMx Timer instance
3708	* @retval None
3709	*/
3710	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
3711	{
3712	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3713	}
3714
3715	/**
3716	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
3717	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
3718	* @param TIMx Timer instance
3719	* @retval State of bit (1 or 0).
3720	*/
3721	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
3722	{
3723	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
3724	}
3725
3726	/**
3727	* @brief Enable capture/compare 2 DMA request (CC2DE).
3728	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
3729	* @param TIMx Timer instance
3730	* @retval None
3731	*/
3732	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
3733	{
3734	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3735	}
3736
3737	/**
3738	* @brief Disable capture/compare 2 DMA request (CC2DE).
3739	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
3740	* @param TIMx Timer instance
3741	* @retval None
3742	*/
3743	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
3744	{
3745	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3746	}
3747
3748	/**
3749	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
3750	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
3751	* @param TIMx Timer instance
3752	* @retval State of bit (1 or 0).
3753	*/
3754	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
3755	{
3756	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
3757	}
3758
3759	/**
3760	* @brief Enable capture/compare 3 DMA request (CC3DE).
3761	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
3762	* @param TIMx Timer instance
3763	* @retval None
3764	*/
3765	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
3766	{
3767	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3768	}
3769
3770	/**
3771	* @brief Disable capture/compare 3 DMA request (CC3DE).
3772	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
3773	* @param TIMx Timer instance
3774	* @retval None
3775	*/
3776	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
3777	{
3778	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3779	}
3780
3781	/**
3782	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3783	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
3784	* @param TIMx Timer instance
3785	* @retval State of bit (1 or 0).
3786	*/
3787	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
3788	{
3789	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
3790	}
3791
3792	/**
3793	* @brief Enable capture/compare 4 DMA request (CC4DE).
3794	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
3795	* @param TIMx Timer instance
3796	* @retval None
3797	*/
3798	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
3799	{
3800	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3801	}
3802
3803	/**
3804	* @brief Disable capture/compare 4 DMA request (CC4DE).
3805	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
3806	* @param TIMx Timer instance
3807	* @retval None
3808	*/
3809	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
3810	{
3811	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3812	}
3813
3814	/**
3815	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3816	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
3817	* @param TIMx Timer instance
3818	* @retval State of bit (1 or 0).
3819	*/
3820	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
3821	{
3822	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
3823	}
3824
3825	/**
3826	* @brief Enable commutation DMA request (COMDE).
3827	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
3828	* @param TIMx Timer instance
3829	* @retval None
3830	*/
3831	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
3832	{
3833	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
3834	}
3835
3836	/**
3837	* @brief Disable commutation DMA request (COMDE).
3838	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
3839	* @param TIMx Timer instance
3840	* @retval None
3841	*/
3842	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
3843	{
3844	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
3845	}
3846
3847	/**
3848	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
3849	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
3850	* @param TIMx Timer instance
3851	* @retval State of bit (1 or 0).
3852	*/
3853	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
3854	{
3855	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
3856	}
3857
3858	/**
3859	* @brief Enable trigger interrupt (TDE).
3860	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
3861	* @param TIMx Timer instance
3862	* @retval None
3863	*/
3864	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
3865	{
3866	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
3867	}
3868
3869	/**
3870	* @brief Disable trigger interrupt (TDE).
3871	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
3872	* @param TIMx Timer instance
3873	* @retval None
3874	*/
3875	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
3876	{
3877	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
3878	}
3879
3880	/**
3881	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
3882	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
3883	* @param TIMx Timer instance
3884	* @retval State of bit (1 or 0).
3885	*/
3886	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
3887	{
3888	return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
3889	}
3890
3891	/**
3892	* @}
3893	*/
3894
3895	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
3896	* @{
3897	*/
3898	/**
3899	* @brief Generate an update event.
3900	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
3901	* @param TIMx Timer instance
3902	* @retval None
3903	*/
3904	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
3905	{
3906	SET_BIT(TIMx->EGR, TIM_EGR_UG);
3907	}
3908
3909	/**
3910	* @brief Generate Capture/Compare 1 event.
3911	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
3912	* @param TIMx Timer instance
3913	* @retval None
3914	*/
3915	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
3916	{
3917	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
3918	}
3919
3920	/**
3921	* @brief Generate Capture/Compare 2 event.
3922	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
3923	* @param TIMx Timer instance
3924	* @retval None
3925	*/
3926	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
3927	{
3928	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
3929	}
3930
3931	/**
3932	* @brief Generate Capture/Compare 3 event.
3933	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
3934	* @param TIMx Timer instance
3935	* @retval None
3936	*/
3937	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
3938	{
3939	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
3940	}
3941
3942	/**
3943	* @brief Generate Capture/Compare 4 event.
3944	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
3945	* @param TIMx Timer instance
3946	* @retval None
3947	*/
3948	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
3949	{
3950	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
3951	}
3952
3953	/**
3954	* @brief Generate commutation event.
3955	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
3956	* @param TIMx Timer instance
3957	* @retval None
3958	*/
3959	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
3960	{
3961	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
3962	}
3963
3964	/**
3965	* @brief Generate trigger event.
3966	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
3967	* @param TIMx Timer instance
3968	* @retval None
3969	*/
3970	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
3971	{
3972	SET_BIT(TIMx->EGR, TIM_EGR_TG);
3973	}
3974
3975	/**
3976	* @brief Generate break event.
3977	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
3978	* @param TIMx Timer instance
3979	* @retval None
3980	*/
3981	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
3982	{
3983	SET_BIT(TIMx->EGR, TIM_EGR_BG);
3984	}
3985
3986	/**
3987	* @}
3988	*/
3989
3990	#if defined(USE_FULL_LL_DRIVER)
3991	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
3992	* @{
3993	*/
3994
3995	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
3996	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
3997	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
3998	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3999	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
4000	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4001	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
4002	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4003	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
4004	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4005	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
4006	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4007	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
4008	/**
4009	* @}
4010	*/
4011	#endif /* USE_FULL_LL_DRIVER */
4012
4013	/**
4014	* @}
4015	*/
4016
4017	/**
4018	* @}
4019	*/
4020
4021	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 */
4022
4023	/**
4024	* @}
4025	*/
4026
4027	#ifdef __cplusplus
4028	}
4029	#endif
4030
4031	#endif /* __STM32F4xx_LL_TIM_H */
4032	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h

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