| 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_ll_wwdg.h
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| 4 | * @author MCD Application Team
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| 5 | * @brief Header file of WWDG LL module.
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| 6 | ******************************************************************************
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| 7 | * @attention
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| 8 | *
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics.
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| 10 | * All rights reserved.</center></h2>
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| 11 | *
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| 12 | * This software component is licensed by ST under BSD 3-Clause license,
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| 13 | * the "License"; You may not use this file except in compliance with the
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| 14 | * License. You may obtain a copy of the License at:
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| 15 | * opensource.org/licenses/BSD-3-Clause
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| 16 | *
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| 17 | ******************************************************************************
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| 18 | */
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| 19 |
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| 20 | /* Define to prevent recursive inclusion -------------------------------------*/
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| 21 | #ifndef STM32F4xx_LL_WWDG_H
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| 22 | #define STM32F4xx_LL_WWDG_H
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| 23 |
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| 24 | #ifdef __cplusplus
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| 25 | extern "C" {
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| 26 | #endif
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| 27 |
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| 28 | /* Includes ------------------------------------------------------------------*/
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| 29 | #include "stm32f4xx.h"
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| 30 |
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| 31 | /** @addtogroup STM32F4xx_LL_Driver
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| 32 | * @{
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| 33 | */
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| 34 |
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| 35 | #if defined (WWDG)
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| 36 |
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| 37 | /** @defgroup WWDG_LL WWDG
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| 38 | * @{
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| 39 | */
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| 40 |
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| 41 | /* Private types -------------------------------------------------------------*/
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| 42 | /* Private variables ---------------------------------------------------------*/
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| 43 | /* Private constants ---------------------------------------------------------*/
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| 44 | /* Private macros ------------------------------------------------------------*/
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| 45 | /* Exported types ------------------------------------------------------------*/
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| 46 | /* Exported constants --------------------------------------------------------*/
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| 47 | /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
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| 48 | * @{
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| 49 | */
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| 50 |
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| 51 | /** @defgroup WWDG_LL_EC_IT IT Defines
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| 52 | * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
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| 53 | * @{
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| 54 | */
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| 55 | #define LL_WWDG_CFR_EWI WWDG_CFR_EWI
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| 56 | /**
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| 57 | * @}
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| 58 | */
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| 59 |
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| 60 | /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
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| 61 | * @{
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| 62 | */
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| 63 | #define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
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| 64 | #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
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| 65 | #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
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| 66 | #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
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| 67 | /**
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| 68 | * @}
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| 69 | */
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| 70 |
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| 71 | /**
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| 72 | * @}
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| 73 | */
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| 74 |
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| 75 | /* Exported macro ------------------------------------------------------------*/
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| 76 | /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
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| 77 | * @{
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| 78 | */
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| 79 | /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
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| 80 | * @{
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| 81 | */
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| 82 | /**
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| 83 | * @brief Write a value in WWDG register
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| 84 | * @param __INSTANCE__ WWDG Instance
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| 85 | * @param __REG__ Register to be written
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| 86 | * @param __VALUE__ Value to be written in the register
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| 87 | * @retval None
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| 88 | */
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| 89 | #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
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| 90 |
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| 91 | /**
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| 92 | * @brief Read a value in WWDG register
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| 93 | * @param __INSTANCE__ WWDG Instance
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| 94 | * @param __REG__ Register to be read
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| 95 | * @retval Register value
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| 96 | */
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| 97 | #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
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| 98 | /**
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| 99 | * @}
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| 100 | */
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| 101 |
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| 102 | /**
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| 103 | * @}
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| 104 | */
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| 105 |
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| 106 | /* Exported functions --------------------------------------------------------*/
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| 107 | /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
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| 108 | * @{
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| 109 | */
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| 110 |
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| 111 | /** @defgroup WWDG_LL_EF_Configuration Configuration
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| 112 | * @{
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| 113 | */
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| 114 | /**
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| 115 | * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
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| 116 | * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
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| 117 | * then it cannot be disabled again except by a reset.
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| 118 | * This bit is set by software and only cleared by hardware after a reset.
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| 119 | * When WDGA = 1, the watchdog can generate a reset.
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| 120 | * @rmtoll CR WDGA LL_WWDG_Enable
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| 121 | * @param WWDGx WWDG Instance
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| 122 | * @retval None
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| 123 | */
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| 124 | __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
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| 125 | {
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| 126 | SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
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| 127 | }
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| 128 |
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| 129 | /**
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| 130 | * @brief Checks if Window Watchdog is enabled
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| 131 | * @rmtoll CR WDGA LL_WWDG_IsEnabled
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| 132 | * @param WWDGx WWDG Instance
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| 133 | * @retval State of bit (1 or 0).
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| 134 | */
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| 135 | __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
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| 136 | {
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| 137 | return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
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| 138 | }
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| 139 |
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| 140 | /**
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| 141 | * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
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| 142 | * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
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| 143 | * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
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| 144 | * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
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| 145 | * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
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| 146 | * @rmtoll CR T LL_WWDG_SetCounter
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| 147 | * @param WWDGx WWDG Instance
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| 148 | * @param Counter 0..0x7F (7 bit counter value)
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| 149 | * @retval None
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| 150 | */
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| 151 | __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
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| 152 | {
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| 153 | MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
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| 154 | }
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| 155 |
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| 156 | /**
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| 157 | * @brief Return current Watchdog Counter Value (7 bits counter value)
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| 158 | * @rmtoll CR T LL_WWDG_GetCounter
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| 159 | * @param WWDGx WWDG Instance
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| 160 | * @retval 7 bit Watchdog Counter value
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| 161 | */
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| 162 | __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
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| 163 | {
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| 164 | return (READ_BIT(WWDGx->CR, WWDG_CR_T));
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| 165 | }
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| 166 |
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| 167 | /**
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| 168 | * @brief Set the time base of the prescaler (WDGTB).
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| 169 | * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
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| 170 | * is decremented every (4096 x 2expWDGTB) PCLK cycles
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| 171 | * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
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| 172 | * @param WWDGx WWDG Instance
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| 173 | * @param Prescaler This parameter can be one of the following values:
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| 174 | * @arg @ref LL_WWDG_PRESCALER_1
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| 175 | * @arg @ref LL_WWDG_PRESCALER_2
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| 176 | * @arg @ref LL_WWDG_PRESCALER_4
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| 177 | * @arg @ref LL_WWDG_PRESCALER_8
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| 178 | * @retval None
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| 179 | */
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| 180 | __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
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| 181 | {
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| 182 | MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
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| 183 | }
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| 184 |
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| 185 | /**
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| 186 | * @brief Return current Watchdog Prescaler Value
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| 187 | * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
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| 188 | * @param WWDGx WWDG Instance
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| 189 | * @retval Returned value can be one of the following values:
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| 190 | * @arg @ref LL_WWDG_PRESCALER_1
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| 191 | * @arg @ref LL_WWDG_PRESCALER_2
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| 192 | * @arg @ref LL_WWDG_PRESCALER_4
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| 193 | * @arg @ref LL_WWDG_PRESCALER_8
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| 194 | */
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| 195 | __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
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| 196 | {
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| 197 | return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
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| 198 | }
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| 199 |
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| 200 | /**
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| 201 | * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
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| 202 | * @note This window value defines when write in the WWDG_CR register
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| 203 | * to program Watchdog counter is allowed.
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| 204 | * Watchdog counter value update must occur only when the counter value
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| 205 | * is lower than the Watchdog window register value.
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| 206 | * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
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| 207 | * (in the control register) is refreshed before the downcounter has reached
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| 208 | * the watchdog window register value.
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| 209 | * Physically is possible to set the Window lower then 0x40 but it is not recommended.
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| 210 | * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
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| 211 | * @rmtoll CFR W LL_WWDG_SetWindow
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| 212 | * @param WWDGx WWDG Instance
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| 213 | * @param Window 0x00..0x7F (7 bit Window value)
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| 214 | * @retval None
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| 215 | */
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| 216 | __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
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| 217 | {
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| 218 | MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
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| 219 | }
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| 220 |
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| 221 | /**
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| 222 | * @brief Return current Watchdog Window Value (7 bits value)
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| 223 | * @rmtoll CFR W LL_WWDG_GetWindow
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| 224 | * @param WWDGx WWDG Instance
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| 225 | * @retval 7 bit Watchdog Window value
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| 226 | */
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| 227 | __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
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| 228 | {
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| 229 | return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
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| 230 | }
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| 231 |
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| 232 | /**
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| 233 | * @}
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| 234 | */
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| 235 |
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| 236 | /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
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| 237 | * @{
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| 238 | */
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| 239 | /**
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| 240 | * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
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| 241 | * @note This bit is set by hardware when the counter has reached the value 0x40.
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| 242 | * It must be cleared by software by writing 0.
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| 243 | * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
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| 244 | * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
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| 245 | * @param WWDGx WWDG Instance
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| 246 | * @retval State of bit (1 or 0).
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| 247 | */
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| 248 | __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
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| 249 | {
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| 250 | return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
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| 251 | }
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| 252 |
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| 253 | /**
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| 254 | * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
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| 255 | * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
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| 256 | * @param WWDGx WWDG Instance
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| 257 | * @retval None
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| 258 | */
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| 259 | __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
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| 260 | {
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| 261 | WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
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| 262 | }
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| 263 |
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| 264 | /**
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| 265 | * @}
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| 266 | */
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| 267 |
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| 268 | /** @defgroup WWDG_LL_EF_IT_Management IT_Management
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| 269 | * @{
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| 270 | */
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| 271 | /**
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| 272 | * @brief Enable the Early Wakeup Interrupt.
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| 273 | * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
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| 274 | * This interrupt is only cleared by hardware after a reset
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| 275 | * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
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| 276 | * @param WWDGx WWDG Instance
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| 277 | * @retval None
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| 278 | */
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| 279 | __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
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| 280 | {
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| 281 | SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
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| 282 | }
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| 283 |
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| 284 | /**
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| 285 | * @brief Check if Early Wakeup Interrupt is enabled
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| 286 | * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
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| 287 | * @param WWDGx WWDG Instance
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| 288 | * @retval State of bit (1 or 0).
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| 289 | */
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| 290 | __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
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| 291 | {
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| 292 | return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
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| 293 | }
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| 294 |
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| 295 | /**
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| 296 | * @}
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| 297 | */
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| 298 |
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| 299 | /**
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| 300 | * @}
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| 301 | */
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| 302 |
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| 303 | /**
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| 304 | * @}
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| 305 | */
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| 306 |
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| 307 | #endif /* WWDG */
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| 308 |
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| 309 | /**
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| 310 | * @}
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| 311 | */
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| 312 |
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| 313 | #ifdef __cplusplus
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| 314 | }
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| 315 | #endif
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| 316 |
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| 317 | #endif /* STM32F4xx_LL_WWDG_H */
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| 318 |
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| 319 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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