source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c

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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC) peripheral:
7 * + Initialization and de-initialization functions
8 * + IO operation functions
9 * + State and errors functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### ADC Peripheral features #####
14 ==============================================================================
15 [..]
16 (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
17 (#) Interrupt generation at the end of conversion, end of injected conversion,
18 and in case of analog watchdog or overrun events
19 (#) Single and continuous conversion modes.
20 (#) Scan mode for automatic conversion of channel 0 to channel x.
21 (#) Data alignment with in-built data coherency.
22 (#) Channel-wise programmable sampling time.
23 (#) External trigger option with configurable polarity for both regular and
24 injected conversion.
25 (#) Dual/Triple mode (on devices with 2 ADCs or more).
26 (#) Configurable DMA data storage in Dual/Triple ADC mode.
27 (#) Configurable delay between conversions in Dual/Triple interleaved mode.
28 (#) ADC conversion type (refer to the datasheets).
29 (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
30 slower speed.
31 (#) ADC input range: VREF(minus) = VIN = VREF(plus).
32 (#) DMA request generation during regular channel conversion.
33
34
35 ##### How to use this driver #####
36 ==============================================================================
37 [..]
38 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
39 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
40 (##) ADC pins configuration
41 (+++) Enable the clock for the ADC GPIOs using the following function:
42 __HAL_RCC_GPIOx_CLK_ENABLE()
43 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
44 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
45 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
46 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
47 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
48 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
49 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
50 (+++) Configure and enable two DMA streams stream for managing data
51 transfer from peripheral to memory (output stream)
52 (+++) Associate the initialized DMA handle to the CRYP DMA handle
53 using __HAL_LINKDMA()
54 (+++) Configure the priority and enable the NVIC for the transfer complete
55 interrupt on the two DMA Streams. The output stream should have higher
56 priority than the input stream.
57
58 *** Configuration of ADC, groups regular/injected, channels parameters ***
59 ==============================================================================
60 [..]
61 (#) Configure the ADC parameters (resolution, data alignment, ...)
62 and regular group parameters (conversion trigger, sequencer, ...)
63 using function HAL_ADC_Init().
64
65 (#) Configure the channels for regular group parameters (channel number,
66 channel rank into sequencer, ..., into regular group)
67 using function HAL_ADC_ConfigChannel().
68
69 (#) Optionally, configure the injected group parameters (conversion trigger,
70 sequencer, ..., of injected group)
71 and the channels for injected group parameters (channel number,
72 channel rank into sequencer, ..., into injected group)
73 using function HAL_ADCEx_InjectedConfigChannel().
74
75 (#) Optionally, configure the analog watchdog parameters (channels
76 monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
77
78 (#) Optionally, for devices with several ADC instances: configure the
79 multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
80
81 *** Execution of ADC conversions ***
82 ==============================================================================
83 [..]
84 (#) ADC driver can be used among three modes: polling, interruption,
85 transfer by DMA.
86
87 *** Polling mode IO operation ***
88 =================================
89 [..]
90 (+) Start the ADC peripheral using HAL_ADC_Start()
91 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
92 user can specify the value of timeout according to his end application
93 (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
94 (+) Stop the ADC peripheral using HAL_ADC_Stop()
95
96 *** Interrupt mode IO operation ***
97 ===================================
98 [..]
99 (+) Start the ADC peripheral using HAL_ADC_Start_IT()
100 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
101 (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
102 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
103 (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
104 add his own code by customization of function pointer HAL_ADC_ErrorCallback
105 (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
106
107 *** DMA mode IO operation ***
108 ==============================
109 [..]
110 (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
111 of data to be transferred at each end of conversion
112 (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
113 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
114 (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
115 add his own code by customization of function pointer HAL_ADC_ErrorCallback
116 (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
117
118 *** ADC HAL driver macros list ***
119 =============================================
120 [..]
121 Below the list of most used macros in ADC HAL driver.
122
123 (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
124 (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
125 (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
126 (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
127 (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
128 (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
129 (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
130 (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
131
132 [..]
133 (@) You can refer to the ADC HAL driver header file for more useful macros
134
135 *** Deinitialization of ADC ***
136 ==============================================================================
137 [..]
138 (#) Disable the ADC interface
139 (++) ADC clock can be hard reset and disabled at RCC top level.
140 (++) Hard reset of ADC peripherals
141 using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
142 (++) ADC clock disable using the equivalent macro/functions as configuration step.
143 (+++) Example:
144 Into HAL_ADC_MspDeInit() (recommended code location) or with
145 other device clock parameters configuration:
146 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
147 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
148 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
149 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
150
151 (#) ADC pins configuration
152 (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
153
154 (#) Optionally, in case of usage of ADC with interruptions:
155 (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
156
157 (#) Optionally, in case of usage of DMA:
158 (++) Deinitialize the DMA using function HAL_DMA_DeInit().
159 (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
160 *** Callback registration ***
161 ==============================================================================
162 [..]
163
164 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
165 allows the user to configure dynamically the driver callbacks.
166 Use Functions @ref HAL_ADC_RegisterCallback()
167 to register an interrupt callback.
168 [..]
169
170 Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
171 (+) ConvCpltCallback : ADC conversion complete callback
172 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
173 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
174 (+) ErrorCallback : ADC error callback
175 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
176 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
177 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
178 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
179 (+) EndOfSamplingCallback : ADC end of sampling callback
180 (+) MspInitCallback : ADC Msp Init callback
181 (+) MspDeInitCallback : ADC Msp DeInit callback
182 This function takes as parameters the HAL peripheral handle, the Callback ID
183 and a pointer to the user callback function.
184 [..]
185
186 Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
187 weak function.
188 [..]
189
190 @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
191 and the Callback ID.
192 This function allows to reset following callbacks:
193 (+) ConvCpltCallback : ADC conversion complete callback
194 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
195 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
196 (+) ErrorCallback : ADC error callback
197 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
198 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
199 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
200 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
201 (+) EndOfSamplingCallback : ADC end of sampling callback
202 (+) MspInitCallback : ADC Msp Init callback
203 (+) MspDeInitCallback : ADC Msp DeInit callback
204 [..]
205
206 By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
207 all callbacks are set to the corresponding weak functions:
208 examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
209 Exception done for MspInit and MspDeInit functions that are
210 reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
211 these callbacks are null (not registered beforehand).
212 [..]
213
214 If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
215 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
216 [..]
217
218 Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
219 Exception done MspInit/MspDeInit functions that can be registered/unregistered
220 in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
221 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
222 [..]
223
224 Then, the user first registers the MspInit/MspDeInit user callbacks
225 using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
226 or @ref HAL_ADC_Init() function.
227 [..]
228
229 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
230 not defined, the callback registration feature is not available and all callbacks
231 are set to the corresponding weak functions.
232
233 @endverbatim
234 ******************************************************************************
235 * @attention
236 *
237 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
238 * All rights reserved.</center></h2>
239 *
240 * This software component is licensed by ST under BSD 3-Clause license,
241 * the "License"; You may not use this file except in compliance with the
242 * License. You may obtain a copy of the License at:
243 * opensource.org/licenses/BSD-3-Clause
244 *
245 ******************************************************************************
246 */
247
248/* Includes ------------------------------------------------------------------*/
249#include "stm32f4xx_hal.h"
250
251/** @addtogroup STM32F4xx_HAL_Driver
252 * @{
253 */
254
255/** @defgroup ADC ADC
256 * @brief ADC driver modules
257 * @{
258 */
259
260#ifdef HAL_ADC_MODULE_ENABLED
261
262/* Private typedef -----------------------------------------------------------*/
263/* Private define ------------------------------------------------------------*/
264/* Private macro -------------------------------------------------------------*/
265/* Private variables ---------------------------------------------------------*/
266/** @addtogroup ADC_Private_Functions
267 * @{
268 */
269/* Private function prototypes -----------------------------------------------*/
270static void ADC_Init(ADC_HandleTypeDef* hadc);
271static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
272static void ADC_DMAError(DMA_HandleTypeDef *hdma);
273static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
274/**
275 * @}
276 */
277/* Exported functions --------------------------------------------------------*/
278/** @defgroup ADC_Exported_Functions ADC Exported Functions
279 * @{
280 */
281
282/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
283 * @brief Initialization and Configuration functions
284 *
285@verbatim
286 ===============================================================================
287 ##### Initialization and de-initialization functions #####
288 ===============================================================================
289 [..] This section provides functions allowing to:
290 (+) Initialize and configure the ADC.
291 (+) De-initialize the ADC.
292
293@endverbatim
294 * @{
295 */
296
297/**
298 * @brief Initializes the ADCx peripheral according to the specified parameters
299 * in the ADC_InitStruct and initializes the ADC MSP.
300 *
301 * @note This function is used to configure the global features of the ADC (
302 * ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
303 * the rest of the configuration parameters are specific to the regular
304 * channels group (scan mode activation, continuous mode activation,
305 * External trigger source and edge, DMA continuous request after the
306 * last transfer and End of conversion selection).
307 *
308 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
309 * the configuration information for the specified ADC.
310 * @retval HAL status
311 */
312HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
313{
314 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
315
316 /* Check ADC handle */
317 if(hadc == NULL)
318 {
319 return HAL_ERROR;
320 }
321
322 /* Check the parameters */
323 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
324 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
325 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
326 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
327 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
328 assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
329 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
330 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
331 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
332 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
333 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
334
335 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
336 {
337 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
338 }
339
340 if(hadc->State == HAL_ADC_STATE_RESET)
341 {
342#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
343 /* Init the ADC Callback settings */
344 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
345 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
346 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
347 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
348 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
349 if (hadc->MspInitCallback == NULL)
350 {
351 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
352 }
353
354 /* Init the low level hardware */
355 hadc->MspInitCallback(hadc);
356#else
357 /* Init the low level hardware */
358 HAL_ADC_MspInit(hadc);
359#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
360
361 /* Initialize ADC error code */
362 ADC_CLEAR_ERRORCODE(hadc);
363
364 /* Allocate lock resource and initialize it */
365 hadc->Lock = HAL_UNLOCKED;
366 }
367
368 /* Configuration of ADC parameters if previous preliminary actions are */
369 /* correctly completed. */
370 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
371 {
372 /* Set ADC state */
373 ADC_STATE_CLR_SET(hadc->State,
374 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
375 HAL_ADC_STATE_BUSY_INTERNAL);
376
377 /* Set ADC parameters */
378 ADC_Init(hadc);
379
380 /* Set ADC error code to none */
381 ADC_CLEAR_ERRORCODE(hadc);
382
383 /* Set the ADC state */
384 ADC_STATE_CLR_SET(hadc->State,
385 HAL_ADC_STATE_BUSY_INTERNAL,
386 HAL_ADC_STATE_READY);
387 }
388 else
389 {
390 tmp_hal_status = HAL_ERROR;
391 }
392
393 /* Release Lock */
394 __HAL_UNLOCK(hadc);
395
396 /* Return function status */
397 return tmp_hal_status;
398}
399
400/**
401 * @brief Deinitializes the ADCx peripheral registers to their default reset values.
402 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
403 * the configuration information for the specified ADC.
404 * @retval HAL status
405 */
406HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
407{
408 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
409
410 /* Check ADC handle */
411 if(hadc == NULL)
412 {
413 return HAL_ERROR;
414 }
415
416 /* Check the parameters */
417 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
418
419 /* Set ADC state */
420 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
421
422 /* Stop potential conversion on going, on regular and injected groups */
423 /* Disable ADC peripheral */
424 __HAL_ADC_DISABLE(hadc);
425
426 /* Configuration of ADC parameters if previous preliminary actions are */
427 /* correctly completed. */
428 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
429 {
430#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
431 if (hadc->MspDeInitCallback == NULL)
432 {
433 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
434 }
435
436 /* DeInit the low level hardware: RCC clock, NVIC */
437 hadc->MspDeInitCallback(hadc);
438#else
439 /* DeInit the low level hardware: RCC clock, NVIC */
440 HAL_ADC_MspDeInit(hadc);
441#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
442
443 /* Set ADC error code to none */
444 ADC_CLEAR_ERRORCODE(hadc);
445
446 /* Set ADC state */
447 hadc->State = HAL_ADC_STATE_RESET;
448 }
449
450 /* Process unlocked */
451 __HAL_UNLOCK(hadc);
452
453 /* Return function status */
454 return tmp_hal_status;
455}
456
457#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
458/**
459 * @brief Register a User ADC Callback
460 * To be used instead of the weak predefined callback
461 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
462 * the configuration information for the specified ADC.
463 * @param CallbackID ID of the callback to be registered
464 * This parameter can be one of the following values:
465 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
466 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
467 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
468 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
469 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
470 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
471 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
472 * @param pCallback pointer to the Callback function
473 * @retval HAL status
474 */
475HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
476{
477 HAL_StatusTypeDef status = HAL_OK;
478
479 if (pCallback == NULL)
480 {
481 /* Update the error code */
482 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
483
484 return HAL_ERROR;
485 }
486
487 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
488 {
489 switch (CallbackID)
490 {
491 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
492 hadc->ConvCpltCallback = pCallback;
493 break;
494
495 case HAL_ADC_CONVERSION_HALF_CB_ID :
496 hadc->ConvHalfCpltCallback = pCallback;
497 break;
498
499 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
500 hadc->LevelOutOfWindowCallback = pCallback;
501 break;
502
503 case HAL_ADC_ERROR_CB_ID :
504 hadc->ErrorCallback = pCallback;
505 break;
506
507 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
508 hadc->InjectedConvCpltCallback = pCallback;
509 break;
510
511 case HAL_ADC_MSPINIT_CB_ID :
512 hadc->MspInitCallback = pCallback;
513 break;
514
515 case HAL_ADC_MSPDEINIT_CB_ID :
516 hadc->MspDeInitCallback = pCallback;
517 break;
518
519 default :
520 /* Update the error code */
521 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
522
523 /* Return error status */
524 status = HAL_ERROR;
525 break;
526 }
527 }
528 else if (HAL_ADC_STATE_RESET == hadc->State)
529 {
530 switch (CallbackID)
531 {
532 case HAL_ADC_MSPINIT_CB_ID :
533 hadc->MspInitCallback = pCallback;
534 break;
535
536 case HAL_ADC_MSPDEINIT_CB_ID :
537 hadc->MspDeInitCallback = pCallback;
538 break;
539
540 default :
541 /* Update the error code */
542 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
543
544 /* Return error status */
545 status = HAL_ERROR;
546 break;
547 }
548 }
549 else
550 {
551 /* Update the error code */
552 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
553
554 /* Return error status */
555 status = HAL_ERROR;
556 }
557
558 return status;
559}
560
561/**
562 * @brief Unregister a ADC Callback
563 * ADC callback is redirected to the weak predefined callback
564 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
565 * the configuration information for the specified ADC.
566 * @param CallbackID ID of the callback to be unregistered
567 * This parameter can be one of the following values:
568 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
569 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
570 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
571 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
572 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
573 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
574 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
575 * @retval HAL status
576 */
577HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
578{
579 HAL_StatusTypeDef status = HAL_OK;
580
581 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
582 {
583 switch (CallbackID)
584 {
585 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
586 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
587 break;
588
589 case HAL_ADC_CONVERSION_HALF_CB_ID :
590 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
591 break;
592
593 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
594 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
595 break;
596
597 case HAL_ADC_ERROR_CB_ID :
598 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
599 break;
600
601 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
602 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
603 break;
604
605 case HAL_ADC_MSPINIT_CB_ID :
606 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
607 break;
608
609 case HAL_ADC_MSPDEINIT_CB_ID :
610 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
611 break;
612
613 default :
614 /* Update the error code */
615 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
616
617 /* Return error status */
618 status = HAL_ERROR;
619 break;
620 }
621 }
622 else if (HAL_ADC_STATE_RESET == hadc->State)
623 {
624 switch (CallbackID)
625 {
626 case HAL_ADC_MSPINIT_CB_ID :
627 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
628 break;
629
630 case HAL_ADC_MSPDEINIT_CB_ID :
631 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
632 break;
633
634 default :
635 /* Update the error code */
636 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
637
638 /* Return error status */
639 status = HAL_ERROR;
640 break;
641 }
642 }
643 else
644 {
645 /* Update the error code */
646 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
647
648 /* Return error status */
649 status = HAL_ERROR;
650 }
651
652 return status;
653}
654
655#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
656
657/**
658 * @brief Initializes the ADC MSP.
659 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
660 * the configuration information for the specified ADC.
661 * @retval None
662 */
663__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
664{
665 /* Prevent unused argument(s) compilation warning */
666 UNUSED(hadc);
667 /* NOTE : This function Should not be modified, when the callback is needed,
668 the HAL_ADC_MspInit could be implemented in the user file
669 */
670}
671
672/**
673 * @brief DeInitializes the ADC MSP.
674 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
675 * the configuration information for the specified ADC.
676 * @retval None
677 */
678__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
679{
680 /* Prevent unused argument(s) compilation warning */
681 UNUSED(hadc);
682 /* NOTE : This function Should not be modified, when the callback is needed,
683 the HAL_ADC_MspDeInit could be implemented in the user file
684 */
685}
686
687/**
688 * @}
689 */
690
691/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
692 * @brief IO operation functions
693 *
694@verbatim
695 ===============================================================================
696 ##### IO operation functions #####
697 ===============================================================================
698 [..] This section provides functions allowing to:
699 (+) Start conversion of regular channel.
700 (+) Stop conversion of regular channel.
701 (+) Start conversion of regular channel and enable interrupt.
702 (+) Stop conversion of regular channel and disable interrupt.
703 (+) Start conversion of regular channel and enable DMA transfer.
704 (+) Stop conversion of regular channel and disable DMA transfer.
705 (+) Handle ADC interrupt request.
706
707@endverbatim
708 * @{
709 */
710
711/**
712 * @brief Enables ADC and starts conversion of the regular channels.
713 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
714 * the configuration information for the specified ADC.
715 * @retval HAL status
716 */
717HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
718{
719 __IO uint32_t counter = 0U;
720 ADC_Common_TypeDef *tmpADC_Common;
721
722 /* Check the parameters */
723 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
724 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
725
726 /* Process locked */
727 __HAL_LOCK(hadc);
728
729 /* Enable the ADC peripheral */
730 /* Check if ADC peripheral is disabled in order to enable it and wait during
731 Tstab time the ADC's stabilization */
732 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
733 {
734 /* Enable the Peripheral */
735 __HAL_ADC_ENABLE(hadc);
736
737 /* Delay for ADC stabilization time */
738 /* Compute number of CPU cycles to wait for */
739 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
740 while(counter != 0U)
741 {
742 counter--;
743 }
744 }
745
746 /* Start conversion if ADC is effectively enabled */
747 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
748 {
749 /* Set ADC state */
750 /* - Clear state bitfield related to regular group conversion results */
751 /* - Set state bitfield related to regular group operation */
752 ADC_STATE_CLR_SET(hadc->State,
753 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
754 HAL_ADC_STATE_REG_BUSY);
755
756 /* If conversions on group regular are also triggering group injected, */
757 /* update ADC state. */
758 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
759 {
760 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
761 }
762
763 /* State machine update: Check if an injected conversion is ongoing */
764 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
765 {
766 /* Reset ADC error code fields related to conversions on group regular */
767 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
768 }
769 else
770 {
771 /* Reset ADC all error code fields */
772 ADC_CLEAR_ERRORCODE(hadc);
773 }
774
775 /* Process unlocked */
776 /* Unlock before starting ADC conversions: in case of potential */
777 /* interruption, to let the process to ADC IRQ Handler. */
778 __HAL_UNLOCK(hadc);
779
780 /* Pointer to the common control register to which is belonging hadc */
781 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
782 /* control register) */
783 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
784
785 /* Clear regular group conversion flag and overrun flag */
786 /* (To ensure of no unknown state from potential previous ADC operations) */
787 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
788
789 /* Check if Multimode enabled */
790 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
791 {
792#if defined(ADC2) && defined(ADC3)
793 if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
794 || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
795 {
796#endif /* ADC2 || ADC3 */
797 /* if no external trigger present enable software conversion of regular channels */
798 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
799 {
800 /* Enable the selected ADC software conversion for regular group */
801 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
802 }
803#if defined(ADC2) && defined(ADC3)
804 }
805#endif /* ADC2 || ADC3 */
806 }
807 else
808 {
809 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
810 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
811 {
812 /* Enable the selected ADC software conversion for regular group */
813 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
814 }
815 }
816 }
817 else
818 {
819 /* Update ADC state machine to error */
820 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
821
822 /* Set ADC error code to ADC IP internal error */
823 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
824 }
825
826 /* Return function status */
827 return HAL_OK;
828}
829
830/**
831 * @brief Disables ADC and stop conversion of regular channels.
832 *
833 * @note Caution: This function will stop also injected channels.
834 *
835 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
836 * the configuration information for the specified ADC.
837 *
838 * @retval HAL status.
839 */
840HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
841{
842 /* Check the parameters */
843 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
844
845 /* Process locked */
846 __HAL_LOCK(hadc);
847
848 /* Stop potential conversion on going, on regular and injected groups */
849 /* Disable ADC peripheral */
850 __HAL_ADC_DISABLE(hadc);
851
852 /* Check if ADC is effectively disabled */
853 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
854 {
855 /* Set ADC state */
856 ADC_STATE_CLR_SET(hadc->State,
857 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
858 HAL_ADC_STATE_READY);
859 }
860
861 /* Process unlocked */
862 __HAL_UNLOCK(hadc);
863
864 /* Return function status */
865 return HAL_OK;
866}
867
868/**
869 * @brief Poll for regular conversion complete
870 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
871 * conversion) are cleared by this function.
872 * @note This function cannot be used in a particular setup: ADC configured
873 * in DMA mode and polling for end of each conversion (ADC init
874 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
875 * In this case, DMA resets the flag EOC and polling cannot be
876 * performed on each conversion. Nevertheless, polling can still
877 * be performed on the complete sequence.
878 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
879 * the configuration information for the specified ADC.
880 * @param Timeout Timeout value in millisecond.
881 * @retval HAL status
882 */
883HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
884{
885 uint32_t tickstart = 0U;
886
887 /* Verification that ADC configuration is compliant with polling for */
888 /* each conversion: */
889 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
890 /* several ranks and polling for end of each conversion. */
891 /* For code simplicity sake, this particular case is generalized to */
892 /* ADC configured in DMA mode and polling for end of each conversion. */
893 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
894 HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
895 {
896 /* Update ADC state machine to error */
897 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
898
899 /* Process unlocked */
900 __HAL_UNLOCK(hadc);
901
902 return HAL_ERROR;
903 }
904
905 /* Get tick */
906 tickstart = HAL_GetTick();
907
908 /* Check End of conversion flag */
909 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
910 {
911 /* Check if timeout is disabled (set to infinite wait) */
912 if(Timeout != HAL_MAX_DELAY)
913 {
914 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
915 {
916 /* New check to avoid false timeout detection in case of preemption */
917 if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
918 {
919 /* Update ADC state machine to timeout */
920 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
921
922 /* Process unlocked */
923 __HAL_UNLOCK(hadc);
924
925 return HAL_TIMEOUT;
926 }
927 }
928 }
929 }
930
931 /* Clear regular group conversion flag */
932 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
933
934 /* Update ADC state machine */
935 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
936
937 /* Determine whether any further conversion upcoming on group regular */
938 /* by external trigger, continuous mode or scan sequence on going. */
939 /* Note: On STM32F4, there is no independent flag of end of sequence. */
940 /* The test of scan sequence on going is done either with scan */
941 /* sequence disabled or with end of conversion flag set to */
942 /* of end of sequence. */
943 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
944 (hadc->Init.ContinuousConvMode == DISABLE) &&
945 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
946 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
947 {
948 /* Set ADC state */
949 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
950
951 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
952 {
953 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
954 }
955 }
956
957 /* Return ADC state */
958 return HAL_OK;
959}
960
961/**
962 * @brief Poll for conversion event
963 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
964 * the configuration information for the specified ADC.
965 * @param EventType the ADC event type.
966 * This parameter can be one of the following values:
967 * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
968 * @arg ADC_OVR_EVENT: ADC Overrun event.
969 * @param Timeout Timeout value in millisecond.
970 * @retval HAL status
971 */
972HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
973{
974 uint32_t tickstart = 0U;
975
976 /* Check the parameters */
977 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
978 assert_param(IS_ADC_EVENT_TYPE(EventType));
979
980 /* Get tick */
981 tickstart = HAL_GetTick();
982
983 /* Check selected event flag */
984 while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
985 {
986 /* Check for the Timeout */
987 if(Timeout != HAL_MAX_DELAY)
988 {
989 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
990 {
991 /* New check to avoid false timeout detection in case of preemption */
992 if(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
993 {
994 /* Update ADC state machine to timeout */
995 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
996
997 /* Process unlocked */
998 __HAL_UNLOCK(hadc);
999
1000 return HAL_TIMEOUT;
1001 }
1002 }
1003 }
1004 }
1005
1006 /* Analog watchdog (level out of window) event */
1007 if(EventType == ADC_AWD_EVENT)
1008 {
1009 /* Set ADC state */
1010 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1011
1012 /* Clear ADC analog watchdog flag */
1013 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1014 }
1015 /* Overrun event */
1016 else
1017 {
1018 /* Set ADC state */
1019 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1020 /* Set ADC error code to overrun */
1021 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1022
1023 /* Clear ADC overrun flag */
1024 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1025 }
1026
1027 /* Return ADC state */
1028 return HAL_OK;
1029}
1030
1031
1032/**
1033 * @brief Enables the interrupt and starts ADC conversion of regular channels.
1034 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1035 * the configuration information for the specified ADC.
1036 * @retval HAL status.
1037 */
1038HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
1039{
1040 __IO uint32_t counter = 0U;
1041 ADC_Common_TypeDef *tmpADC_Common;
1042
1043 /* Check the parameters */
1044 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1045 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1046
1047 /* Process locked */
1048 __HAL_LOCK(hadc);
1049
1050 /* Enable the ADC peripheral */
1051 /* Check if ADC peripheral is disabled in order to enable it and wait during
1052 Tstab time the ADC's stabilization */
1053 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
1054 {
1055 /* Enable the Peripheral */
1056 __HAL_ADC_ENABLE(hadc);
1057
1058 /* Delay for ADC stabilization time */
1059 /* Compute number of CPU cycles to wait for */
1060 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
1061 while(counter != 0U)
1062 {
1063 counter--;
1064 }
1065 }
1066
1067 /* Start conversion if ADC is effectively enabled */
1068 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
1069 {
1070 /* Set ADC state */
1071 /* - Clear state bitfield related to regular group conversion results */
1072 /* - Set state bitfield related to regular group operation */
1073 ADC_STATE_CLR_SET(hadc->State,
1074 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1075 HAL_ADC_STATE_REG_BUSY);
1076
1077 /* If conversions on group regular are also triggering group injected, */
1078 /* update ADC state. */
1079 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1080 {
1081 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1082 }
1083
1084 /* State machine update: Check if an injected conversion is ongoing */
1085 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1086 {
1087 /* Reset ADC error code fields related to conversions on group regular */
1088 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1089 }
1090 else
1091 {
1092 /* Reset ADC all error code fields */
1093 ADC_CLEAR_ERRORCODE(hadc);
1094 }
1095
1096 /* Process unlocked */
1097 /* Unlock before starting ADC conversions: in case of potential */
1098 /* interruption, to let the process to ADC IRQ Handler. */
1099 __HAL_UNLOCK(hadc);
1100
1101 /* Pointer to the common control register to which is belonging hadc */
1102 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1103 /* control register) */
1104 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1105
1106 /* Clear regular group conversion flag and overrun flag */
1107 /* (To ensure of no unknown state from potential previous ADC operations) */
1108 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1109
1110 /* Enable end of conversion interrupt for regular group */
1111 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
1112
1113 /* Check if Multimode enabled */
1114 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
1115 {
1116#if defined(ADC2) && defined(ADC3)
1117 if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
1118 || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
1119 {
1120#endif /* ADC2 || ADC3 */
1121 /* if no external trigger present enable software conversion of regular channels */
1122 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
1123 {
1124 /* Enable the selected ADC software conversion for regular group */
1125 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1126 }
1127#if defined(ADC2) && defined(ADC3)
1128 }
1129#endif /* ADC2 || ADC3 */
1130 }
1131 else
1132 {
1133 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
1134 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1135 {
1136 /* Enable the selected ADC software conversion for regular group */
1137 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1138 }
1139 }
1140 }
1141 else
1142 {
1143 /* Update ADC state machine to error */
1144 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1145
1146 /* Set ADC error code to ADC IP internal error */
1147 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1148 }
1149
1150 /* Return function status */
1151 return HAL_OK;
1152}
1153
1154/**
1155 * @brief Disables the interrupt and stop ADC conversion of regular channels.
1156 *
1157 * @note Caution: This function will stop also injected channels.
1158 *
1159 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1160 * the configuration information for the specified ADC.
1161 * @retval HAL status.
1162 */
1163HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
1164{
1165 /* Check the parameters */
1166 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1167
1168 /* Process locked */
1169 __HAL_LOCK(hadc);
1170
1171 /* Stop potential conversion on going, on regular and injected groups */
1172 /* Disable ADC peripheral */
1173 __HAL_ADC_DISABLE(hadc);
1174
1175 /* Check if ADC is effectively disabled */
1176 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
1177 {
1178 /* Disable ADC end of conversion interrupt for regular group */
1179 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
1180
1181 /* Set ADC state */
1182 ADC_STATE_CLR_SET(hadc->State,
1183 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1184 HAL_ADC_STATE_READY);
1185 }
1186
1187 /* Process unlocked */
1188 __HAL_UNLOCK(hadc);
1189
1190 /* Return function status */
1191 return HAL_OK;
1192}
1193
1194/**
1195 * @brief Handles ADC interrupt request
1196 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1197 * the configuration information for the specified ADC.
1198 * @retval None
1199 */
1200void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
1201{
1202 uint32_t tmp1 = 0U, tmp2 = 0U;
1203
1204 /* Check the parameters */
1205 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1206 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
1207 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
1208
1209 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
1210 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
1211 /* Check End of conversion flag for regular channels */
1212 if(tmp1 && tmp2)
1213 {
1214 /* Update state machine on conversion status if not in error state */
1215 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1216 {
1217 /* Set ADC state */
1218 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1219 }
1220
1221 /* Determine whether any further conversion upcoming on group regular */
1222 /* by external trigger, continuous mode or scan sequence on going. */
1223 /* Note: On STM32F4, there is no independent flag of end of sequence. */
1224 /* The test of scan sequence on going is done either with scan */
1225 /* sequence disabled or with end of conversion flag set to */
1226 /* of end of sequence. */
1227 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1228 (hadc->Init.ContinuousConvMode == DISABLE) &&
1229 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
1230 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
1231 {
1232 /* Disable ADC end of single conversion interrupt on group regular */
1233 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1234 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
1235 /* by overrun IRQ process below. */
1236 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1237
1238 /* Set ADC state */
1239 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1240
1241 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1242 {
1243 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1244 }
1245 }
1246
1247 /* Conversion complete callback */
1248#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1249 hadc->ConvCpltCallback(hadc);
1250#else
1251 HAL_ADC_ConvCpltCallback(hadc);
1252#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1253
1254 /* Clear regular group conversion flag */
1255 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
1256 }
1257
1258 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
1259 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
1260 /* Check End of conversion flag for injected channels */
1261 if(tmp1 && tmp2)
1262 {
1263 /* Update state machine on conversion status if not in error state */
1264 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1265 {
1266 /* Set ADC state */
1267 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
1268 }
1269
1270 /* Determine whether any further conversion upcoming on group injected */
1271 /* by external trigger, scan sequence on going or by automatic injected */
1272 /* conversion from group regular (same conditions as group regular */
1273 /* interruption disabling above). */
1274 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
1275 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
1276 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
1277 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
1278 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1279 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
1280 {
1281 /* Disable ADC end of single conversion interrupt on group injected */
1282 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1283
1284 /* Set ADC state */
1285 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1286
1287 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
1288 {
1289 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1290 }
1291 }
1292
1293 /* Conversion complete callback */
1294 /* Conversion complete callback */
1295#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1296 hadc->InjectedConvCpltCallback(hadc);
1297#else
1298 HAL_ADCEx_InjectedConvCpltCallback(hadc);
1299#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1300
1301 /* Clear injected group conversion flag */
1302 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
1303 }
1304
1305 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
1306 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
1307 /* Check Analog watchdog flag */
1308 if(tmp1 && tmp2)
1309 {
1310 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
1311 {
1312 /* Set ADC state */
1313 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1314
1315 /* Level out of window callback */
1316#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1317 hadc->LevelOutOfWindowCallback(hadc);
1318#else
1319 HAL_ADC_LevelOutOfWindowCallback(hadc);
1320#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1321
1322 /* Clear the ADC analog watchdog flag */
1323 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1324 }
1325 }
1326
1327 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
1328 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
1329 /* Check Overrun flag */
1330 if(tmp1 && tmp2)
1331 {
1332 /* Note: On STM32F4, ADC overrun can be set through other parameters */
1333 /* refer to description of parameter "EOCSelection" for more */
1334 /* details. */
1335
1336 /* Set ADC error code to overrun */
1337 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1338
1339 /* Clear ADC overrun flag */
1340 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1341
1342 /* Error callback */
1343#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1344 hadc->ErrorCallback(hadc);
1345#else
1346 HAL_ADC_ErrorCallback(hadc);
1347#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1348
1349 /* Clear the Overrun flag */
1350 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1351 }
1352}
1353
1354/**
1355 * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
1356 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1357 * the configuration information for the specified ADC.
1358 * @param pData The destination Buffer address.
1359 * @param Length The length of data to be transferred from ADC peripheral to memory.
1360 * @retval HAL status
1361 */
1362HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
1363{
1364 __IO uint32_t counter = 0U;
1365 ADC_Common_TypeDef *tmpADC_Common;
1366
1367 /* Check the parameters */
1368 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1369 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1370
1371 /* Process locked */
1372 __HAL_LOCK(hadc);
1373
1374 /* Enable the ADC peripheral */
1375 /* Check if ADC peripheral is disabled in order to enable it and wait during
1376 Tstab time the ADC's stabilization */
1377 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
1378 {
1379 /* Enable the Peripheral */
1380 __HAL_ADC_ENABLE(hadc);
1381
1382 /* Delay for ADC stabilization time */
1383 /* Compute number of CPU cycles to wait for */
1384 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
1385 while(counter != 0U)
1386 {
1387 counter--;
1388 }
1389 }
1390
1391 /* Check ADC DMA Mode */
1392 /* - disable the DMA Mode if it is already enabled */
1393 if((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA)
1394 {
1395 CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
1396 }
1397
1398 /* Start conversion if ADC is effectively enabled */
1399 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
1400 {
1401 /* Set ADC state */
1402 /* - Clear state bitfield related to regular group conversion results */
1403 /* - Set state bitfield related to regular group operation */
1404 ADC_STATE_CLR_SET(hadc->State,
1405 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1406 HAL_ADC_STATE_REG_BUSY);
1407
1408 /* If conversions on group regular are also triggering group injected, */
1409 /* update ADC state. */
1410 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1411 {
1412 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1413 }
1414
1415 /* State machine update: Check if an injected conversion is ongoing */
1416 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1417 {
1418 /* Reset ADC error code fields related to conversions on group regular */
1419 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1420 }
1421 else
1422 {
1423 /* Reset ADC all error code fields */
1424 ADC_CLEAR_ERRORCODE(hadc);
1425 }
1426
1427 /* Process unlocked */
1428 /* Unlock before starting ADC conversions: in case of potential */
1429 /* interruption, to let the process to ADC IRQ Handler. */
1430 __HAL_UNLOCK(hadc);
1431
1432 /* Pointer to the common control register to which is belonging hadc */
1433 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1434 /* control register) */
1435 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1436
1437 /* Set the DMA transfer complete callback */
1438 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1439
1440 /* Set the DMA half transfer complete callback */
1441 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1442
1443 /* Set the DMA error callback */
1444 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
1445
1446
1447 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1448 /* start (in case of SW start): */
1449
1450 /* Clear regular group conversion flag and overrun flag */
1451 /* (To ensure of no unknown state from potential previous ADC operations) */
1452 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1453
1454 /* Enable ADC overrun interrupt */
1455 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1456
1457 /* Enable ADC DMA mode */
1458 hadc->Instance->CR2 |= ADC_CR2_DMA;
1459
1460 /* Start the DMA channel */
1461 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
1462
1463 /* Check if Multimode enabled */
1464 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
1465 {
1466#if defined(ADC2) && defined(ADC3)
1467 if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
1468 || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
1469 {
1470#endif /* ADC2 || ADC3 */
1471 /* if no external trigger present enable software conversion of regular channels */
1472 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
1473 {
1474 /* Enable the selected ADC software conversion for regular group */
1475 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1476 }
1477#if defined(ADC2) && defined(ADC3)
1478 }
1479#endif /* ADC2 || ADC3 */
1480 }
1481 else
1482 {
1483 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
1484 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1485 {
1486 /* Enable the selected ADC software conversion for regular group */
1487 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1488 }
1489 }
1490 }
1491 else
1492 {
1493 /* Update ADC state machine to error */
1494 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1495
1496 /* Set ADC error code to ADC IP internal error */
1497 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1498 }
1499
1500 /* Return function status */
1501 return HAL_OK;
1502}
1503
1504/**
1505 * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
1506 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1507 * the configuration information for the specified ADC.
1508 * @retval HAL status
1509 */
1510HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
1511{
1512 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1513
1514 /* Check the parameters */
1515 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1516
1517 /* Process locked */
1518 __HAL_LOCK(hadc);
1519
1520 /* Stop potential conversion on going, on regular and injected groups */
1521 /* Disable ADC peripheral */
1522 __HAL_ADC_DISABLE(hadc);
1523
1524 /* Check if ADC is effectively disabled */
1525 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
1526 {
1527 /* Disable the selected ADC DMA mode */
1528 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
1529
1530 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1531 /* DMA transfer is on going) */
1532 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
1533 {
1534 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1535
1536 /* Check if DMA channel effectively disabled */
1537 if (tmp_hal_status != HAL_OK)
1538 {
1539 /* Update ADC state machine to error */
1540 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1541 }
1542 }
1543
1544 /* Disable ADC overrun interrupt */
1545 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1546
1547 /* Set ADC state */
1548 ADC_STATE_CLR_SET(hadc->State,
1549 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1550 HAL_ADC_STATE_READY);
1551 }
1552
1553 /* Process unlocked */
1554 __HAL_UNLOCK(hadc);
1555
1556 /* Return function status */
1557 return tmp_hal_status;
1558}
1559
1560/**
1561 * @brief Gets the converted value from data register of regular channel.
1562 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1563 * the configuration information for the specified ADC.
1564 * @retval Converted value
1565 */
1566uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
1567{
1568 /* Return the selected ADC converted value */
1569 return hadc->Instance->DR;
1570}
1571
1572/**
1573 * @brief Regular conversion complete callback in non blocking mode
1574 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1575 * the configuration information for the specified ADC.
1576 * @retval None
1577 */
1578__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
1579{
1580 /* Prevent unused argument(s) compilation warning */
1581 UNUSED(hadc);
1582 /* NOTE : This function Should not be modified, when the callback is needed,
1583 the HAL_ADC_ConvCpltCallback could be implemented in the user file
1584 */
1585}
1586
1587/**
1588 * @brief Regular conversion half DMA transfer callback in non blocking mode
1589 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1590 * the configuration information for the specified ADC.
1591 * @retval None
1592 */
1593__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
1594{
1595 /* Prevent unused argument(s) compilation warning */
1596 UNUSED(hadc);
1597 /* NOTE : This function Should not be modified, when the callback is needed,
1598 the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
1599 */
1600}
1601
1602/**
1603 * @brief Analog watchdog callback in non blocking mode
1604 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1605 * the configuration information for the specified ADC.
1606 * @retval None
1607 */
1608__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
1609{
1610 /* Prevent unused argument(s) compilation warning */
1611 UNUSED(hadc);
1612 /* NOTE : This function Should not be modified, when the callback is needed,
1613 the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
1614 */
1615}
1616
1617/**
1618 * @brief Error ADC callback.
1619 * @note In case of error due to overrun when using ADC with DMA transfer
1620 * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
1621 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
1622 * - If needed, restart a new ADC conversion using function
1623 * "HAL_ADC_Start_DMA()"
1624 * (this function is also clearing overrun flag)
1625 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1626 * the configuration information for the specified ADC.
1627 * @retval None
1628 */
1629__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
1630{
1631 /* Prevent unused argument(s) compilation warning */
1632 UNUSED(hadc);
1633 /* NOTE : This function Should not be modified, when the callback is needed,
1634 the HAL_ADC_ErrorCallback could be implemented in the user file
1635 */
1636}
1637
1638/**
1639 * @}
1640 */
1641
1642/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
1643 * @brief Peripheral Control functions
1644 *
1645@verbatim
1646 ===============================================================================
1647 ##### Peripheral Control functions #####
1648 ===============================================================================
1649 [..] This section provides functions allowing to:
1650 (+) Configure regular channels.
1651 (+) Configure injected channels.
1652 (+) Configure multimode.
1653 (+) Configure the analog watch dog.
1654
1655@endverbatim
1656 * @{
1657 */
1658
1659 /**
1660 * @brief Configures for the selected ADC regular channel its corresponding
1661 * rank in the sequencer and its sample time.
1662 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1663 * the configuration information for the specified ADC.
1664 * @param sConfig ADC configuration structure.
1665 * @retval HAL status
1666 */
1667HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
1668{
1669 __IO uint32_t counter = 0U;
1670 ADC_Common_TypeDef *tmpADC_Common;
1671
1672 /* Check the parameters */
1673 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
1674 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
1675 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
1676
1677 /* Process locked */
1678 __HAL_LOCK(hadc);
1679
1680 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
1681 if (sConfig->Channel > ADC_CHANNEL_9)
1682 {
1683 /* Clear the old sample time */
1684 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
1685
1686 /* Set the new sample time */
1687 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
1688 }
1689 else /* ADC_Channel include in ADC_Channel_[0..9] */
1690 {
1691 /* Clear the old sample time */
1692 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
1693
1694 /* Set the new sample time */
1695 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
1696 }
1697
1698 /* For Rank 1 to 6 */
1699 if (sConfig->Rank < 7U)
1700 {
1701 /* Clear the old SQx bits for the selected rank */
1702 hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
1703
1704 /* Set the SQx bits for the selected rank */
1705 hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
1706 }
1707 /* For Rank 7 to 12 */
1708 else if (sConfig->Rank < 13U)
1709 {
1710 /* Clear the old SQx bits for the selected rank */
1711 hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
1712
1713 /* Set the SQx bits for the selected rank */
1714 hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
1715 }
1716 /* For Rank 13 to 16 */
1717 else
1718 {
1719 /* Clear the old SQx bits for the selected rank */
1720 hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
1721
1722 /* Set the SQx bits for the selected rank */
1723 hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
1724 }
1725
1726 /* Pointer to the common control register to which is belonging hadc */
1727 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1728 /* control register) */
1729 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1730
1731 /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */
1732 if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
1733 {
1734 /* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
1735 if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
1736 {
1737 tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE;
1738 }
1739 /* Enable the VBAT channel*/
1740 tmpADC_Common->CCR |= ADC_CCR_VBATE;
1741 }
1742
1743 /* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or
1744 Channel_17 is selected for VREFINT enable TSVREFE */
1745 if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
1746 {
1747 /* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
1748 if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
1749 {
1750 tmpADC_Common->CCR &= ~ADC_CCR_VBATE;
1751 }
1752 /* Enable the Temperature sensor and VREFINT channel*/
1753 tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
1754
1755 if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
1756 {
1757 /* Delay for temperature sensor stabilization time */
1758 /* Compute number of CPU cycles to wait for */
1759 counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
1760 while(counter != 0U)
1761 {
1762 counter--;
1763 }
1764 }
1765 }
1766
1767 /* Process unlocked */
1768 __HAL_UNLOCK(hadc);
1769
1770 /* Return function status */
1771 return HAL_OK;
1772}
1773
1774/**
1775 * @brief Configures the analog watchdog.
1776 * @note Analog watchdog thresholds can be modified while ADC conversion
1777 * is on going.
1778 * In this case, some constraints must be taken into account:
1779 * The programmed threshold values are effective from the next
1780 * ADC EOC (end of unitary conversion).
1781 * Considering that registers write delay may happen due to
1782 * bus activity, this might cause an uncertainty on the
1783 * effective timing of the new programmed threshold values.
1784 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1785 * the configuration information for the specified ADC.
1786 * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure
1787 * that contains the configuration information of ADC analog watchdog.
1788 * @retval HAL status
1789 */
1790HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
1791{
1792#ifdef USE_FULL_ASSERT
1793 uint32_t tmp = 0U;
1794#endif /* USE_FULL_ASSERT */
1795
1796 /* Check the parameters */
1797 assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
1798 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
1799 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
1800
1801#ifdef USE_FULL_ASSERT
1802 tmp = ADC_GET_RESOLUTION(hadc);
1803 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
1804 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
1805#endif /* USE_FULL_ASSERT */
1806
1807 /* Process locked */
1808 __HAL_LOCK(hadc);
1809
1810 if(AnalogWDGConfig->ITMode == ENABLE)
1811 {
1812 /* Enable the ADC Analog watchdog interrupt */
1813 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
1814 }
1815 else
1816 {
1817 /* Disable the ADC Analog watchdog interrupt */
1818 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
1819 }
1820
1821 /* Clear AWDEN, JAWDEN and AWDSGL bits */
1822 hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
1823
1824 /* Set the analog watchdog enable mode */
1825 hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
1826
1827 /* Set the high threshold */
1828 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
1829
1830 /* Set the low threshold */
1831 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
1832
1833 /* Clear the Analog watchdog channel select bits */
1834 hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
1835
1836 /* Set the Analog watchdog channel */
1837 hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
1838
1839 /* Process unlocked */
1840 __HAL_UNLOCK(hadc);
1841
1842 /* Return function status */
1843 return HAL_OK;
1844}
1845
1846/**
1847 * @}
1848 */
1849
1850/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
1851 * @brief ADC Peripheral State functions
1852 *
1853@verbatim
1854 ===============================================================================
1855 ##### Peripheral State and errors functions #####
1856 ===============================================================================
1857 [..]
1858 This subsection provides functions allowing to
1859 (+) Check the ADC state
1860 (+) Check the ADC Error
1861
1862@endverbatim
1863 * @{
1864 */
1865
1866/**
1867 * @brief return the ADC state
1868 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1869 * the configuration information for the specified ADC.
1870 * @retval HAL state
1871 */
1872uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
1873{
1874 /* Return ADC state */
1875 return hadc->State;
1876}
1877
1878/**
1879 * @brief Return the ADC error code
1880 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1881 * the configuration information for the specified ADC.
1882 * @retval ADC Error Code
1883 */
1884uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
1885{
1886 return hadc->ErrorCode;
1887}
1888
1889/**
1890 * @}
1891 */
1892
1893/** @addtogroup ADC_Private_Functions
1894 * @{
1895 */
1896
1897/**
1898 * @brief Initializes the ADCx peripheral according to the specified parameters
1899 * in the ADC_InitStruct without initializing the ADC MSP.
1900 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1901 * the configuration information for the specified ADC.
1902 * @retval None
1903 */
1904static void ADC_Init(ADC_HandleTypeDef* hadc)
1905{
1906 ADC_Common_TypeDef *tmpADC_Common;
1907
1908 /* Set ADC parameters */
1909 /* Pointer to the common control register to which is belonging hadc */
1910 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1911 /* control register) */
1912 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1913
1914 /* Set the ADC clock prescaler */
1915 tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
1916 tmpADC_Common->CCR |= hadc->Init.ClockPrescaler;
1917
1918 /* Set ADC scan mode */
1919 hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
1920 hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
1921
1922 /* Set ADC resolution */
1923 hadc->Instance->CR1 &= ~(ADC_CR1_RES);
1924 hadc->Instance->CR1 |= hadc->Init.Resolution;
1925
1926 /* Set ADC data alignment */
1927 hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
1928 hadc->Instance->CR2 |= hadc->Init.DataAlign;
1929
1930 /* Enable external trigger if trigger selection is different of software */
1931 /* start. */
1932 /* Note: This configuration keeps the hardware feature of parameter */
1933 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
1934 /* software start. */
1935 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
1936 {
1937 /* Select external trigger to start conversion */
1938 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1939 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
1940
1941 /* Select external trigger polarity */
1942 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1943 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
1944 }
1945 else
1946 {
1947 /* Reset the external trigger */
1948 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1949 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1950 }
1951
1952 /* Enable or disable ADC continuous conversion mode */
1953 hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
1954 hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
1955
1956 if(hadc->Init.DiscontinuousConvMode != DISABLE)
1957 {
1958 assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
1959
1960 /* Enable the selected ADC regular discontinuous mode */
1961 hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
1962
1963 /* Set the number of channels to be converted in discontinuous mode */
1964 hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
1965 hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
1966 }
1967 else
1968 {
1969 /* Disable the selected ADC regular discontinuous mode */
1970 hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
1971 }
1972
1973 /* Set ADC number of conversion */
1974 hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
1975 hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
1976
1977 /* Enable or disable ADC DMA continuous request */
1978 hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
1979 hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
1980
1981 /* Enable or disable ADC end of conversion selection */
1982 hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
1983 hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
1984}
1985
1986/**
1987 * @brief DMA transfer complete callback.
1988 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1989 * the configuration information for the specified DMA module.
1990 * @retval None
1991 */
1992static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
1993{
1994 /* Retrieve ADC handle corresponding to current DMA handle */
1995 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1996
1997 /* Update state machine on conversion status if not in error state */
1998 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
1999 {
2000 /* Update ADC state machine */
2001 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2002
2003 /* Determine whether any further conversion upcoming on group regular */
2004 /* by external trigger, continuous mode or scan sequence on going. */
2005 /* Note: On STM32F4, there is no independent flag of end of sequence. */
2006 /* The test of scan sequence on going is done either with scan */
2007 /* sequence disabled or with end of conversion flag set to */
2008 /* of end of sequence. */
2009 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
2010 (hadc->Init.ContinuousConvMode == DISABLE) &&
2011 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
2012 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
2013 {
2014 /* Disable ADC end of single conversion interrupt on group regular */
2015 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2016 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
2017 /* by overrun IRQ process below. */
2018 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
2019
2020 /* Set ADC state */
2021 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
2022
2023 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
2024 {
2025 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2026 }
2027 }
2028
2029 /* Conversion complete callback */
2030#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2031 hadc->ConvCpltCallback(hadc);
2032#else
2033 HAL_ADC_ConvCpltCallback(hadc);
2034#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2035 }
2036 else /* DMA and-or internal error occurred */
2037 {
2038 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
2039 {
2040 /* Call HAL ADC Error Callback function */
2041#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2042 hadc->ErrorCallback(hadc);
2043#else
2044 HAL_ADC_ErrorCallback(hadc);
2045#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2046 }
2047 else
2048 {
2049 /* Call DMA error callback */
2050 hadc->DMA_Handle->XferErrorCallback(hdma);
2051 }
2052 }
2053}
2054
2055/**
2056 * @brief DMA half transfer complete callback.
2057 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2058 * the configuration information for the specified DMA module.
2059 * @retval None
2060 */
2061static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
2062{
2063 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2064 /* Half conversion callback */
2065#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2066 hadc->ConvHalfCpltCallback(hadc);
2067#else
2068 HAL_ADC_ConvHalfCpltCallback(hadc);
2069#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2070}
2071
2072/**
2073 * @brief DMA error callback
2074 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2075 * the configuration information for the specified DMA module.
2076 * @retval None
2077 */
2078static void ADC_DMAError(DMA_HandleTypeDef *hdma)
2079{
2080 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2081 hadc->State= HAL_ADC_STATE_ERROR_DMA;
2082 /* Set ADC error code to DMA error */
2083 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
2084 /* Error callback */
2085#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2086 hadc->ErrorCallback(hadc);
2087#else
2088 HAL_ADC_ErrorCallback(hadc);
2089#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2090}
2091
2092/**
2093 * @}
2094 */
2095
2096/**
2097 * @}
2098 */
2099
2100#endif /* HAL_ADC_MODULE_ENABLED */
2101/**
2102 * @}
2103 */
2104
2105/**
2106 * @}
2107 */
2108
2109/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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