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stm32f4xx_hal_cryp.c

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_hal_cryp.c
4	* @author MCD Application Team
5	* @brief CRYP HAL module driver.
6	* This file provides firmware functions to manage the following
7	* functionalities of the Cryptography (CRYP) peripheral:
8	* + Initialization, de-initialization, set config and get config functions
9	* + DES/TDES, AES processing functions
10	* + DMA callback functions
11	* + CRYP IRQ handler management
12	* + Peripheral State functions
13	*
14	@verbatim
15	==============================================================================
16	##### How to use this driver #####
17	==============================================================================
18	[..]
19	The CRYP HAL driver can be used in CRYP or TinyAES IP as follows:
20
21	(#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
22	(##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES IP
23	(##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
24	(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
25	(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
26	(+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
27	(##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
28	(+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
29	(+++) Configure and enable two DMA streams one for managing data transfer from
30	memory to peripheral (input stream) and another stream for managing data
31	transfer from peripheral to memory (output stream)
32	(+++) Associate the initialized DMA handle to the CRYP DMA handle
33	using __HAL_LINKDMA()
34	(+++) Configure the priority and enable the NVIC for the transfer complete
35	interrupt on the two DMA Streams. The output stream should have higher
36	priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
37
38	(#)Initialize the CRYP according to the specified parameters :
39	(##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
40	(##) The key size: 128, 192 or 256.
41	(##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
42	(##) The initialization vector (counter). It is not used in ECB mode.
43	(##) The key buffer used for encryption/decryption.
44	(##) The Header used only in AES GCM and CCM Algorithm for authentication.
45	(##) The HeaderSize The size of header buffer in word.
46	(##) The B0 block is the first authentication block used only in AES CCM mode.
47
48	(#)Three processing (encryption/decryption) functions are available:
49	(##) Polling mode: encryption and decryption APIs are blocking functions
50	i.e. they process the data and wait till the processing is finished,
51	e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
52	(##) Interrupt mode: encryption and decryption APIs are not blocking functions
53	i.e. they process the data under interrupt,
54	e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
55	(##) DMA mode: encryption and decryption APIs are not blocking functions
56	i.e. the data transfer is ensured by DMA,
57	e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
58
59	(#)When the processing function is called at first time after HAL_CRYP_Init()
60	the CRYP peripheral is configured and processes the buffer in input.
61	At second call, no need to Initialize the CRYP, user have to get current configuration via
62	HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
63	new parametres, finally user can start encryption/decryption.
64
65	(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
66
67	(#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
68	without having to configure again the Key or the Initialization Vector between each API call,
69	the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
70	Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
71	or HAL_CRYP_Decrypt_DMA().
72
73	[..]
74	The cryptographic processor supports following standards:
75	(#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
76	(##)64-bit data block processing
77	(##) chaining modes supported :
78	(+++) Electronic Code Book(ECB)
79	(+++) Cipher Block Chaining (CBC)
80	(##) keys length supported :64-bit, 128-bit and 192-bit.
81	(#) The advanced encryption standard (AES) supported by CRYP1 & TinyAES IP:
82	(##)128-bit data block processing
83	(##) chaining modes supported :
84	(+++) Electronic Code Book(ECB)
85	(+++) Cipher Block Chaining (CBC)
86	(+++) Counter mode (CTR)
87	(+++) Galois/counter mode (GCM/GMAC)
88	(+++) Counter with Cipher Block Chaining-Message(CCM)
89	(##) keys length Supported :
90	(+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
91	(+++) for TinyAES IP: 128-bit and 256-bit
92
93	[..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
94	(#) Algorithm supported :
95	(##) Galois/counter mode (GCM)
96	(##) Galois message authentication code (GMAC) :is exactly the same as
97	GCM algorithm composed only by an header.
98	(#) Four phases are performed in GCM :
99	(##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
100	(##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
101	computation only.
102	(##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
103	encryption + data XORing. It works in a similar way for ciphertext (C).
104	(##) Final phase: IP generates the authenticated tag (T) using the last block of data.
105	(#) structure of message construction in GCM is defined as below :
106	(##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
107	(##) The authenticated header A (also knows as Additional Authentication Data AAD)
108	this part of the message is only authenticated, not encrypted.
109	(##) The plaintext message P is both authenticated and encrypted as ciphertext.
110	GCM standard specifies that ciphertext has same bit length as the plaintext.
111	(##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
112	(on 64 bits)
113
114	[..] This section describe The AES Counter with Cipher Block Chaining-Message
115	Authentication Code (CCM) supported by both CRYP1 IP:
116	(#) Specific parameters for CCM :
117
118	(##) B0 block : According to NIST Special Publication 800-38C,
119	The first block B0 is formatted as follows, where l(m) is encoded in
120	most-significant-byte first order(see below table 3)
121
122	(+++) Q: a bit string representation of the octet length of P (plaintext)
123	(+++) q The octet length of the binary representation of the octet length of the payload
124	(+++) A nonce (N), n The octet length of the where n+q=15.
125	(+++) Flags: most significant octet containing four flags for control information,
126	(+++) t The octet length of the MAC.
127	(##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
128	the associated data length expressed in bytes (a) defined as below:
129	(+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
130	(+++) If 216-28 < a < 232, then it is encoded as 0xff \|\| 0xfe \|\| [a]32, i.e. six octets
131	(+++) If 232 < a < 264, then it is encoded as 0xff \|\| 0xff \|\| [a]64, i.e. ten octets
132	(##) CTRx block : control blocks
133	(+++) Generation of CTR1 from first block B0 information :
134	equal to B0 with first 5 bits zeroed and most significant bits storing octet
135	length of P also zeroed, then incremented by one ( see below Table 4)
136	(+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
137
138	(#) Four phases are performed in CCM for CRYP1 IP:
139	(##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
140	(##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
141	computation only.
142	(##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
143	encryption + data XORing. It works in a similar way for ciphertext (C).
144	(##) Final phase: IP generates the authenticated tag (T) using the last block of data.
145
146	* Callback registration *
147	=============================================
148
149	The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
150	allows the user to configure dynamically the driver callbacks.
151	Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
152	to register an interrupt callback.
153
154	Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
155	(+) InCpltCallback : Input FIFO transfer completed callback.
156	(+) OutCpltCallback : Output FIFO transfer completed callback.
157	(+) ErrorCallback : callback for error detection.
158	(+) MspInitCallback : CRYP MspInit.
159	(+) MspDeInitCallback : CRYP MspDeInit.
160	This function takes as parameters the HAL peripheral handle, the Callback ID
161	and a pointer to the user callback function.
162
163	Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
164	weak function.
165	@ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
166	and the Callback ID.
167	This function allows to reset following callbacks:
168	(+) InCpltCallback : Input FIFO transfer completed callback.
169	(+) OutCpltCallback : Output FIFO transfer completed callback.
170	(+) ErrorCallback : callback for error detection.
171	(+) MspInitCallback : CRYP MspInit.
172	(+) MspDeInitCallback : CRYP MspDeInit.
173
174	By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
175	all callbacks are set to the corresponding weak functions :
176	examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
177	Exception done for MspInit and MspDeInit functions that are
178	reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
179	these callbacks are null (not registered beforehand).
180	if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
181	keep and use the user MspInit/MspDeInit functions (registered beforehand)
182
183	Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
184	Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
185	in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
186	thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
187	In that case first register the MspInit/MspDeInit user callbacks
188	using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
189	or @ref HAL_CRYP_Init() function.
190
191	When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
192	not defined, the callback registration feature is not available and all callbacks
193	are set to the corresponding weak functions.
194
195	Table 1. Initial Counter Block (ICB)
196	+-------------------------------------------------------+
197	\| Initialization vector (IV) \| Counter \|
198	\|----------------\|----------------\|-----------\|---------\|
199	127 95 63 31 0
200
201
202	Bit Number Register Contents
203	---------- --------------- -----------
204	127 ...96 CRYP_IV1R[31:0] ICB[127:96]
205	95 ...64 CRYP_IV1L[31:0] B0[95:64]
206	63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
207	31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
208
209	Table 2. GCM last block definition
210
211	+-------------------------------------------------------------------+
212	\| Bit[0] \| Bit[32] \| Bit[64] \| Bit[96] \|
213	\|-----------\|--------------------\|-----------\|----------------------\|
214	\| 0x0 \| Header length[31:0]\| 0x0 \| Payload length[31:0] \|
215	\|-----------\|--------------------\|-----------\|----------------------\|
216
217	Table 3. B0 block
218	Octet Number Contents
219	------------ ---------
220	0 Flags
221	1 ... 15-q Nonce N
222	16-q ... 15 Q
223
224	the Flags field is formatted as follows:
225
226	Bit Number Contents
227	---------- ----------------------
228	7 Reserved (always zero)
229	6 Adata
230	5 ... 3 (t-2)/2
231	2 ... 0 [q-1]3
232
233	Table 4. CTRx block
234	Bit Number Register Contents
235	---------- --------------- -----------
236	127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
237	bit 0 that is set to 1
238	95 ...64 CRYP_IV1L[31:0] B0[95:64]
239	63 ... 32 CRYP_IV0R[31:0] B0[63:32]
240	31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
241
242	@endverbatim
243	******************************************************************************
244	* @attention
245	*
246	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
247	* All rights reserved.</center></h2>
248	*
249	* This software component is licensed by ST under BSD 3-Clause license,
250	* the "License"; You may not use this file except in compliance with the
251	* License. You may obtain a copy of the License at:
252	* opensource.org/licenses/BSD-3-Clause
253	*
254	******************************************************************************
255	*/
256
257	/* Includes ------------------------------------------------------------------*/
258	#include "stm32f4xx_hal.h"
259
260	/** @addtogroup STM32F4xx_HAL_Driver
261	* @{
262	*/
263
264	#if defined (AES) \|\| defined (CRYP)
265
266	/** @defgroup CRYP CRYP
267	* @brief CRYP HAL module driver.
268	* @{
269	*/
270
271
272	#ifdef HAL_CRYP_MODULE_ENABLED
273
274	/* Private typedef -----------------------------------------------------------*/
275	/* Private define ------------------------------------------------------------*/
276	/** @addtogroup CRYP_Private_Defines
277	* @{
278	*/
279	#define CRYP_TIMEOUT_KEYPREPARATION 82U /The latency of key preparation operation is 82 clock cycles./
280	#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
281	#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
282
283	#define CRYP_PHASE_READY 0x00000001U /!< CRYP peripheral is ready for initialization. /
284	#define CRYP_PHASE_PROCESS 0x00000002U /!< CRYP peripheral is in processing phase /
285
286	#if defined(AES)
287	#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /!< Encryption mode(Mode 1) /
288	#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) /
289	#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /!< Decryption (Mode 3) /
290	#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) /
291	#define CRYP_PHASE_INIT 0x00000000U /!< GCM/GMAC (or CCM) init phase /
292	#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /!< GCM/GMAC or CCM header phase /
293	#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /!< GCM(/CCM) payload phase /
294	#define CRYP_PHASE_FINAL AES_CR_GCMPH /!< GCM/GMAC or CCM final phase /
295	#else /* CRYP */
296	#define CRYP_PHASE_INIT 0x00000000U /!< GCM/GMAC (or CCM) init phase /
297	#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /!< GCM/GMAC or CCM header phase /
298	#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /!< GCM(/CCM) payload phase /
299	#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /!< GCM/GMAC or CCM final phase /
300	#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /!< Encryption mode /
301	#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /!< Decryption /
302	#endif /* End CRYP or AES */
303
304	/* CTR1 information to use in CCM algorithm */
305	#define CRYP_CCM_CTR1_0 0x07FFFFFFU
306	#define CRYP_CCM_CTR1_1 0xFFFFFF00U
307	#define CRYP_CCM_CTR1_2 0x00000001U
308
309
310	/**
311	* @}
312	*/
313
314
315	/* Private macro -------------------------------------------------------------*/
316	/** @addtogroup CRYP_Private_Macros
317	* @{
318	*/
319
320	#if defined(CRYP)
321
322	#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
323	(__HANDLE__)->Instance->CR \|= (uint32_t)(__PHASE__);\
324	}while(0)
325
326	#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR \|= CRYP_CR_FFLUSH)
327
328	#else /AES/
329	#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
330	(__HANDLE__)->Instance->CR \|= (uint32_t)(__PHASE__);\
331	}while(0)
332	#endif /* End AES or CRYP*/
333
334
335	/**
336	* @}
337	*/
338
339	/* Private struct -------------------------------------------------------------*/
340	/* Private variables ---------------------------------------------------------*/
341	/* Private function prototypes -----------------------------------------------*/
342	/** @addtogroup CRYP_Private_Functions_prototypes
343	* @{
344	*/
345
346	static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
347	static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
348	static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
349	static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
350	static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
351	static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
352	#if defined (CRYP_CR_ALGOMODE_AES_GCM)\|\| defined (AES)
353	static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
354	static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
355	static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
356	static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
357	static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
358	static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
359	static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
360	static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
361	static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
362	static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
363	static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
364	#endif /* AES or GCM CCM defined*/
365	static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
366	static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
367	static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
368	static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
369	static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
370	static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
371	#if defined (CRYP)
372	static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
373	#if defined (CRYP_CR_ALGOMODE_AES_GCM)
374	static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
375	#endif /* GCM CCM defined*/
376	static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
377	static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
378	static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
379	#else /AES/
380	static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
381	#endif /* End CRYP or AES */
382
383	/**
384	* @}
385	*/
386
387	/* Exported functions ---------------------------------------------------------*/
388
389	/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
390	* @{
391	*/
392
393
394	/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
395	* @brief Initialization and Configuration functions.
396	*
397	@verbatim
398	========================================================================================
399	##### Initialization, de-initialization and Set and Get configuration functions #####
400	========================================================================================
401	[..] This section provides functions allowing to:
402	(+) Initialize the CRYP
403	(+) DeInitialize the CRYP
404	(+) Initialize the CRYP MSP
405	(+) DeInitialize the CRYP MSP
406	(+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
407	Parameters which are configured in This section are :
408	(+) Key size
409	(+) Data Type : 32,16, 8 or 1bit
410	(+) AlgoMode :
411	- for CRYP1 IP :
412	ECB and CBC in DES/TDES Standard
413	ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
414	- for TinyAES2 IP, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
415	(+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
416
417
418	@endverbatim
419	* @{
420	*/
421
422
423	/**
424	* @brief Initializes the CRYP according to the specified
425	* parameters in the CRYP_ConfigTypeDef and creates the associated handle.
426	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
427	* the configuration information for CRYP module
428	* @retval HAL status
429	*/
430	HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
431	{
432	/* Check the CRYP handle allocation */
433	if (hcryp == NULL)
434	{
435	return HAL_ERROR;
436	}
437
438	/* Check parameters */
439	assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
440	assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
441	assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
442	assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
443
444	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
445	if (hcryp->State == HAL_CRYP_STATE_RESET)
446	{
447	/* Allocate lock resource and initialize it */
448	hcryp->Lock = HAL_UNLOCKED;
449
450	hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
451	hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
452	hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
453
454	if (hcryp->MspInitCallback == NULL)
455	{
456	hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
457	}
458
459	/* Init the low level hardware */
460	hcryp->MspInitCallback(hcryp);
461	}
462	#else
463	if (hcryp->State == HAL_CRYP_STATE_RESET)
464	{
465	/* Allocate lock resource and initialize it */
466	hcryp->Lock = HAL_UNLOCKED;
467
468	/* Init the low level hardware */
469	HAL_CRYP_MspInit(hcryp);
470	}
471	#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
472
473	/* Set the key size(This bit field is dont care in the DES or TDES modes) data type and Algorithm */
474	#if defined (CRYP)
475
476	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE \| CRYP_CR_KEYSIZE \| CRYP_CR_ALGOMODE,
477	hcryp->Init.DataType \| hcryp->Init.KeySize \| hcryp->Init.Algorithm);
478
479	#else /AES/
480
481	MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE \| AES_CR_KEYSIZE \| AES_CR_CHMOD,
482	hcryp->Init.DataType \| hcryp->Init.KeySize \| hcryp->Init.Algorithm);
483
484	#endif /* End AES or CRYP*/
485
486	/* Reset Error Code field */
487	hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
488
489	/* Change the CRYP state */
490	hcryp->State = HAL_CRYP_STATE_READY;
491
492	/* Set the default CRYP phase */
493	hcryp->Phase = CRYP_PHASE_READY;
494
495	/* Return function status */
496	return HAL_OK;
497	}
498
499	/**
500	* @brief De-Initializes the CRYP peripheral.
501	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
502	* the configuration information for CRYP module
503	* @retval HAL status
504	*/
505	HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
506	{
507	/* Check the CRYP handle allocation */
508	if (hcryp == NULL)
509	{
510	return HAL_ERROR;
511	}
512
513	/* Set the default CRYP phase */
514	hcryp->Phase = CRYP_PHASE_READY;
515
516	/* Reset CrypInCount and CrypOutCount */
517	hcryp->CrypInCount = 0;
518	hcryp->CrypOutCount = 0;
519	hcryp->CrypHeaderCount = 0;
520
521	/* Disable the CRYP peripheral clock */
522	__HAL_CRYP_DISABLE(hcryp);
523
524	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
525
526	if (hcryp->MspDeInitCallback == NULL)
527	{
528	hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
529	}
530	/* DeInit the low level hardware */
531	hcryp->MspDeInitCallback(hcryp);
532
533	#else
534
535	/* DeInit the low level hardware: CLOCK, NVIC.*/
536	HAL_CRYP_MspDeInit(hcryp);
537
538	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
539
540	/* Change the CRYP state */
541	hcryp->State = HAL_CRYP_STATE_RESET;
542
543	/* Release Lock */
544	__HAL_UNLOCK(hcryp);
545
546	/* Return function status */
547	return HAL_OK;
548	}
549
550	/**
551	* @brief Configure the CRYP according to the specified
552	* parameters in the CRYP_ConfigTypeDef
553	* @param hcryp: pointer to a CRYP_HandleTypeDef structure
554	* @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
555	* the configuration information for CRYP module
556	* @retval HAL status
557	*/
558	HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef hcryp, CRYP_ConfigTypeDef pConf)
559	{
560	/* Check the CRYP handle allocation */
561	if ((hcryp == NULL) \|\| (pConf == NULL))
562	{
563	return HAL_ERROR;
564	}
565
566	/* Check parameters */
567	assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
568	assert_param(IS_CRYP_DATATYPE(pConf->DataType));
569	assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
570
571	if (hcryp->State == HAL_CRYP_STATE_READY)
572	{
573	/* Change the CRYP state */
574	hcryp->State = HAL_CRYP_STATE_BUSY;
575
576	/* Process locked */
577	__HAL_LOCK(hcryp);
578
579	/* Set CRYP parameters */
580	hcryp->Init.DataType = pConf->DataType;
581	hcryp->Init.pKey = pConf->pKey;
582	hcryp->Init.Algorithm = pConf->Algorithm;
583	hcryp->Init.KeySize = pConf->KeySize;
584	hcryp->Init.pInitVect = pConf->pInitVect;
585	hcryp->Init.Header = pConf->Header;
586	hcryp->Init.HeaderSize = pConf->HeaderSize;
587	hcryp->Init.B0 = pConf->B0;
588	hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
589	hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
590	hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
591
592	/* Set the key size(This bit field is dont care in the DES or TDES modes) data type, AlgoMode and operating mode*/
593	#if defined (CRYP)
594
595	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE \| CRYP_CR_KEYSIZE \| CRYP_CR_ALGOMODE,
596	hcryp->Init.DataType \| hcryp->Init.KeySize \| hcryp->Init.Algorithm);
597
598	#else /AES/
599	MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE \| AES_CR_KEYSIZE \| AES_CR_CHMOD,
600	hcryp->Init.DataType \| hcryp->Init.KeySize \| hcryp->Init.Algorithm);
601
602	/clear error flags/
603	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
604
605	#endif /* End AES or CRYP */
606
607	/* Process Unlocked */
608	__HAL_UNLOCK(hcryp);
609
610	/* Reset Error Code field */
611	hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
612
613	/* Change the CRYP state */
614	hcryp->State = HAL_CRYP_STATE_READY;
615
616	/* Set the default CRYP phase */
617	hcryp->Phase = CRYP_PHASE_READY;
618
619	/* Return function status */
620	return HAL_OK;
621	}
622	else
623	{
624	/* Process Unlocked */
625	__HAL_UNLOCK(hcryp);
626
627	/* Busy error code field */
628	hcryp->ErrorCode \|= HAL_CRYP_ERROR_BUSY;
629	return HAL_ERROR;
630	}
631	}
632
633	/**
634	* @brief Get CRYP Configuration parameters in associated handle.
635	* @param pConf: pointer to a CRYP_ConfigTypeDef structure
636	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
637	* the configuration information for CRYP module
638	* @retval HAL status
639	*/
640	HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef hcryp, CRYP_ConfigTypeDef pConf)
641	{
642	/* Check the CRYP handle allocation */
643	if ((hcryp == NULL) \|\| (pConf == NULL))
644	{
645	return HAL_ERROR;
646	}
647
648	if (hcryp->State == HAL_CRYP_STATE_READY)
649	{
650	/* Change the CRYP state */
651	hcryp->State = HAL_CRYP_STATE_BUSY;
652
653	/* Process locked */
654	__HAL_LOCK(hcryp);
655
656	/* Get CRYP parameters */
657	pConf->DataType = hcryp->Init.DataType;
658	pConf->pKey = hcryp->Init.pKey;
659	pConf->Algorithm = hcryp->Init.Algorithm;
660	pConf->KeySize = hcryp->Init.KeySize ;
661	pConf->pInitVect = hcryp->Init.pInitVect;
662	pConf->Header = hcryp->Init.Header ;
663	pConf->HeaderSize = hcryp->Init.HeaderSize;
664	pConf->B0 = hcryp->Init.B0;
665	pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
666	pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
667	pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
668
669	/* Process Unlocked */
670	__HAL_UNLOCK(hcryp);
671
672	/* Change the CRYP state */
673	hcryp->State = HAL_CRYP_STATE_READY;
674
675	/* Return function status */
676	return HAL_OK;
677	}
678	else
679	{
680	/* Process Unlocked */
681	__HAL_UNLOCK(hcryp);
682
683	/* Busy error code field */
684	hcryp->ErrorCode \|= HAL_CRYP_ERROR_BUSY;
685	return HAL_ERROR;
686	}
687	}
688	/**
689	* @brief Initializes the CRYP MSP.
690	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
691	* the configuration information for CRYP module
692	* @retval None
693	*/
694	__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
695	{
696	/* Prevent unused argument(s) compilation warning */
697	UNUSED(hcryp);
698
699	/* NOTE : This function should not be modified, when the callback is needed,
700	the HAL_CRYP_MspInit can be implemented in the user file
701	*/
702	}
703
704	/**
705	* @brief DeInitializes CRYP MSP.
706	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
707	* the configuration information for CRYP module
708	* @retval None
709	*/
710	__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
711	{
712	/* Prevent unused argument(s) compilation warning */
713	UNUSED(hcryp);
714
715	/* NOTE : This function should not be modified, when the callback is needed,
716	the HAL_CRYP_MspDeInit can be implemented in the user file
717	*/
718	}
719
720	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
721	/**
722	* @brief Register a User CRYP Callback
723	* To be used instead of the weak predefined callback
724	* @param hcryp cryp handle
725	* @param CallbackID ID of the callback to be registered
726	* This parameter can be one of the following values:
727	* @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
728	* @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
729	* @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
730	* @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
731	* @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
732	* @param pCallback pointer to the Callback function
733	* @retval status
734	*/
735	HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
736	pCRYP_CallbackTypeDef pCallback)
737	{
738	HAL_StatusTypeDef status = HAL_OK;
739
740	if (pCallback == NULL)
741	{
742	/* Update the error code */
743	hcryp->ErrorCode \|= HAL_CRYP_ERROR_INVALID_CALLBACK;
744
745	return HAL_ERROR;
746	}
747	/* Process locked */
748	__HAL_LOCK(hcryp);
749
750	if (hcryp->State == HAL_CRYP_STATE_READY)
751	{
752	switch (CallbackID)
753	{
754	case HAL_CRYP_INPUT_COMPLETE_CB_ID :
755	hcryp->InCpltCallback = pCallback;
756	break;
757
758	case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
759	hcryp->OutCpltCallback = pCallback;
760	break;
761
762	case HAL_CRYP_ERROR_CB_ID :
763	hcryp->ErrorCallback = pCallback;
764	break;
765
766	case HAL_CRYP_MSPINIT_CB_ID :
767	hcryp->MspInitCallback = pCallback;
768	break;
769
770	case HAL_CRYP_MSPDEINIT_CB_ID :
771	hcryp->MspDeInitCallback = pCallback;
772	break;
773
774	default :
775	/* Update the error code */
776	hcryp->ErrorCode \|= HAL_CRYP_ERROR_INVALID_CALLBACK;
777	/* Return error status */
778	status = HAL_ERROR;
779	break;
780	}
781	}
782	else if (hcryp->State == HAL_CRYP_STATE_RESET)
783	{
784	switch (CallbackID)
785	{
786	case HAL_CRYP_MSPINIT_CB_ID :
787	hcryp->MspInitCallback = pCallback;
788	break;
789
790	case HAL_CRYP_MSPDEINIT_CB_ID :
791	hcryp->MspDeInitCallback = pCallback;
792	break;
793
794	default :
795	/* Update the error code */
796	hcryp->ErrorCode \|= HAL_CRYP_ERROR_INVALID_CALLBACK;
797	/* Return error status */
798	status = HAL_ERROR;
799	break;
800	}
801	}
802	else
803	{
804	/* Update the error code */
805	hcryp->ErrorCode \|= HAL_CRYP_ERROR_INVALID_CALLBACK;
806	/* Return error status */
807	status = HAL_ERROR;
808	}
809
810	/* Release Lock */
811	__HAL_UNLOCK(hcryp);
812
813	return status;
814	}
815
816	/**
817	* @brief Unregister an CRYP Callback
818	* CRYP callback is redirected to the weak predefined callback
819	* @param hcryp cryp handle
820	* @param CallbackID ID of the callback to be unregistered
821	* This parameter can be one of the following values:
822	* @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
823	* @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
824	* @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
825	* @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
826	* @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
827	* @retval status
828	*/
829	HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
830	{
831	HAL_StatusTypeDef status = HAL_OK;
832
833	/* Process locked */
834	__HAL_LOCK(hcryp);
835
836	if (hcryp->State == HAL_CRYP_STATE_READY)
837	{
838	switch (CallbackID)
839	{
840	case HAL_CRYP_INPUT_COMPLETE_CB_ID :
841	hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
842	break;
843
844	case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
845	hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
846	break;
847
848	case HAL_CRYP_ERROR_CB_ID :
849	hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
850	break;
851
852	case HAL_CRYP_MSPINIT_CB_ID :
853	hcryp->MspInitCallback = HAL_CRYP_MspInit;
854	break;
855
856	case HAL_CRYP_MSPDEINIT_CB_ID :
857	hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
858	break;
859
860	default :
861	/* Update the error code */
862	hcryp->ErrorCode \|= HAL_CRYP_ERROR_INVALID_CALLBACK;
863	/* Return error status */
864	status = HAL_ERROR;
865	break;
866	}
867	}
868	else if (hcryp->State == HAL_CRYP_STATE_RESET)
869	{
870	switch (CallbackID)
871	{
872	case HAL_CRYP_MSPINIT_CB_ID :
873	hcryp->MspInitCallback = HAL_CRYP_MspInit;
874	break;
875
876	case HAL_CRYP_MSPDEINIT_CB_ID :
877	hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
878	break;
879
880	default :
881	/* Update the error code */
882	hcryp->ErrorCode \|= HAL_CRYP_ERROR_INVALID_CALLBACK;
883	/* Return error status */
884	status = HAL_ERROR;
885	break;
886	}
887	}
888	else
889	{
890	/* Update the error code */
891	hcryp->ErrorCode \|= HAL_CRYP_ERROR_INVALID_CALLBACK;
892	/* Return error status */
893	status = HAL_ERROR;
894	}
895
896	/* Release Lock */
897	__HAL_UNLOCK(hcryp);
898
899	return status;
900	}
901	#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
902	/**
903	* @}
904	*/
905
906	/** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
907	* @brief processing functions.
908	*
909	@verbatim
910	==============================================================================
911	##### Encrypt Decrypt functions #####
912	==============================================================================
913	[..] This section provides API allowing to Encrypt/Decrypt Data following
914	Standard DES/TDES or AES, and Algorithm configured by the user:
915	(+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
916	- Electronic Code Book(ECB)
917	- Cipher Block Chaining (CBC)
918	(+) Standard AES supported by CRYP1 IP & TinyAES, list of Algorithm supported:
919	- Electronic Code Book(ECB)
920	- Cipher Block Chaining (CBC)
921	- Counter mode (CTR)
922	- Cipher Block Chaining (CBC)
923	- Counter mode (CTR)
924	- Galois/counter mode (GCM)
925	- Counter with Cipher Block Chaining-Message(CCM)
926	[..] Three processing functions are available:
927	(+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
928	(+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
929	(+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
930
931	@endverbatim
932	* @{
933	*/
934
935
936	/**
937	* @brief Encryption mode.
938	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
939	* the configuration information for CRYP module
940	* @param Input: Pointer to the input buffer (plaintext)
941	* @param Size: Length of the plaintext buffer in word.
942	* @param Output: Pointer to the output buffer(ciphertext)
943	* @param Timeout: Specify Timeout value
944	* @retval HAL status
945	*/
946	HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef hcryp, uint32_t Input, uint16_t Size, uint32_t *Output,
947	uint32_t Timeout)
948	{
949	uint32_t algo;
950	HAL_StatusTypeDef status;
951
952	if (hcryp->State == HAL_CRYP_STATE_READY)
953	{
954	/* Change state Busy */
955	hcryp->State = HAL_CRYP_STATE_BUSY;
956
957	/* Process locked */
958	__HAL_LOCK(hcryp);
959
960	/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
961	hcryp->CrypInCount = 0U;
962	hcryp->CrypOutCount = 0U;
963	hcryp->pCrypInBuffPtr = Input;
964	hcryp->pCrypOutBuffPtr = Output;
965
966	/* Calculate Size parameter in Byte*/
967	if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
968	{
969	hcryp->Size = Size * 4U;
970	}
971	else
972	{
973	hcryp->Size = Size;
974	}
975
976	#if defined (CRYP)
977	/* Set Encryption operating mode*/
978	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
979
980	/* algo get algorithm selected */
981	algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
982
983	switch (algo)
984	{
985	case CRYP_DES_ECB:
986	case CRYP_DES_CBC:
987	case CRYP_TDES_ECB:
988	case CRYP_TDES_CBC:
989
990	/Set Key /
991	hcryp->Instance->K1LR = (uint32_t )(hcryp->Init.pKey);
992	hcryp->Instance->K1RR = (uint32_t )(hcryp->Init.pKey + 1);
993	if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
994	{
995	hcryp->Instance->K2LR = (uint32_t )(hcryp->Init.pKey + 2);
996	hcryp->Instance->K2RR = (uint32_t )(hcryp->Init.pKey + 3);
997	hcryp->Instance->K3LR = (uint32_t )(hcryp->Init.pKey + 4);
998	hcryp->Instance->K3RR = (uint32_t )(hcryp->Init.pKey + 5);
999	}
1000
1001	/Set Initialization Vector (IV)/
1002	if ((hcryp->Init.Algorithm == CRYP_DES_CBC) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1003	{
1004	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
1005	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
1006	}
1007
1008	/* Flush FIFO */
1009	HAL_CRYP_FIFO_FLUSH(hcryp);
1010
1011	/* Set the phase */
1012	hcryp->Phase = CRYP_PHASE_PROCESS;
1013
1014	/* Statrt DES/TDES encryption process */
1015	status = CRYP_TDES_Process(hcryp, Timeout);
1016	break;
1017
1018	case CRYP_AES_ECB:
1019	case CRYP_AES_CBC:
1020	case CRYP_AES_CTR:
1021
1022	/* AES encryption */
1023	status = CRYP_AES_Encrypt(hcryp, Timeout);
1024	break;
1025	#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1026	case CRYP_AES_GCM:
1027
1028	/* AES GCM encryption */
1029	status = CRYP_AESGCM_Process(hcryp, Timeout);
1030
1031	break;
1032
1033	case CRYP_AES_CCM:
1034
1035	/* AES CCM encryption */
1036	status = CRYP_AESCCM_Process(hcryp, Timeout);
1037	break;
1038	#endif /* GCM CCM defined*/
1039	default:
1040	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1041	/* Change the CRYP peripheral state */
1042	hcryp->State = HAL_CRYP_STATE_READY;
1043	/* Process unlocked */
1044	__HAL_UNLOCK(hcryp);
1045	return HAL_ERROR;
1046	}
1047
1048	#else /AES/
1049
1050	/* Set the operating mode*/
1051	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1052
1053	/* algo get algorithm selected */
1054	algo = hcryp->Instance->CR & AES_CR_CHMOD;
1055
1056	switch (algo)
1057	{
1058
1059	case CRYP_AES_ECB:
1060	case CRYP_AES_CBC:
1061	case CRYP_AES_CTR:
1062
1063	/* AES encryption */
1064	status = CRYP_AES_Encrypt(hcryp, Timeout);
1065	break;
1066
1067	case CRYP_AES_GCM_GMAC:
1068
1069	/* AES GCM encryption */
1070	status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1071	break;
1072
1073	case CRYP_AES_CCM:
1074
1075	/* AES CCM encryption */
1076	status = CRYP_AESCCM_Process(hcryp, Timeout);
1077	break;
1078
1079	default:
1080	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1081	/* Change the CRYP peripheral state */
1082	hcryp->State = HAL_CRYP_STATE_READY;
1083	/* Process unlocked */
1084	__HAL_UNLOCK(hcryp);
1085	return HAL_ERROR;
1086	}
1087	#endif /end AES or CRYP /
1088
1089	if (status == HAL_OK)
1090	{
1091	/* Change the CRYP peripheral state */
1092	hcryp->State = HAL_CRYP_STATE_READY;
1093
1094	/* Process unlocked */
1095	__HAL_UNLOCK(hcryp);
1096	}
1097	}
1098	else
1099	{
1100	/* Busy error code field */
1101	hcryp->ErrorCode \|= HAL_CRYP_ERROR_BUSY;
1102	return HAL_ERROR;
1103	}
1104
1105	/* Return function status */
1106	return HAL_OK;
1107	}
1108
1109	/**
1110	* @brief Decryption mode.
1111	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1112	* the configuration information for CRYP module
1113	* @param Input: Pointer to the input buffer (ciphertext )
1114	* @param Size: Length of the plaintext buffer in word.
1115	* @param Output: Pointer to the output buffer(plaintext)
1116	* @param Timeout: Specify Timeout value
1117	* @retval HAL status
1118	*/
1119	HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef hcryp, uint32_t Input, uint16_t Size, uint32_t *Output,
1120	uint32_t Timeout)
1121	{
1122	HAL_StatusTypeDef status;
1123	uint32_t algo;
1124
1125	if (hcryp->State == HAL_CRYP_STATE_READY)
1126	{
1127	/* Change state Busy */
1128	hcryp->State = HAL_CRYP_STATE_BUSY;
1129
1130	/* Process locked */
1131	__HAL_LOCK(hcryp);
1132
1133	/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1134	hcryp->CrypInCount = 0U;
1135	hcryp->CrypOutCount = 0U;
1136	hcryp->pCrypInBuffPtr = Input;
1137	hcryp->pCrypOutBuffPtr = Output;
1138
1139	/* Calculate Size parameter in Byte*/
1140	if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1141	{
1142	hcryp->Size = Size * 4U;
1143	}
1144	else
1145	{
1146	hcryp->Size = Size;
1147	}
1148
1149	#if defined (CRYP)
1150
1151	/* Set Decryption operating mode*/
1152	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1153
1154	/* algo get algorithm selected */
1155	algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1156
1157	switch (algo)
1158	{
1159	case CRYP_DES_ECB:
1160	case CRYP_DES_CBC:
1161	case CRYP_TDES_ECB:
1162	case CRYP_TDES_CBC:
1163
1164	/Set Key /
1165	hcryp->Instance->K1LR = (uint32_t )(hcryp->Init.pKey);
1166	hcryp->Instance->K1RR = (uint32_t )(hcryp->Init.pKey + 1);
1167	if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1168	{
1169	hcryp->Instance->K2LR = (uint32_t )(hcryp->Init.pKey + 2);
1170	hcryp->Instance->K2RR = (uint32_t )(hcryp->Init.pKey + 3);
1171	hcryp->Instance->K3LR = (uint32_t )(hcryp->Init.pKey + 4);
1172	hcryp->Instance->K3RR = (uint32_t )(hcryp->Init.pKey + 5);
1173	}
1174
1175	/Set Initialization Vector (IV)/
1176	if ((hcryp->Init.Algorithm == CRYP_DES_CBC) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1177	{
1178	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
1179	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
1180	}
1181
1182	/* Flush FIFO */
1183	HAL_CRYP_FIFO_FLUSH(hcryp);
1184
1185	/* Set the phase */
1186	hcryp->Phase = CRYP_PHASE_PROCESS;
1187
1188	/* Start DES/TDES decryption process */
1189	status = CRYP_TDES_Process(hcryp, Timeout);
1190
1191	break;
1192
1193	case CRYP_AES_ECB:
1194	case CRYP_AES_CBC:
1195	case CRYP_AES_CTR:
1196
1197	/* AES decryption */
1198	status = CRYP_AES_Decrypt(hcryp, Timeout);
1199	break;
1200	#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1201	case CRYP_AES_GCM:
1202
1203	/* AES GCM decryption */
1204	status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1205	break;
1206
1207	case CRYP_AES_CCM:
1208
1209	/* AES CCM decryption */
1210	status = CRYP_AESCCM_Process(hcryp, Timeout);
1211	break;
1212	#endif /* GCM CCM defined*/
1213	default:
1214	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1215	/* Change the CRYP peripheral state */
1216	hcryp->State = HAL_CRYP_STATE_READY;
1217	/* Process unlocked */
1218	__HAL_UNLOCK(hcryp);
1219	return HAL_ERROR;
1220	}
1221
1222	#else /AES/
1223
1224	/* Set Decryption operating mode*/
1225	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1226
1227	/* algo get algorithm selected */
1228	algo = hcryp->Instance->CR & AES_CR_CHMOD;
1229
1230	switch (algo)
1231	{
1232
1233	case CRYP_AES_ECB:
1234	case CRYP_AES_CBC:
1235	case CRYP_AES_CTR:
1236
1237	/* AES decryption */
1238	status = CRYP_AES_Decrypt(hcryp, Timeout);
1239	break;
1240
1241	case CRYP_AES_GCM_GMAC:
1242
1243	/* AES GCM decryption */
1244	status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1245	break;
1246
1247	case CRYP_AES_CCM:
1248
1249	/* AES CCM decryption */
1250	status = CRYP_AESCCM_Process(hcryp, Timeout);
1251	break;
1252
1253	default:
1254	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1255	/* Change the CRYP peripheral state */
1256	hcryp->State = HAL_CRYP_STATE_READY;
1257	/* Process unlocked */
1258	__HAL_UNLOCK(hcryp);
1259	return HAL_ERROR;
1260	}
1261	#endif /* End AES or CRYP */
1262
1263	if (status == HAL_OK)
1264	{
1265	/* Change the CRYP peripheral state */
1266	hcryp->State = HAL_CRYP_STATE_READY;
1267
1268	/* Process unlocked */
1269	__HAL_UNLOCK(hcryp);
1270	}
1271	}
1272	else
1273	{
1274	/* Busy error code field */
1275	hcryp->ErrorCode \|= HAL_CRYP_ERROR_BUSY;
1276	return HAL_ERROR;
1277	}
1278
1279	/* Return function status */
1280	return HAL_OK;
1281	}
1282
1283	/**
1284	* @brief Encryption in interrupt mode.
1285	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1286	* the configuration information for CRYP module
1287	* @param Input: Pointer to the input buffer (plaintext)
1288	* @param Size: Length of the plaintext buffer in word
1289	* @param Output: Pointer to the output buffer(ciphertext)
1290	* @retval HAL status
1291	*/
1292	HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef hcryp, uint32_t Input, uint16_t Size, uint32_t *Output)
1293	{
1294	uint32_t algo;
1295	HAL_StatusTypeDef status = HAL_OK;
1296
1297	if (hcryp->State == HAL_CRYP_STATE_READY)
1298	{
1299	/* Change state Busy */
1300	hcryp->State = HAL_CRYP_STATE_BUSY;
1301
1302	/* Process locked */
1303	__HAL_LOCK(hcryp);
1304
1305	/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1306	hcryp->CrypInCount = 0U;
1307	hcryp->CrypOutCount = 0U;
1308	hcryp->pCrypInBuffPtr = Input;
1309	hcryp->pCrypOutBuffPtr = Output;
1310
1311	/* Calculate Size parameter in Byte*/
1312	if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1313	{
1314	hcryp->Size = Size * 4U;
1315	}
1316	else
1317	{
1318	hcryp->Size = Size;
1319	}
1320
1321	#if defined (CRYP)
1322
1323	/* Set encryption operating mode*/
1324	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1325
1326	/* algo get algorithm selected */
1327	algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
1328
1329	switch (algo)
1330	{
1331	case CRYP_DES_ECB:
1332	case CRYP_DES_CBC:
1333	case CRYP_TDES_ECB:
1334	case CRYP_TDES_CBC:
1335
1336	/Set Key /
1337	hcryp->Instance->K1LR = (uint32_t )(hcryp->Init.pKey);
1338	hcryp->Instance->K1RR = (uint32_t )(hcryp->Init.pKey + 1);
1339	if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1340	{
1341	hcryp->Instance->K2LR = (uint32_t )(hcryp->Init.pKey + 2);
1342	hcryp->Instance->K2RR = (uint32_t )(hcryp->Init.pKey + 3);
1343	hcryp->Instance->K3LR = (uint32_t )(hcryp->Init.pKey + 4);
1344	hcryp->Instance->K3RR = (uint32_t )(hcryp->Init.pKey + 5);
1345	}
1346	/* Set the Initialization Vector*/
1347	if ((hcryp->Init.Algorithm == CRYP_DES_CBC) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1348	{
1349	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
1350	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
1351	}
1352
1353	/* Flush FIFO */
1354	HAL_CRYP_FIFO_FLUSH(hcryp);
1355
1356	/* Set the phase */
1357	hcryp->Phase = CRYP_PHASE_PROCESS;
1358
1359	/* Enable interrupts */
1360	__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI \| CRYP_IT_OUTI);
1361
1362	/* Enable CRYP to start DES/TDES process*/
1363	__HAL_CRYP_ENABLE(hcryp);
1364	break;
1365
1366	case CRYP_AES_ECB:
1367	case CRYP_AES_CBC:
1368	case CRYP_AES_CTR:
1369
1370	status = CRYP_AES_Encrypt_IT(hcryp);
1371	break;
1372	#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1373	case CRYP_AES_GCM:
1374
1375	status = CRYP_AESGCM_Process_IT(hcryp) ;
1376	break;
1377
1378	case CRYP_AES_CCM:
1379
1380	status = CRYP_AESCCM_Process_IT(hcryp);
1381	break;
1382	#endif /* GCM CCM defined*/
1383	default:
1384	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1385	/* Change the CRYP peripheral state */
1386	hcryp->State = HAL_CRYP_STATE_READY;
1387	/* Process unlocked */
1388	__HAL_UNLOCK(hcryp);
1389	status = HAL_ERROR;
1390	break;
1391	}
1392
1393	#else /* AES */
1394
1395	/* Set encryption operating mode*/
1396	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1397
1398	/* algo get algorithm selected */
1399	algo = hcryp->Instance->CR & AES_CR_CHMOD;
1400
1401	switch (algo)
1402	{
1403	case CRYP_AES_ECB:
1404	case CRYP_AES_CBC:
1405	case CRYP_AES_CTR:
1406
1407	/* AES encryption */
1408	status = CRYP_AES_Encrypt_IT(hcryp);
1409	break;
1410
1411	case CRYP_AES_GCM_GMAC:
1412
1413	/* AES GCM encryption */
1414	status = CRYP_AESGCM_Process_IT(hcryp) ;
1415	break;
1416
1417	case CRYP_AES_CCM:
1418
1419	/* AES CCM encryption */
1420	status = CRYP_AESCCM_Process_IT(hcryp);
1421	break;
1422
1423	default:
1424	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1425	/* Change the CRYP peripheral state */
1426	hcryp->State = HAL_CRYP_STATE_READY;
1427	/* Process unlocked */
1428	__HAL_UNLOCK(hcryp);
1429	status = HAL_ERROR;
1430	break;
1431	}
1432	#endif /end AES or CRYP/
1433
1434	}
1435	else
1436	{
1437	/* Busy error code field */
1438	hcryp->ErrorCode \|= HAL_CRYP_ERROR_BUSY;
1439	status = HAL_ERROR;
1440	}
1441
1442	/* Return function status */
1443	return status;
1444	}
1445
1446	/**
1447	* @brief Decryption in itnterrupt mode.
1448	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1449	* the configuration information for CRYP module
1450	* @param Input: Pointer to the input buffer (ciphertext )
1451	* @param Size: Length of the plaintext buffer in word.
1452	* @param Output: Pointer to the output buffer(plaintext)
1453	* @retval HAL status
1454	*/
1455	HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef hcryp, uint32_t Input, uint16_t Size, uint32_t *Output)
1456	{
1457	uint32_t algo;
1458	HAL_StatusTypeDef status = HAL_OK;
1459
1460	if (hcryp->State == HAL_CRYP_STATE_READY)
1461	{
1462	/* Change state Busy */
1463	hcryp->State = HAL_CRYP_STATE_BUSY;
1464
1465	/* Process locked */
1466	__HAL_LOCK(hcryp);
1467
1468	/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1469	hcryp->CrypInCount = 0U;
1470	hcryp->CrypOutCount = 0U;
1471	hcryp->pCrypInBuffPtr = Input;
1472	hcryp->pCrypOutBuffPtr = Output;
1473
1474	/* Calculate Size parameter in Byte*/
1475	if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1476	{
1477	hcryp->Size = Size * 4U;
1478	}
1479	else
1480	{
1481	hcryp->Size = Size;
1482	}
1483
1484	#if defined (CRYP)
1485
1486	/* Set decryption operating mode*/
1487	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1488
1489	/* algo get algorithm selected */
1490	algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1491
1492	switch (algo)
1493	{
1494	case CRYP_DES_ECB:
1495	case CRYP_DES_CBC:
1496	case CRYP_TDES_ECB:
1497	case CRYP_TDES_CBC:
1498
1499	/Set Key /
1500	hcryp->Instance->K1LR = (uint32_t )(hcryp->Init.pKey);
1501	hcryp->Instance->K1RR = (uint32_t )(hcryp->Init.pKey + 1);
1502	if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1503	{
1504	hcryp->Instance->K2LR = (uint32_t )(hcryp->Init.pKey + 2);
1505	hcryp->Instance->K2RR = (uint32_t )(hcryp->Init.pKey + 3);
1506	hcryp->Instance->K3LR = (uint32_t )(hcryp->Init.pKey + 4);
1507	hcryp->Instance->K3RR = (uint32_t )(hcryp->Init.pKey + 5);
1508	}
1509
1510	/* Set the Initialization Vector*/
1511	if ((hcryp->Init.Algorithm == CRYP_DES_CBC) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1512	{
1513	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
1514	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
1515	}
1516	/* Flush FIFO */
1517	HAL_CRYP_FIFO_FLUSH(hcryp);
1518
1519	/* Set the phase */
1520	hcryp->Phase = CRYP_PHASE_PROCESS;
1521
1522	/* Enable interrupts */
1523	__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI \| CRYP_IT_OUTI);
1524
1525	/* Enable CRYP and start DES/TDES process*/
1526	__HAL_CRYP_ENABLE(hcryp);
1527
1528	break;
1529
1530	case CRYP_AES_ECB:
1531	case CRYP_AES_CBC:
1532	case CRYP_AES_CTR:
1533
1534	/* AES decryption */
1535	status = CRYP_AES_Decrypt_IT(hcryp);
1536	break;
1537	#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1538	case CRYP_AES_GCM:
1539
1540	/* AES GCM decryption */
1541	status = CRYP_AESGCM_Process_IT(hcryp) ;
1542	break;
1543
1544	case CRYP_AES_CCM:
1545
1546	/* AES CCMdecryption */
1547	status = CRYP_AESCCM_Process_IT(hcryp);
1548	break;
1549	#endif /* GCM CCM defined*/
1550	default:
1551	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1552	/* Change the CRYP peripheral state */
1553	hcryp->State = HAL_CRYP_STATE_READY;
1554	/* Process unlocked */
1555	__HAL_UNLOCK(hcryp);
1556	status = HAL_ERROR;
1557	break;
1558	}
1559
1560	#else /AES/
1561
1562	/* Set decryption operating mode*/
1563	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1564
1565	/* algo get algorithm selected */
1566	algo = hcryp->Instance->CR & AES_CR_CHMOD;
1567
1568	switch (algo)
1569	{
1570	case CRYP_AES_ECB:
1571	case CRYP_AES_CBC:
1572	case CRYP_AES_CTR:
1573
1574	/* AES decryption */
1575	status = CRYP_AES_Decrypt_IT(hcryp);
1576	break;
1577
1578	case CRYP_AES_GCM_GMAC:
1579
1580	/* AES GCM decryption */
1581	status = CRYP_AESGCM_Process_IT(hcryp) ;
1582	break;
1583
1584	case CRYP_AES_CCM:
1585
1586	/* AES CCM decryption */
1587	status = CRYP_AESCCM_Process_IT(hcryp);
1588	break;
1589
1590	default:
1591	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1592	/* Change the CRYP peripheral state */
1593	hcryp->State = HAL_CRYP_STATE_READY;
1594	/* Process unlocked */
1595	__HAL_UNLOCK(hcryp);
1596	status = HAL_ERROR;
1597	break;
1598	}
1599	#endif /* End AES or CRYP */
1600
1601	}
1602	else
1603	{
1604	/* Busy error code field */
1605	hcryp->ErrorCode \|= HAL_CRYP_ERROR_BUSY;
1606	status = HAL_ERROR;
1607	}
1608
1609	/* Return function status */
1610	return status;
1611	}
1612
1613	/**
1614	* @brief Encryption in DMA mode.
1615	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1616	* the configuration information for CRYP module
1617	* @param Input: Pointer to the input buffer (plaintext)
1618	* @param Size: Length of the plaintext buffer in word.
1619	* @param Output: Pointer to the output buffer(ciphertext)
1620	* @retval HAL status
1621	*/
1622	HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef hcryp, uint32_t Input, uint16_t Size, uint32_t *Output)
1623	{
1624	uint32_t algo;
1625	HAL_StatusTypeDef status = HAL_OK;
1626	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
1627
1628	if (hcryp->State == HAL_CRYP_STATE_READY)
1629	{
1630	/* Change state Busy */
1631	hcryp->State = HAL_CRYP_STATE_BUSY;
1632
1633	/* Process locked */
1634	__HAL_LOCK(hcryp);
1635
1636	/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1637	hcryp->CrypInCount = 0U;
1638	hcryp->CrypOutCount = 0U;
1639	hcryp->pCrypInBuffPtr = Input;
1640	hcryp->pCrypOutBuffPtr = Output;
1641
1642	/* Calculate Size parameter in Byte*/
1643	if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1644	{
1645	hcryp->Size = Size * 4U;
1646	}
1647	else
1648	{
1649	hcryp->Size = Size;
1650	}
1651
1652	#if defined (CRYP)
1653
1654	/* Set encryption operating mode*/
1655	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1656
1657	/* algo get algorithm selected */
1658	algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1659
1660	switch (algo)
1661	{
1662	case CRYP_DES_ECB:
1663	case CRYP_DES_CBC:
1664	case CRYP_TDES_ECB:
1665	case CRYP_TDES_CBC:
1666
1667	/Set Key /
1668	hcryp->Instance->K1LR = (uint32_t )(hcryp->Init.pKey);
1669	hcryp->Instance->K1RR = (uint32_t )(hcryp->Init.pKey + 1);
1670	if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1671	{
1672	hcryp->Instance->K2LR = (uint32_t )(hcryp->Init.pKey + 2);
1673	hcryp->Instance->K2RR = (uint32_t )(hcryp->Init.pKey + 3);
1674	hcryp->Instance->K3LR = (uint32_t )(hcryp->Init.pKey + 4);
1675	hcryp->Instance->K3RR = (uint32_t )(hcryp->Init.pKey + 5);
1676	}
1677
1678	/* Set the Initialization Vector*/
1679	if ((hcryp->Init.Algorithm == CRYP_DES_CBC) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1680	{
1681	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
1682	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
1683	}
1684
1685	/* Flush FIFO */
1686	HAL_CRYP_FIFO_FLUSH(hcryp);
1687
1688	/* Set the phase */
1689	hcryp->Phase = CRYP_PHASE_PROCESS;
1690
1691	/* Start DMA process transfer for DES/TDES */
1692	CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1693	(uint32_t)(hcryp->pCrypOutBuffPtr));
1694	break;
1695
1696	case CRYP_AES_ECB:
1697	case CRYP_AES_CBC:
1698	case CRYP_AES_CTR:
1699
1700	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1701	{
1702	if (hcryp->KeyIVConfig == 1U)
1703	{
1704	/* If the Key and IV configuration has to be done only once
1705	and if it has already been done, skip it */
1706	DoKeyIVConfig = 0U;
1707	}
1708	else
1709	{
1710	/* If the Key and IV configuration has to be done only once
1711	and if it has not been done already, do it and set KeyIVConfig
1712	to keep track it won't have to be done again next time */
1713	hcryp->KeyIVConfig = 1U;
1714	}
1715	}
1716
1717	if (DoKeyIVConfig == 1U)
1718	{
1719	/* Set the Key*/
1720	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1721
1722	/* Set the Initialization Vector*/
1723	if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1724	{
1725	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
1726	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1U);
1727	hcryp->Instance->IV1LR = (uint32_t )(hcryp->Init.pInitVect + 2U);
1728	hcryp->Instance->IV1RR = (uint32_t )(hcryp->Init.pInitVect + 3U);
1729	}
1730	} /* if (DoKeyIVConfig == 1U) */
1731
1732	/* Set the phase */
1733	hcryp->Phase = CRYP_PHASE_PROCESS;
1734
1735	/* Start DMA process transfer for AES */
1736	CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1737	(uint32_t)(hcryp->pCrypOutBuffPtr));
1738	break;
1739	#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1740	case CRYP_AES_GCM:
1741	/* AES GCM encryption */
1742	status = CRYP_AESGCM_Process_DMA(hcryp) ;
1743	break;
1744
1745	case CRYP_AES_CCM:
1746	/* AES CCM encryption */
1747	status = CRYP_AESCCM_Process_DMA(hcryp);
1748	break;
1749	#endif /* GCM CCM defined*/
1750	default:
1751	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1752	/* Change the CRYP peripheral state */
1753	hcryp->State = HAL_CRYP_STATE_READY;
1754	/* Process unlocked */
1755	__HAL_UNLOCK(hcryp);
1756	status = HAL_ERROR;
1757	break;
1758	}
1759
1760	#else /AES/
1761	/* Set encryption operating mode*/
1762	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1763
1764	/* algo get algorithm selected */
1765	algo = hcryp->Instance->CR & AES_CR_CHMOD;
1766
1767	switch (algo)
1768	{
1769
1770	case CRYP_AES_ECB:
1771	case CRYP_AES_CBC:
1772	case CRYP_AES_CTR:
1773
1774	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1775	{
1776	if (hcryp->KeyIVConfig == 1U)
1777	{
1778	/* If the Key and IV configuration has to be done only once
1779	and if it has already been done, skip it */
1780	DoKeyIVConfig = 0U;
1781	}
1782	else
1783	{
1784	/* If the Key and IV configuration has to be done only once
1785	and if it has not been done already, do it and set KeyIVConfig
1786	to keep track it won't have to be done again next time */
1787	hcryp->KeyIVConfig = 1U;
1788	}
1789	}
1790
1791	if (DoKeyIVConfig == 1U)
1792	{
1793	/* Set the Key*/
1794	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1795
1796	/* Set the Initialization Vector*/
1797	if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1798	{
1799	hcryp->Instance->IVR3 = (uint32_t )(hcryp->Init.pInitVect);
1800	hcryp->Instance->IVR2 = (uint32_t )(hcryp->Init.pInitVect + 1);
1801	hcryp->Instance->IVR1 = (uint32_t )(hcryp->Init.pInitVect + 2);
1802	hcryp->Instance->IVR0 = (uint32_t )(hcryp->Init.pInitVect + 3);
1803	}
1804	} /* if (DoKeyIVConfig == 1U) */
1805	/* Set the phase */
1806	hcryp->Phase = CRYP_PHASE_PROCESS;
1807
1808	/* Start DMA process transfer for AES */
1809	CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1810	break;
1811
1812	case CRYP_AES_GCM_GMAC:
1813	/* AES GCM encryption */
1814	status = CRYP_AESGCM_Process_DMA(hcryp) ;
1815	break;
1816
1817	case CRYP_AES_CCM:
1818	/* AES CCM encryption */
1819	status = CRYP_AESCCM_Process_DMA(hcryp);
1820	break;
1821
1822	default:
1823	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1824	/* Change the CRYP peripheral state */
1825	hcryp->State = HAL_CRYP_STATE_READY;
1826	/* Process unlocked */
1827	__HAL_UNLOCK(hcryp);
1828	status = HAL_ERROR;
1829	break;
1830	}
1831	#endif /* End AES or CRYP */
1832
1833	}
1834	else
1835	{
1836	/* Busy error code field */
1837	hcryp->ErrorCode \|= HAL_CRYP_ERROR_BUSY;
1838	status = HAL_ERROR;
1839	}
1840
1841	/* Return function status */
1842	return status;
1843	}
1844
1845	/**
1846	* @brief Decryption in DMA mode.
1847	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1848	* the configuration information for CRYP module
1849	* @param Input: Pointer to the input buffer (ciphertext )
1850	* @param Size: Length of the plaintext buffer in word
1851	* @param Output: Pointer to the output buffer(plaintext)
1852	* @retval HAL status
1853	*/
1854	HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef hcryp, uint32_t Input, uint16_t Size, uint32_t *Output)
1855	{
1856	uint32_t algo;
1857	HAL_StatusTypeDef status = HAL_OK;
1858
1859	if (hcryp->State == HAL_CRYP_STATE_READY)
1860	{
1861
1862	/* Change state Busy */
1863	hcryp->State = HAL_CRYP_STATE_BUSY;
1864
1865	/* Process locked */
1866	__HAL_LOCK(hcryp);
1867
1868	/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1869	hcryp->CrypInCount = 0U;
1870	hcryp->CrypOutCount = 0U;
1871	hcryp->pCrypInBuffPtr = Input;
1872	hcryp->pCrypOutBuffPtr = Output;
1873
1874	/* Calculate Size parameter in Byte*/
1875	if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1876	{
1877	hcryp->Size = Size * 4U;
1878	}
1879	else
1880	{
1881	hcryp->Size = Size;
1882	}
1883
1884	#if defined (CRYP)
1885
1886	/* Set decryption operating mode*/
1887	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1888
1889	/* algo get algorithm selected */
1890	algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1891
1892	switch (algo)
1893	{
1894	case CRYP_DES_ECB:
1895	case CRYP_DES_CBC:
1896	case CRYP_TDES_ECB:
1897	case CRYP_TDES_CBC:
1898
1899	/Set Key /
1900	hcryp->Instance->K1LR = (uint32_t )(hcryp->Init.pKey);
1901	hcryp->Instance->K1RR = (uint32_t )(hcryp->Init.pKey + 1);
1902	if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1903	{
1904	hcryp->Instance->K2LR = (uint32_t )(hcryp->Init.pKey + 2);
1905	hcryp->Instance->K2RR = (uint32_t )(hcryp->Init.pKey + 3);
1906	hcryp->Instance->K3LR = (uint32_t )(hcryp->Init.pKey + 4);
1907	hcryp->Instance->K3RR = (uint32_t )(hcryp->Init.pKey + 5);
1908	}
1909
1910	/* Set the Initialization Vector*/
1911	if ((hcryp->Init.Algorithm == CRYP_DES_CBC) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1912	{
1913	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
1914	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
1915	}
1916
1917	/* Flush FIFO */
1918	HAL_CRYP_FIFO_FLUSH(hcryp);
1919
1920	/* Set the phase */
1921	hcryp->Phase = CRYP_PHASE_PROCESS;
1922
1923	/* Start DMA process transfer for DES/TDES */
1924	CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1925	(uint32_t)(hcryp->pCrypOutBuffPtr));
1926	break;
1927
1928	case CRYP_AES_ECB:
1929	case CRYP_AES_CBC:
1930	case CRYP_AES_CTR:
1931
1932	/* AES decryption */
1933	status = CRYP_AES_Decrypt_DMA(hcryp);
1934	break;
1935	#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1936	case CRYP_AES_GCM:
1937	/* AES GCM decryption */
1938	status = CRYP_AESGCM_Process_DMA(hcryp) ;
1939	break;
1940
1941	case CRYP_AES_CCM:
1942	/* AES CCM decryption */
1943	status = CRYP_AESCCM_Process_DMA(hcryp);
1944	break;
1945	#endif /* GCM CCM defined*/
1946	default:
1947	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1948	/* Change the CRYP peripheral state */
1949	hcryp->State = HAL_CRYP_STATE_READY;
1950	/* Process unlocked */
1951	__HAL_UNLOCK(hcryp);
1952	status = HAL_ERROR;
1953	break;
1954	}
1955
1956	#else /AES/
1957
1958	/* Set decryption operating mode*/
1959	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1960
1961	/* algo get algorithm selected */
1962	algo = hcryp->Instance->CR & AES_CR_CHMOD;
1963
1964	switch (algo)
1965	{
1966
1967	case CRYP_AES_ECB:
1968	case CRYP_AES_CBC:
1969	case CRYP_AES_CTR:
1970
1971	/* AES decryption */
1972	status = CRYP_AES_Decrypt_DMA(hcryp);
1973	break;
1974
1975	case CRYP_AES_GCM_GMAC:
1976	/* AES GCM decryption */
1977	status = CRYP_AESGCM_Process_DMA(hcryp) ;
1978	break;
1979
1980	case CRYP_AES_CCM:
1981	/* AES CCM decryption */
1982	status = CRYP_AESCCM_Process_DMA(hcryp);
1983	break;
1984
1985	default:
1986	hcryp->ErrorCode \|= HAL_CRYP_ERROR_NOT_SUPPORTED;
1987	/* Change the CRYP peripheral state */
1988	hcryp->State = HAL_CRYP_STATE_READY;
1989	/* Process unlocked */
1990	__HAL_UNLOCK(hcryp);
1991	status = HAL_ERROR;
1992	break;
1993	}
1994	#endif /* End AES or CRYP */
1995	}
1996	else
1997	{
1998	/* Busy error code field */
1999	hcryp->ErrorCode \|= HAL_CRYP_ERROR_BUSY;
2000	status = HAL_ERROR;
2001	}
2002
2003	/* Return function status */
2004	return status;
2005	}
2006
2007	/**
2008	* @}
2009	*/
2010
2011	/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
2012	* @brief CRYP IRQ handler.
2013	*
2014	@verbatim
2015	==============================================================================
2016	##### CRYP IRQ handler management #####
2017	==============================================================================
2018	[..] This section provides CRYP IRQ handler and callback functions.
2019	(+) HAL_CRYP_IRQHandler CRYP interrupt request
2020	(+) HAL_CRYP_InCpltCallback input data transfer complete callback
2021	(+) HAL_CRYP_OutCpltCallback output data transfer complete callback
2022	(+) HAL_CRYP_ErrorCallback CRYP error callback
2023	(+) HAL_CRYP_GetState return the CRYP state
2024	(+) HAL_CRYP_GetError return the CRYP error code
2025	@endverbatim
2026	* @{
2027	*/
2028
2029	/**
2030	* @brief This function handles cryptographic interrupt request.
2031	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2032	* the configuration information for CRYP module
2033	* @retval None
2034	*/
2035	void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
2036	{
2037
2038	#if defined (CRYP)
2039
2040	uint32_t itstatus = hcryp->Instance->MISR;
2041
2042	if ((itstatus & (CRYP_IT_INI \| CRYP_IT_OUTI)) != 0U)
2043	{
2044	if ((hcryp->Init.Algorithm == CRYP_DES_ECB) \|\| (hcryp->Init.Algorithm == CRYP_DES_CBC)
2045	\|\| (hcryp->Init.Algorithm == CRYP_TDES_ECB) \|\| (hcryp->Init.Algorithm == CRYP_TDES_CBC))
2046	{
2047	CRYP_TDES_IT(hcryp); /* DES or TDES*/
2048	}
2049	else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) \|\| (hcryp->Init.Algorithm == CRYP_AES_CBC)
2050	\|\| (hcryp->Init.Algorithm == CRYP_AES_CTR))
2051	{
2052	CRYP_AES_IT(hcryp); /AES/
2053	}
2054	#if defined (CRYP_CR_ALGOMODE_AES_GCM)
2055	else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) \|\| (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM))
2056	{
2057	/* if header phase */
2058	if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2059	{
2060	CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2061	}
2062	else /* if payload phase */
2063	{
2064	CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2065	}
2066	}
2067	#endif /* GCM CCM defined*/
2068	else
2069	{
2070	/* Nothing to do */
2071	}
2072	}
2073
2074	#else /AES/
2075	if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
2076	{
2077	if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
2078	{
2079
2080	/* Clear computation complete flag */
2081	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2082
2083	if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
2084	{
2085
2086	/* if header phase */
2087	if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2088	{
2089	CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2090	}
2091	else /* if payload phase */
2092	{
2093	CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2094	}
2095	}
2096	else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
2097	{
2098	/* if header phase */
2099	if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
2100	{
2101	CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2102	}
2103	else /* if payload phase */
2104	{
2105	CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2106	}
2107	}
2108	else /* AES Algorithm ECB,CBC or CTR*/
2109	{
2110	CRYP_AES_IT(hcryp);
2111	}
2112	}
2113	}
2114	/* Check if error occurred */
2115	if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET)
2116	{
2117	/* If write Error occurred */
2118	if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET)
2119	{
2120	hcryp->ErrorCode \|= HAL_CRYP_ERROR_WRITE;
2121	}
2122	/* If read Error occurred */
2123	if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET)
2124	{
2125	hcryp->ErrorCode \|= HAL_CRYP_ERROR_READ;
2126	}
2127	}
2128	#endif /* End AES or CRYP */
2129	}
2130
2131	/**
2132	* @brief Return the CRYP error code.
2133	* @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains
2134	* the configuration information for the CRYP IP
2135	* @retval CRYP error code
2136	*/
2137	uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
2138	{
2139	return hcryp->ErrorCode;
2140	}
2141
2142	/**
2143	* @brief Returns the CRYP state.
2144	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2145	* the configuration information for CRYP module.
2146	* @retval HAL state
2147	*/
2148	HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
2149	{
2150	return hcryp->State;
2151	}
2152
2153	/**
2154	* @brief Input FIFO transfer completed callback.
2155	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2156	* the configuration information for CRYP module.
2157	* @retval None
2158	*/
2159	__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
2160	{
2161	/* Prevent unused argument(s) compilation warning */
2162	UNUSED(hcryp);
2163
2164	/* NOTE : This function should not be modified, when the callback is needed,
2165	the HAL_CRYP_InCpltCallback can be implemented in the user file
2166	*/
2167	}
2168
2169	/**
2170	* @brief Output FIFO transfer completed callback.
2171	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2172	* the configuration information for CRYP module.
2173	* @retval None
2174	*/
2175	__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
2176	{
2177	/* Prevent unused argument(s) compilation warning */
2178	UNUSED(hcryp);
2179
2180	/* NOTE : This function should not be modified, when the callback is needed,
2181	the HAL_CRYP_OutCpltCallback can be implemented in the user file
2182	*/
2183	}
2184
2185	/**
2186	* @brief CRYP error callback.
2187	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2188	* the configuration information for CRYP module.
2189	* @retval None
2190	*/
2191	__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
2192	{
2193	/* Prevent unused argument(s) compilation warning */
2194	UNUSED(hcryp);
2195
2196	/* NOTE : This function Should not be modified, when the callback is needed,
2197	the HAL_CRYP_ErrorCallback could be implemented in the user file
2198	*/
2199	}
2200	/**
2201	* @}
2202	*/
2203
2204	/* Private functions ---------------------------------------------------------*/
2205	/** @addtogroup CRYP_Private_Functions
2206	* @{
2207	*/
2208
2209	#if defined (CRYP)
2210
2211	/**
2212	* @brief Encryption in ECB/CBC Algorithm with DES/TDES standard.
2213	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2214	* the configuration information for CRYP module
2215	* @param Timeout: specify Timeout value
2216	* @retval HAL status
2217	*/
2218	static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2219	{
2220	uint32_t temp[2]; /* Temporary CrypOutBuff */
2221	uint16_t incount; /* Temporary CrypInCount Value */
2222	uint16_t outcount; /* Temporary CrypOutCount Value */
2223	uint32_t i;
2224
2225	/* Enable CRYP */
2226	__HAL_CRYP_ENABLE(hcryp);
2227	/Temporary CrypOutCount Value/
2228	outcount = hcryp->CrypOutCount;
2229
2230	/Start processing/
2231	while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2232	{
2233	/* Temporary CrypInCount Value */
2234	incount = hcryp->CrypInCount;
2235	/* Write plain data and get cipher data */
2236	if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
2237	{
2238	/* Write the input block in the IN FIFO */
2239	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2240	hcryp->CrypInCount++;
2241	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2242	hcryp->CrypInCount++;
2243	}
2244
2245	/* Wait for OFNE flag to be raised */
2246	if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
2247	{
2248	/* Disable the CRYP peripheral clock */
2249	__HAL_CRYP_DISABLE(hcryp);
2250
2251	/* Change state & errorCode*/
2252	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
2253	hcryp->State = HAL_CRYP_STATE_READY;
2254
2255	/* Process unlocked */
2256	__HAL_UNLOCK(hcryp);
2257	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2258	/Call registered error callback/
2259	hcryp->ErrorCallback(hcryp);
2260	#else
2261	/Call legacy weak error callback/
2262	HAL_CRYP_ErrorCallback(hcryp);
2263	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2264	}
2265
2266	/Temporary CrypOutCount Value/
2267	outcount = hcryp->CrypOutCount;
2268
2269	if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
2270	{
2271	/* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2272	for (i = 0U; i < 2U; i++)
2273	{
2274	temp[i] = hcryp->Instance->DOUT;
2275	}
2276	i = 0U;
2277	while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2278	{
2279	(uint32_t )(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2280	hcryp->CrypOutCount++;
2281	i++;
2282	}
2283	}
2284	/Temporary CrypOutCount Value/
2285	outcount = hcryp->CrypOutCount;
2286	}
2287	/* Disable CRYP */
2288	__HAL_CRYP_DISABLE(hcryp);
2289	/* Change the CRYP state */
2290	hcryp->State = HAL_CRYP_STATE_READY;
2291
2292	/* Return function status */
2293	return HAL_OK;
2294	}
2295
2296	/**
2297	* @brief CRYP block input/output data handling under interruption with DES/TDES standard.
2298	* @note The function is called under interruption only, once
2299	* interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
2300	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2301	* the configuration information for CRYP module.
2302	* @retval none
2303	*/
2304	static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
2305	{
2306	uint32_t temp[2]; /* Temporary CrypOutBuff */
2307	uint32_t i;
2308
2309	if (hcryp->State == HAL_CRYP_STATE_BUSY)
2310	{
2311	if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U)
2312	{
2313	if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
2314	{
2315	/* Write input block in the IN FIFO */
2316	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2317	hcryp->CrypInCount++;
2318	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2319	hcryp->CrypInCount++;
2320
2321	if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
2322	{
2323	/* Disable interruption */
2324	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
2325	/* Call the input data transfer complete callback */
2326	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
2327	/Call registered Input complete callback/
2328	hcryp->InCpltCallback(hcryp);
2329	#else
2330	/Call legacy weak Input complete callback/
2331	HAL_CRYP_InCpltCallback(hcryp);
2332	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2333	}
2334	}
2335	}
2336	if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)
2337	{
2338	if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
2339	{
2340	/* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2341	for (i = 0U; i < 2U; i++)
2342	{
2343	temp[i] = hcryp->Instance->DOUT;
2344	}
2345	i = 0U;
2346	while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2347	{
2348	(uint32_t )(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2349	hcryp->CrypOutCount++;
2350	i++;
2351	}
2352	if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
2353	{
2354	/* Disable interruption */
2355	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
2356
2357	/* Disable CRYP */
2358	__HAL_CRYP_DISABLE(hcryp);
2359
2360	/* Process unlocked */
2361	__HAL_UNLOCK(hcryp);
2362
2363	/* Change the CRYP state */
2364	hcryp->State = HAL_CRYP_STATE_READY;
2365	/* Call output transfer complete callback */
2366	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2367	/Call registered Output complete callback/
2368	hcryp->OutCpltCallback(hcryp);
2369	#else
2370	/Call legacy weak Output complete callback/
2371	HAL_CRYP_OutCpltCallback(hcryp);
2372	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2373	}
2374	}
2375	}
2376	}
2377	else
2378	{
2379	/* Process unlocked */
2380	__HAL_UNLOCK(hcryp);
2381	/* Busy error code field */
2382	hcryp->ErrorCode \|= HAL_CRYP_ERROR_BUSY;
2383	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2384	/Call registered error callback/
2385	hcryp->ErrorCallback(hcryp);
2386	#else
2387	/Call legacy weak error callback/
2388	HAL_CRYP_ErrorCallback(hcryp);
2389	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2390	}
2391	}
2392
2393	#endif /* CRYP */
2394
2395	/**
2396	* @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
2397	* @param hcryp: pointer to a CRYP_HandleTypeDef structure
2398	* @param Timeout: specify Timeout value
2399	* @retval HAL status
2400	*/
2401	static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2402	{
2403	uint16_t outcount; /* Temporary CrypOutCount Value */
2404	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2405
2406	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2407	{
2408	if (hcryp->KeyIVConfig == 1U)
2409	{
2410	/* If the Key and IV configuration has to be done only once
2411	and if it has already been done, skip it */
2412	DoKeyIVConfig = 0U;
2413	}
2414	else
2415	{
2416	/* If the Key and IV configuration has to be done only once
2417	and if it has not been done already, do it and set KeyIVConfig
2418	to keep track it won't have to be done again next time */
2419	hcryp->KeyIVConfig = 1U;
2420	}
2421	}
2422
2423	if (DoKeyIVConfig == 1U)
2424	{
2425
2426	/* Set the Key*/
2427	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2428
2429	if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2430	{
2431	/* Set the Initialization Vector*/
2432	#if defined (AES)
2433	hcryp->Instance->IVR3 = (uint32_t )(hcryp->Init.pInitVect);
2434	hcryp->Instance->IVR2 = (uint32_t )(hcryp->Init.pInitVect + 1);
2435	hcryp->Instance->IVR1 = (uint32_t )(hcryp->Init.pInitVect + 2);
2436	hcryp->Instance->IVR0 = (uint32_t )(hcryp->Init.pInitVect + 3);
2437	#else /* CRYP */
2438	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
2439	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
2440	hcryp->Instance->IV1LR = (uint32_t )(hcryp->Init.pInitVect + 2);
2441	hcryp->Instance->IV1RR = (uint32_t )(hcryp->Init.pInitVect + 3);
2442	#endif /* End AES or CRYP */
2443	}
2444	} /* if (DoKeyIVConfig == 1U) */
2445
2446	/* Set the phase */
2447	hcryp->Phase = CRYP_PHASE_PROCESS;
2448
2449	/* Enable CRYP */
2450	__HAL_CRYP_ENABLE(hcryp);
2451
2452	/Temporary CrypOutCount Value/
2453	outcount = hcryp->CrypOutCount;
2454
2455	while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2456	{
2457	/* Write plain Ddta and get cipher data */
2458	CRYP_AES_ProcessData(hcryp, Timeout);
2459	/Temporary CrypOutCount Value/
2460	outcount = hcryp->CrypOutCount;
2461	}
2462
2463	/* Disable CRYP */
2464	__HAL_CRYP_DISABLE(hcryp);
2465
2466	/* Change the CRYP state */
2467	hcryp->State = HAL_CRYP_STATE_READY;
2468
2469	/* Return function status */
2470	return HAL_OK;
2471	}
2472
2473	/**
2474	* @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2475	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2476	* the configuration information for CRYP module
2477	* @retval HAL status
2478	*/
2479	static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
2480	{
2481	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2482
2483	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2484	{
2485	if (hcryp->KeyIVConfig == 1U)
2486	{
2487	/* If the Key and IV configuration has to be done only once
2488	and if it has already been done, skip it */
2489	DoKeyIVConfig = 0U;
2490	}
2491	else
2492	{
2493	/* If the Key and IV configuration has to be done only once
2494	and if it has not been done already, do it and set KeyIVConfig
2495	to keep track it won't have to be done again next time */
2496	hcryp->KeyIVConfig = 1U;
2497	}
2498	}
2499
2500	if (DoKeyIVConfig == 1U)
2501	{
2502	/* Set the Key*/
2503	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2504
2505	if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2506	{
2507	/* Set the Initialization Vector*/
2508	#if defined (AES)
2509	hcryp->Instance->IVR3 = (uint32_t )(hcryp->Init.pInitVect);
2510	hcryp->Instance->IVR2 = (uint32_t )(hcryp->Init.pInitVect + 1);
2511	hcryp->Instance->IVR1 = (uint32_t )(hcryp->Init.pInitVect + 2);
2512	hcryp->Instance->IVR0 = (uint32_t )(hcryp->Init.pInitVect + 3);
2513
2514	#else /* CRYP */
2515	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
2516	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
2517	hcryp->Instance->IV1LR = (uint32_t )(hcryp->Init.pInitVect + 2);
2518	hcryp->Instance->IV1RR = (uint32_t )(hcryp->Init.pInitVect + 3);
2519	#endif /* End AES or CRYP */
2520	}
2521	} /* if (DoKeyIVConfig == 1U) */
2522
2523	/* Set the phase */
2524	hcryp->Phase = CRYP_PHASE_PROCESS;
2525
2526	if (hcryp->Size != 0U)
2527	{
2528	#if defined (AES)
2529
2530	/* Enable computation complete flag and error interrupts */
2531	__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE \| CRYP_IT_ERRIE);
2532
2533	/* Enable CRYP */
2534	__HAL_CRYP_ENABLE(hcryp);
2535
2536	/* Write the input block in the IN FIFO */
2537	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2538	hcryp->CrypInCount++;
2539	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2540	hcryp->CrypInCount++;
2541	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2542	hcryp->CrypInCount++;
2543	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2544	hcryp->CrypInCount++;
2545
2546	#else /* CRYP */
2547
2548	/* Enable interrupts */
2549	__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI \| CRYP_IT_OUTI);
2550
2551	/* Enable CRYP */
2552	__HAL_CRYP_ENABLE(hcryp);
2553
2554	#endif /* End AES or CRYP */
2555	}
2556	else
2557	{
2558	/* Change the CRYP state */
2559	hcryp->State = HAL_CRYP_STATE_READY;
2560
2561	/* Process unlocked */
2562	__HAL_UNLOCK(hcryp);
2563	}
2564
2565	/* Return function status */
2566	return HAL_OK;
2567	}
2568
2569	/**
2570	* @brief Decryption in ECB/CBC & CTR mode with AES Standard
2571	* @param hcryp: pointer to a CRYP_HandleTypeDef structure
2572	* @param Timeout: Specify Timeout value
2573	* @retval HAL status
2574	*/
2575	static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2576	{
2577	uint16_t outcount; /* Temporary CrypOutCount Value */
2578	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2579
2580	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2581	{
2582	if (hcryp->KeyIVConfig == 1U)
2583	{
2584	/* If the Key and IV configuration has to be done only once
2585	and if it has already been done, skip it */
2586	DoKeyIVConfig = 0U;
2587	}
2588	else
2589	{
2590	/* If the Key and IV configuration has to be done only once
2591	and if it has not been done already, do it and set KeyIVConfig
2592	to keep track it won't have to be done again next time */
2593	hcryp->KeyIVConfig = 1U;
2594	}
2595	}
2596
2597	if (DoKeyIVConfig == 1U)
2598	{
2599	/* Key preparation for ECB/CBC */
2600	if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2601	{
2602	#if defined (AES)
2603	if (hcryp->AutoKeyDerivation == DISABLE)/Mode 2 Key preparation/
2604	{
2605	/* Set key preparation for decryption operating mode*/
2606	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2607
2608	/* Set the Key*/
2609	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2610
2611	/* Enable CRYP */
2612	__HAL_CRYP_ENABLE(hcryp);
2613
2614	/* Wait for CCF flag to be raised */
2615	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
2616	{
2617	/* Disable the CRYP peripheral clock */
2618	__HAL_CRYP_DISABLE(hcryp);
2619
2620	/* Change state & error code*/
2621	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
2622	hcryp->State = HAL_CRYP_STATE_READY;
2623
2624	/* Process unlocked */
2625	__HAL_UNLOCK(hcryp);
2626	return HAL_ERROR;
2627	}
2628	/* Clear CCF Flag */
2629	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2630
2631	/* Return to decryption operating mode(Mode 3)*/
2632	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2633	}
2634	else /Mode 4 : decryption & Key preparation/
2635	{
2636	/* Set the Key*/
2637	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2638
2639	/* Set decryption & Key preparation operating mode*/
2640	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2641	}
2642	#else /* CRYP */
2643	/* change ALGOMODE to key preparation for decryption*/
2644	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2645
2646	/* Set the Key*/
2647	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2648
2649	/* Enable CRYP */
2650	__HAL_CRYP_ENABLE(hcryp);
2651
2652	/* Wait for BUSY flag to be raised */
2653	if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2654	{
2655	/* Disable the CRYP peripheral clock */
2656	__HAL_CRYP_DISABLE(hcryp);
2657
2658	/* Change state */
2659	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
2660	hcryp->State = HAL_CRYP_STATE_READY;
2661
2662	/* Process unlocked */
2663	__HAL_UNLOCK(hcryp);
2664	return HAL_ERROR;
2665	}
2666	/* Turn back to ALGOMODE of the configuration */
2667	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2668
2669	#endif /* End AES or CRYP */
2670	}
2671	else /Algorithm CTR /
2672	{
2673	/* Set the Key*/
2674	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2675	}
2676
2677	/* Set IV */
2678	if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2679	{
2680	/* Set the Initialization Vector*/
2681	#if defined (AES)
2682	hcryp->Instance->IVR3 = (uint32_t )(hcryp->Init.pInitVect);
2683	hcryp->Instance->IVR2 = (uint32_t )(hcryp->Init.pInitVect + 1);
2684	hcryp->Instance->IVR1 = (uint32_t )(hcryp->Init.pInitVect + 2);
2685	hcryp->Instance->IVR0 = (uint32_t )(hcryp->Init.pInitVect + 3);
2686	#else /* CRYP */
2687	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
2688	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
2689	hcryp->Instance->IV1LR = (uint32_t )(hcryp->Init.pInitVect + 2);
2690	hcryp->Instance->IV1RR = (uint32_t )(hcryp->Init.pInitVect + 3);
2691	#endif /* End AES or CRYP */
2692	}
2693	} /* if (DoKeyIVConfig == 1U) */
2694	/* Set the phase */
2695	hcryp->Phase = CRYP_PHASE_PROCESS;
2696
2697	/* Enable CRYP */
2698	__HAL_CRYP_ENABLE(hcryp);
2699
2700	/Temporary CrypOutCount Value/
2701	outcount = hcryp->CrypOutCount;
2702
2703	while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2704	{
2705	/* Write plain data and get cipher data */
2706	CRYP_AES_ProcessData(hcryp, Timeout);
2707	/Temporary CrypOutCount Value/
2708	outcount = hcryp->CrypOutCount;
2709	}
2710
2711	/* Disable CRYP */
2712	__HAL_CRYP_DISABLE(hcryp);
2713
2714	/* Change the CRYP state */
2715	hcryp->State = HAL_CRYP_STATE_READY;
2716
2717	/* Return function status */
2718	return HAL_OK;
2719	}
2720	/**
2721	* @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2722	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2723	* the configuration information for CRYP module
2724	* @retval HAL status
2725	*/
2726	static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
2727	{
2728	__IO uint32_t count = 0U;
2729	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2730
2731	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2732	{
2733	if (hcryp->KeyIVConfig == 1U)
2734	{
2735	/* If the Key and IV configuration has to be done only once
2736	and if it has already been done, skip it */
2737	DoKeyIVConfig = 0U;
2738	}
2739	else
2740	{
2741	/* If the Key and IV configuration has to be done only once
2742	and if it has not been done already, do it and set KeyIVConfig
2743	to keep track it won't have to be done again next time */
2744	hcryp->KeyIVConfig = 1U;
2745	}
2746	}
2747
2748	if (DoKeyIVConfig == 1U)
2749	{
2750	/* Key preparation for ECB/CBC */
2751	if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2752	{
2753	#if defined (AES)
2754	if (hcryp->AutoKeyDerivation == DISABLE)/Mode 2 Key preparation/
2755	{
2756	/* Set key preparation for decryption operating mode*/
2757	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2758
2759	/* Set the Key*/
2760	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2761
2762	/* Enable CRYP */
2763	__HAL_CRYP_ENABLE(hcryp);
2764
2765	/* Wait for CCF flag to be raised */
2766	count = CRYP_TIMEOUT_KEYPREPARATION;
2767	do
2768	{
2769	count-- ;
2770	if (count == 0U)
2771	{
2772	/* Disable the CRYP peripheral clock */
2773	__HAL_CRYP_DISABLE(hcryp);
2774
2775	/* Change state */
2776	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
2777	hcryp->State = HAL_CRYP_STATE_READY;
2778
2779	/* Process unlocked */
2780	__HAL_UNLOCK(hcryp);
2781	return HAL_ERROR;
2782	}
2783	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2784
2785	/* Clear CCF Flag */
2786	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2787
2788	/* Return to decryption operating mode(Mode 3)*/
2789	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2790	}
2791	else /Mode 4 : decryption & key preparation/
2792	{
2793	/* Set the Key*/
2794	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2795
2796	/* Set decryption & key preparation operating mode*/
2797	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2798	}
2799	#else /* CRYP */
2800
2801	/* change ALGOMODE to key preparation for decryption*/
2802	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2803
2804	/* Set the Key*/
2805	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2806
2807	/* Enable CRYP */
2808	__HAL_CRYP_ENABLE(hcryp);
2809
2810	/* Wait for BUSY flag to be raised */
2811	count = CRYP_TIMEOUT_KEYPREPARATION;
2812	do
2813	{
2814	count-- ;
2815	if (count == 0U)
2816	{
2817	/* Change state */
2818	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
2819	hcryp->State = HAL_CRYP_STATE_READY;
2820
2821	/* Process unlocked */
2822	__HAL_UNLOCK(hcryp);
2823	return HAL_ERROR;
2824	}
2825	} while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
2826
2827	/* Turn back to ALGOMODE of the configuration */
2828	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2829
2830	#endif /* End AES or CRYP */
2831	}
2832
2833	else /Algorithm CTR /
2834	{
2835	/* Set the Key*/
2836	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2837	}
2838
2839	/* Set IV */
2840	if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2841	{
2842	/* Set the Initialization Vector*/
2843	#if defined (AES)
2844	hcryp->Instance->IVR3 = (uint32_t )(hcryp->Init.pInitVect);
2845	hcryp->Instance->IVR2 = (uint32_t )(hcryp->Init.pInitVect + 1);
2846	hcryp->Instance->IVR1 = (uint32_t )(hcryp->Init.pInitVect + 2);
2847	hcryp->Instance->IVR0 = (uint32_t )(hcryp->Init.pInitVect + 3);
2848	#else /* CRYP */
2849	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
2850	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
2851	hcryp->Instance->IV1LR = (uint32_t )(hcryp->Init.pInitVect + 2);
2852	hcryp->Instance->IV1RR = (uint32_t )(hcryp->Init.pInitVect + 3);
2853	#endif /* End AES or CRYP */
2854	}
2855	} /* if (DoKeyIVConfig == 1U) */
2856
2857	/* Set the phase */
2858	hcryp->Phase = CRYP_PHASE_PROCESS;
2859	if (hcryp->Size != 0U)
2860	{
2861
2862	#if defined (AES)
2863
2864	/* Enable computation complete flag and error interrupts */
2865	__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE \| CRYP_IT_ERRIE);
2866
2867	/* Enable CRYP */
2868	__HAL_CRYP_ENABLE(hcryp);
2869
2870	/* Write the input block in the IN FIFO */
2871	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2872	hcryp->CrypInCount++;
2873	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2874	hcryp->CrypInCount++;
2875	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2876	hcryp->CrypInCount++;
2877	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2878	hcryp->CrypInCount++;
2879
2880	#else /* CRYP */
2881
2882	/* Enable interrupts */
2883	__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI \| CRYP_IT_OUTI);
2884
2885	/* Enable CRYP */
2886	__HAL_CRYP_ENABLE(hcryp);
2887
2888	#endif /* End AES or CRYP */
2889	}
2890	else
2891	{
2892	/* Process locked */
2893	__HAL_UNLOCK(hcryp);
2894
2895	/* Change the CRYP state */
2896	hcryp->State = HAL_CRYP_STATE_READY;
2897	}
2898
2899	/* Return function status */
2900	return HAL_OK;
2901	}
2902	/**
2903	* @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
2904	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2905	* the configuration information for CRYP module
2906	* @retval HAL status
2907	*/
2908	static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
2909	{
2910	__IO uint32_t count = 0U;
2911	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2912
2913	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2914	{
2915	if (hcryp->KeyIVConfig == 1U)
2916	{
2917	/* If the Key and IV configuration has to be done only once
2918	and if it has already been done, skip it */
2919	DoKeyIVConfig = 0U;
2920	}
2921	else
2922	{
2923	/* If the Key and IV configuration has to be done only once
2924	and if it has not been done already, do it and set KeyIVConfig
2925	to keep track it won't have to be done again next time */
2926	hcryp->KeyIVConfig = 1U;
2927	}
2928	}
2929	if (DoKeyIVConfig == 1U)
2930	{
2931	/* Key preparation for ECB/CBC */
2932	if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2933	{
2934	#if defined (AES)
2935	if (hcryp->AutoKeyDerivation == DISABLE)/Mode 2 key preparation/
2936	{
2937	/* Set key preparation for decryption operating mode*/
2938	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2939
2940	/* Set the Key*/
2941	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2942
2943	/* Enable CRYP */
2944	__HAL_CRYP_ENABLE(hcryp);
2945
2946	/* Wait for CCF flag to be raised */
2947	count = CRYP_TIMEOUT_KEYPREPARATION;
2948	do
2949	{
2950	count-- ;
2951	if (count == 0U)
2952	{
2953	/* Disable the CRYP peripheral clock */
2954	__HAL_CRYP_DISABLE(hcryp);
2955
2956	/* Change state */
2957	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
2958	hcryp->State = HAL_CRYP_STATE_READY;
2959
2960	/* Process unlocked */
2961	__HAL_UNLOCK(hcryp);
2962	return HAL_ERROR;
2963	}
2964	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2965
2966	/* Clear CCF Flag */
2967	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2968
2969	/* Return to decryption operating mode(Mode 3)*/
2970	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2971	}
2972	else /Mode 4 : decryption & key preparation/
2973	{
2974	/* Set the Key*/
2975	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2976
2977	/* Set decryption & Key preparation operating mode*/
2978	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2979	}
2980	#else /* CRYP */
2981	/* change ALGOMODE to key preparation for decryption*/
2982	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2983
2984	/* Set the Key*/
2985	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2986
2987	/* Enable CRYP */
2988	__HAL_CRYP_ENABLE(hcryp);
2989
2990	/* Wait for BUSY flag to be raised */
2991	count = CRYP_TIMEOUT_KEYPREPARATION;
2992	do
2993	{
2994	count-- ;
2995	if (count == 0U)
2996	{
2997	/* Disable the CRYP peripheral clock */
2998	__HAL_CRYP_DISABLE(hcryp);
2999
3000	/* Change state */
3001	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
3002	hcryp->State = HAL_CRYP_STATE_READY;
3003
3004	/* Process unlocked */
3005	__HAL_UNLOCK(hcryp);
3006	return HAL_ERROR;
3007	}
3008	} while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
3009
3010	/* Turn back to ALGOMODE of the configuration */
3011	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
3012
3013	#endif /* End AES or CRYP */
3014	}
3015	else /Algorithm CTR /
3016	{
3017	/* Set the Key*/
3018	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3019	}
3020
3021	if (hcryp->Init.Algorithm != CRYP_AES_ECB)
3022	{
3023	/* Set the Initialization Vector*/
3024	#if defined (AES)
3025	hcryp->Instance->IVR3 = (uint32_t )(hcryp->Init.pInitVect);
3026	hcryp->Instance->IVR2 = (uint32_t )(hcryp->Init.pInitVect + 1);
3027	hcryp->Instance->IVR1 = (uint32_t )(hcryp->Init.pInitVect + 2);
3028	hcryp->Instance->IVR0 = (uint32_t )(hcryp->Init.pInitVect + 3);
3029	#else /* CRYP */
3030	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
3031	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
3032	hcryp->Instance->IV1LR = (uint32_t )(hcryp->Init.pInitVect + 2);
3033	hcryp->Instance->IV1RR = (uint32_t )(hcryp->Init.pInitVect + 3);
3034	#endif /* End AES or CRYP */
3035	}
3036	} /* if (DoKeyIVConfig == 1U) */
3037
3038	/* Set the phase */
3039	hcryp->Phase = CRYP_PHASE_PROCESS;
3040
3041	if (hcryp->Size != 0U)
3042	{
3043	/* Set the input and output addresses and start DMA transfer */
3044	CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
3045	}
3046	else
3047	{
3048	/* Process unlocked */
3049	__HAL_UNLOCK(hcryp);
3050
3051	/* Change the CRYP state */
3052	hcryp->State = HAL_CRYP_STATE_READY;
3053	}
3054
3055	/* Return function status */
3056	return HAL_OK;
3057	}
3058
3059
3060	/**
3061	* @brief DMA CRYP input data process complete callback.
3062	* @param hdma: DMA handle
3063	* @retval None
3064	*/
3065	static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
3066	{
3067	CRYP_HandleTypeDef hcryp = (CRYP_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
3068
3069	/* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
3070	in the DMACR register */
3071	#if defined (CRYP)
3072	hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
3073
3074	#else /* AES */
3075	CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
3076
3077	/* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */
3078	if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3079	{
3080	/* Clear CCF flag */
3081	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3082
3083	/* Change the CRYP state to ready */
3084	hcryp->State = HAL_CRYP_STATE_READY;
3085
3086	/* Process Unlocked */
3087	__HAL_UNLOCK(hcryp);
3088	}
3089	#endif /* End AES or CRYP */
3090
3091	/* Call input data transfer complete callback */
3092	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3093	/Call registered Input complete callback/
3094	hcryp->InCpltCallback(hcryp);
3095	#else
3096	/Call legacy weak Input complete callback/
3097	HAL_CRYP_InCpltCallback(hcryp);
3098	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3099	}
3100
3101	/**
3102	* @brief DMA CRYP output data process complete callback.
3103	* @param hdma: DMA handle
3104	* @retval None
3105	*/
3106	static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
3107	{
3108	CRYP_HandleTypeDef hcryp = (CRYP_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
3109
3110	/* Disable the DMA transfer for output FIFO request by resetting
3111	the DOEN bit in the DMACR register */
3112
3113	#if defined (CRYP)
3114
3115	hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
3116	#if defined (CRYP_CR_ALGOMODE_AES_GCM)
3117	if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
3118	{
3119	/* Disable CRYP (not allowed in GCM)*/
3120	__HAL_CRYP_DISABLE(hcryp);
3121	}
3122
3123	#else /NO GCM CCM /
3124	/* Disable CRYP */
3125	__HAL_CRYP_DISABLE(hcryp);
3126	#endif /* GCM CCM defined*/
3127	#else /* AES */
3128
3129	CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
3130
3131	/* Clear CCF flag */
3132	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3133
3134	if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3135	{
3136	/* Disable CRYP (not allowed in GCM)*/
3137	__HAL_CRYP_DISABLE(hcryp);
3138	}
3139	#endif /* End AES or CRYP */
3140
3141	/* Change the CRYP state to ready */
3142	hcryp->State = HAL_CRYP_STATE_READY;
3143
3144	/* Process unlocked */
3145	__HAL_UNLOCK(hcryp);
3146	/* Call output data transfer complete callback */
3147	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3148	/Call registered Output complete callback/
3149	hcryp->OutCpltCallback(hcryp);
3150	#else
3151	/Call legacy weak Output complete callback/
3152	HAL_CRYP_OutCpltCallback(hcryp);
3153	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3154	}
3155
3156	/**
3157	* @brief DMA CRYP communication error callback.
3158	* @param hdma: DMA handle
3159	* @retval None
3160	*/
3161	static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
3162	{
3163	CRYP_HandleTypeDef hcryp = (CRYP_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
3164
3165	/* Change the CRYP peripheral state */
3166	hcryp->State = HAL_CRYP_STATE_READY;
3167
3168	/* DMA error code field */
3169	hcryp->ErrorCode \|= HAL_CRYP_ERROR_DMA;
3170
3171	#if defined (AES)
3172
3173	/* Clear CCF flag */
3174	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3175
3176	#endif /* AES */
3177
3178	/* Call error callback */
3179	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3180	/Call registered error callback/
3181	hcryp->ErrorCallback(hcryp);
3182	#else
3183	/Call legacy weak error callback/
3184	HAL_CRYP_ErrorCallback(hcryp);
3185	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3186	}
3187
3188	/**
3189	* @brief Set the DMA configuration and start the DMA transfer
3190	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3191	* the configuration information for CRYP module
3192	* @param inputaddr: address of the input buffer
3193	* @param Size: size of the input buffer, must be a multiple of 16.
3194	* @param outputaddr: address of the output buffer
3195	* @retval None
3196	*/
3197	static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
3198	{
3199	/* Set the CRYP DMA transfer complete callback */
3200	hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
3201
3202	/* Set the DMA input error callback */
3203	hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
3204
3205	/* Set the CRYP DMA transfer complete callback */
3206	hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
3207
3208	/* Set the DMA output error callback */
3209	hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
3210
3211	#if defined (CRYP)
3212
3213	/* Enable CRYP */
3214	__HAL_CRYP_ENABLE(hcryp);
3215
3216	/* Enable the input DMA Stream */
3217	if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK)
3218	{
3219	/* DMA error code field */
3220	hcryp->ErrorCode \|= HAL_CRYP_ERROR_DMA;
3221
3222	/* Call error callback */
3223	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3224	/Call registered error callback/
3225	hcryp->ErrorCallback(hcryp);
3226	#else
3227	/Call legacy weak error callback/
3228	HAL_CRYP_ErrorCallback(hcryp);
3229	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3230	}
3231	/* Enable the output DMA Stream */
3232	if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK)
3233	{
3234	/* DMA error code field */
3235	hcryp->ErrorCode \|= HAL_CRYP_ERROR_DMA;
3236
3237	/* Call error callback */
3238	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3239	/Call registered error callback/
3240	hcryp->ErrorCallback(hcryp);
3241	#else
3242	/Call legacy weak error callback/
3243	HAL_CRYP_ErrorCallback(hcryp);
3244	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3245	}
3246	/* Enable In/Out DMA request */
3247	hcryp->Instance->DMACR = CRYP_DMACR_DOEN \| CRYP_DMACR_DIEN;
3248
3249	#else /* AES */
3250
3251	if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3252	&& ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
3253	{
3254	/* Enable CRYP (not allowed in GCM & CCM)*/
3255	__HAL_CRYP_ENABLE(hcryp);
3256	}
3257
3258	/* Enable the DMA input stream */
3259	if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
3260	{
3261	/* DMA error code field */
3262	hcryp->ErrorCode \|= HAL_CRYP_ERROR_DMA;
3263
3264	/* Call error callback */
3265	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3266	/Call registered error callback/
3267	hcryp->ErrorCallback(hcryp);
3268	#else
3269	/Call legacy weak error callback/
3270	HAL_CRYP_ErrorCallback(hcryp);
3271	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3272	}
3273	/* Enable the DMA output stream */
3274	if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK)
3275	{
3276	/* DMA error code field */
3277	hcryp->ErrorCode \|= HAL_CRYP_ERROR_DMA;
3278
3279	/* Call error callback */
3280	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3281	/Call registered error callback/
3282	hcryp->ErrorCallback(hcryp);
3283	#else
3284	/Call legacy weak error callback/
3285	HAL_CRYP_ErrorCallback(hcryp);
3286	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3287	}
3288	/AES2v1.1.1 : CCM authentication : no init phase, only header and final phase /
3289	/* Enable In and Out DMA requests */
3290	if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3291	{
3292	/* Enable only In DMA requests for CCM*/
3293	SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN));
3294	}
3295	else
3296	{
3297	/* Enable In and Out DMA requests */
3298	SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN \| AES_CR_DMAOUTEN));
3299	}
3300	#endif /* End AES or CRYP */
3301	}
3302
3303	/**
3304	* @brief Process Data: Write Input data in polling mode and used in AES functions.
3305	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3306	* the configuration information for CRYP module
3307	* @param Timeout: Specify Timeout value
3308	* @retval None
3309	*/
3310	static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3311	{
3312
3313	uint32_t temp[4]; /* Temporary CrypOutBuff */
3314	uint32_t i;
3315	#if defined (CRYP)
3316	uint16_t incount; /* Temporary CrypInCount Value */
3317	uint16_t outcount; /* Temporary CrypOutCount Value */
3318	#endif
3319
3320	#if defined (CRYP)
3321
3322	/Temporary CrypOutCount Value/
3323	incount = hcryp->CrypInCount;
3324
3325	if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3326	{
3327	/* Write the input block in the IN FIFO */
3328	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3329	hcryp->CrypInCount++;
3330	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3331	hcryp->CrypInCount++;
3332	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3333	hcryp->CrypInCount++;
3334	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3335	hcryp->CrypInCount++;
3336	}
3337
3338	/* Wait for OFNE flag to be raised */
3339	if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
3340	{
3341	/* Disable the CRYP peripheral clock */
3342	__HAL_CRYP_DISABLE(hcryp);
3343
3344	/* Change state & error code*/
3345	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
3346	hcryp->State = HAL_CRYP_STATE_READY;
3347
3348	/* Process unlocked */
3349	__HAL_UNLOCK(hcryp);
3350	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3351	/Call registered error callback/
3352	hcryp->ErrorCallback(hcryp);
3353	#else
3354	/Call legacy weak error callback/
3355	HAL_CRYP_ErrorCallback(hcryp);
3356	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3357	}
3358
3359	/Temporary CrypOutCount Value/
3360	outcount = hcryp->CrypOutCount;
3361
3362	if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3363	{
3364	/* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3365	for (i = 0U; i < 4U; i++)
3366	{
3367	temp[i] = hcryp->Instance->DOUT;
3368	}
3369	i = 0U;
3370	while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3371	{
3372	(uint32_t )(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3373	hcryp->CrypOutCount++;
3374	i++;
3375	}
3376	}
3377
3378	#else /* AES */
3379
3380	/* Write the input block in the IN FIFO */
3381	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3382	hcryp->CrypInCount++;
3383	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3384	hcryp->CrypInCount++;
3385	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3386	hcryp->CrypInCount++;
3387	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3388	hcryp->CrypInCount++;
3389
3390	/* Wait for CCF flag to be raised */
3391	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3392	{
3393	/* Disable the CRYP peripheral clock */
3394	__HAL_CRYP_DISABLE(hcryp);
3395
3396	/* Change state */
3397	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
3398	hcryp->State = HAL_CRYP_STATE_READY;
3399
3400	/* Process unlocked */
3401	__HAL_UNLOCK(hcryp);
3402	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3403	/Call registered error callback/
3404	hcryp->ErrorCallback(hcryp);
3405	#else
3406	/Call legacy weak error callback/
3407	HAL_CRYP_ErrorCallback(hcryp);
3408	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3409	}
3410
3411	/* Clear CCF Flag */
3412	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3413
3414	/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3415	for (i = 0U; i < 4U; i++)
3416	{
3417	temp[i] = hcryp->Instance->DOUTR;
3418	}
3419	i = 0U;
3420	while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3421	{
3422	(uint32_t )(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3423	hcryp->CrypOutCount++;
3424	i++;
3425	}
3426	#endif /* End AES or CRYP */
3427	}
3428
3429	/**
3430	* @brief Handle CRYP block input/output data handling under interruption.
3431	* @note The function is called under interruption only, once
3432	* interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
3433	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3434	* the configuration information for CRYP module.
3435	* @retval HAL status
3436	*/
3437	static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
3438	{
3439	uint32_t temp[4]; /* Temporary CrypOutBuff */
3440	uint32_t i;
3441	#if defined (CRYP)
3442	uint16_t incount; /* Temporary CrypInCount Value */
3443	uint16_t outcount; /* Temporary CrypOutCount Value */
3444	#endif
3445
3446	if (hcryp->State == HAL_CRYP_STATE_BUSY)
3447	{
3448	#if defined (CRYP)
3449
3450	/Temporary CrypOutCount Value/
3451	incount = hcryp->CrypInCount;
3452	if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3453	{
3454	/* Write the input block in the IN FIFO */
3455	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3456	hcryp->CrypInCount++;
3457	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3458	hcryp->CrypInCount++;
3459	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3460	hcryp->CrypInCount++;
3461	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3462	hcryp->CrypInCount++;
3463	if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
3464	{
3465	/* Disable interrupts */
3466	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3467
3468	/* Call the input data transfer complete callback */
3469	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3470	/Call registered Input complete callback/
3471	hcryp->InCpltCallback(hcryp);
3472	#else
3473	/Call legacy weak Input complete callback/
3474	HAL_CRYP_InCpltCallback(hcryp);
3475	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3476	}
3477	}
3478	/Temporary CrypOutCount Value/
3479	outcount = hcryp->CrypOutCount;
3480
3481	if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3482	{
3483	/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3484	for (i = 0U; i < 4U; i++)
3485	{
3486	temp[i] = hcryp->Instance->DOUT;
3487	}
3488	i = 0U;
3489	while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3490	{
3491	(uint32_t )(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3492	hcryp->CrypOutCount++;
3493	i++;
3494	}
3495	if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
3496	{
3497	/* Disable interrupts */
3498	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3499
3500	/* Change the CRYP state */
3501	hcryp->State = HAL_CRYP_STATE_READY;
3502
3503	/* Disable CRYP */
3504	__HAL_CRYP_DISABLE(hcryp);
3505
3506	/* Process unlocked */
3507	__HAL_UNLOCK(hcryp);
3508
3509	/* Call Output transfer complete callback */
3510	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3511	/Call registered Output complete callback/
3512	hcryp->OutCpltCallback(hcryp);
3513	#else
3514	/Call legacy weak Output complete callback/
3515	HAL_CRYP_OutCpltCallback(hcryp);
3516	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3517	}
3518	}
3519
3520	#else /AES/
3521
3522	/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3523	for (i = 0U; i < 4U; i++)
3524	{
3525	temp[i] = hcryp->Instance->DOUTR;
3526	}
3527	i = 0U;
3528	while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3529	{
3530	(uint32_t )(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3531	hcryp->CrypOutCount++;
3532	i++;
3533	}
3534
3535	if (hcryp->CrypOutCount == (hcryp->Size / 4U))
3536	{
3537	/* Disable Computation Complete flag and errors interrupts */
3538	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE \| CRYP_IT_ERRIE);
3539
3540	/* Change the CRYP state */
3541	hcryp->State = HAL_CRYP_STATE_READY;
3542
3543	/* Disable CRYP */
3544	__HAL_CRYP_DISABLE(hcryp);
3545
3546	/* Process Unlocked */
3547	__HAL_UNLOCK(hcryp);
3548
3549	/* Call Output transfer complete callback */
3550	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3551	/Call registered Output complete callback/
3552	hcryp->OutCpltCallback(hcryp);
3553	#else
3554	/Call legacy weak Output complete callback/
3555	HAL_CRYP_OutCpltCallback(hcryp);
3556	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3557	}
3558	else
3559	{
3560	/* Write the input block in the IN FIFO */
3561	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3562	hcryp->CrypInCount++;
3563	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3564	hcryp->CrypInCount++;
3565	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3566	hcryp->CrypInCount++;
3567	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3568	hcryp->CrypInCount++;
3569
3570	if (hcryp->CrypInCount == (hcryp->Size / 4U))
3571	{
3572	/* Call Input transfer complete callback */
3573	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3574	/Call registered Input complete callback/
3575	hcryp->InCpltCallback(hcryp);
3576	#else
3577	/Call legacy weak Input complete callback/
3578	HAL_CRYP_InCpltCallback(hcryp);
3579	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3580	}
3581	}
3582	#endif /* End AES or CRYP */
3583
3584	}
3585	else
3586	{
3587	/* Busy error code field */
3588	hcryp->ErrorCode \|= HAL_CRYP_ERROR_BUSY;
3589	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3590	/Call registered error callback/
3591	hcryp->ErrorCallback(hcryp);
3592	#else
3593	/Call legacy weak error callback/
3594	HAL_CRYP_ErrorCallback(hcryp);
3595	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3596	}
3597	}
3598
3599	/**
3600	* @brief Writes Key in Key registers.
3601	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3602	* the configuration information for CRYP module
3603	* @param KeySize: Size of Key
3604	* @retval None
3605	*/
3606	static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
3607	{
3608	#if defined (CRYP)
3609
3610	switch (KeySize)
3611	{
3612	case CRYP_KEYSIZE_256B:
3613	hcryp->Instance->K0LR = (uint32_t )(hcryp->Init.pKey);
3614	hcryp->Instance->K0RR = (uint32_t )(hcryp->Init.pKey + 1);
3615	hcryp->Instance->K1LR = (uint32_t )(hcryp->Init.pKey + 2);
3616	hcryp->Instance->K1RR = (uint32_t )(hcryp->Init.pKey + 3);
3617	hcryp->Instance->K2LR = (uint32_t )(hcryp->Init.pKey + 4);
3618	hcryp->Instance->K2RR = (uint32_t )(hcryp->Init.pKey + 5);
3619	hcryp->Instance->K3LR = (uint32_t )(hcryp->Init.pKey + 6);
3620	hcryp->Instance->K3RR = (uint32_t )(hcryp->Init.pKey + 7);
3621	break;
3622	case CRYP_KEYSIZE_192B:
3623	hcryp->Instance->K1LR = (uint32_t )(hcryp->Init.pKey);
3624	hcryp->Instance->K1RR = (uint32_t )(hcryp->Init.pKey + 1);
3625	hcryp->Instance->K2LR = (uint32_t )(hcryp->Init.pKey + 2);
3626	hcryp->Instance->K2RR = (uint32_t )(hcryp->Init.pKey + 3);
3627	hcryp->Instance->K3LR = (uint32_t )(hcryp->Init.pKey + 4);
3628	hcryp->Instance->K3RR = (uint32_t )(hcryp->Init.pKey + 5);
3629	break;
3630	case CRYP_KEYSIZE_128B:
3631	hcryp->Instance->K2LR = (uint32_t )(hcryp->Init.pKey);
3632	hcryp->Instance->K2RR = (uint32_t )(hcryp->Init.pKey + 1);
3633	hcryp->Instance->K3LR = (uint32_t )(hcryp->Init.pKey + 2);
3634	hcryp->Instance->K3RR = (uint32_t )(hcryp->Init.pKey + 3);
3635
3636	break;
3637	default:
3638	break;
3639	}
3640	#else /AES/
3641	switch (KeySize)
3642	{
3643	case CRYP_KEYSIZE_256B:
3644	hcryp->Instance->KEYR7 = (uint32_t )(hcryp->Init.pKey);
3645	hcryp->Instance->KEYR6 = (uint32_t )(hcryp->Init.pKey + 1);
3646	hcryp->Instance->KEYR5 = (uint32_t )(hcryp->Init.pKey + 2);
3647	hcryp->Instance->KEYR4 = (uint32_t )(hcryp->Init.pKey + 3);
3648	hcryp->Instance->KEYR3 = (uint32_t )(hcryp->Init.pKey + 4);
3649	hcryp->Instance->KEYR2 = (uint32_t )(hcryp->Init.pKey + 5);
3650	hcryp->Instance->KEYR1 = (uint32_t )(hcryp->Init.pKey + 6);
3651	hcryp->Instance->KEYR0 = (uint32_t )(hcryp->Init.pKey + 7);
3652	break;
3653	case CRYP_KEYSIZE_128B:
3654	hcryp->Instance->KEYR3 = (uint32_t )(hcryp->Init.pKey);
3655	hcryp->Instance->KEYR2 = (uint32_t )(hcryp->Init.pKey + 1);
3656	hcryp->Instance->KEYR1 = (uint32_t )(hcryp->Init.pKey + 2);
3657	hcryp->Instance->KEYR0 = (uint32_t )(hcryp->Init.pKey + 3);
3658
3659	break;
3660	default:
3661	break;
3662	}
3663	#endif /* End AES or CRYP */
3664	}
3665
3666	#if defined (CRYP_CR_ALGOMODE_AES_GCM)\|\| defined (AES)
3667	/**
3668	* @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
3669	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3670	* the configuration information for CRYP module
3671	* @param Timeout: Timeout duration
3672	* @retval HAL status
3673	*/
3674	static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3675	{
3676	uint32_t tickstart;
3677	uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
3678	uint16_t outcount; /* Temporary CrypOutCount Value */
3679	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3680
3681	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3682	{
3683	if (hcryp->KeyIVConfig == 1U)
3684	{
3685	/* If the Key and IV configuration has to be done only once
3686	and if it has already been done, skip it */
3687	DoKeyIVConfig = 0U;
3688	hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3689	}
3690	else
3691	{
3692	/* If the Key and IV configuration has to be done only once
3693	and if it has not been done already, do it and set KeyIVConfig
3694	to keep track it won't have to be done again next time */
3695	hcryp->KeyIVConfig = 1U;
3696	hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3697	}
3698	}
3699	else
3700	{
3701	hcryp->SizesSum = hcryp->Size;
3702	}
3703
3704	if (DoKeyIVConfig == 1U)
3705	{
3706	/* Reset CrypHeaderCount */
3707	hcryp->CrypHeaderCount = 0U;
3708
3709	/**************************** Init phase ********************************/
3710
3711	CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3712
3713	/* Set the key */
3714	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3715
3716	#if defined(CRYP)
3717
3718	/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3719	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
3720	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
3721	hcryp->Instance->IV1LR = (uint32_t )(hcryp->Init.pInitVect + 2);
3722	hcryp->Instance->IV1RR = (uint32_t )(hcryp->Init.pInitVect + 3);
3723
3724	/* Enable the CRYP peripheral */
3725	__HAL_CRYP_ENABLE(hcryp);
3726
3727	/* Get tick */
3728	tickstart = HAL_GetTick();
3729
3730	/Wait for the CRYPEN bit to be cleared/
3731	while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
3732	{
3733	/* Check for the Timeout */
3734	if (Timeout != HAL_MAX_DELAY)
3735	{
3736	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
3737	{
3738	/* Disable the CRYP peripheral clock */
3739	__HAL_CRYP_DISABLE(hcryp);
3740
3741	/* Change state */
3742	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
3743	hcryp->State = HAL_CRYP_STATE_READY;
3744
3745	/* Process unlocked */
3746	__HAL_UNLOCK(hcryp);
3747	return HAL_ERROR;
3748	}
3749	}
3750	}
3751
3752	#else /* AES */
3753	/* Workaround 1 : only AES.
3754	Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
3755	enabling the IP, datatype different from 32 bits can be configured.*/
3756	/* Select DATATYPE 32 */
3757	MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3758
3759	/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3760	hcryp->Instance->IVR3 = (uint32_t )(hcryp->Init.pInitVect);
3761	hcryp->Instance->IVR2 = (uint32_t )(hcryp->Init.pInitVect + 1);
3762	hcryp->Instance->IVR1 = (uint32_t )(hcryp->Init.pInitVect + 2);
3763	hcryp->Instance->IVR0 = (uint32_t )(hcryp->Init.pInitVect + 3);
3764
3765	/* Enable the CRYP peripheral */
3766	__HAL_CRYP_ENABLE(hcryp);
3767
3768	/* just wait for hash computation */
3769	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3770	{
3771	/* Change state */
3772	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
3773	hcryp->State = HAL_CRYP_STATE_READY;
3774
3775	/* Process unlocked & return error */
3776	__HAL_UNLOCK(hcryp);
3777	return HAL_ERROR;
3778	}
3779	/* Clear CCF flag */
3780	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3781
3782	#endif /* End AES or CRYP */
3783
3784	/********************** Header phase ***********************************/
3785
3786	if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
3787	{
3788	return HAL_ERROR;
3789	}
3790
3791	/***********************Payload phase **********************************/
3792
3793	/* Set the phase */
3794	hcryp->Phase = CRYP_PHASE_PROCESS;
3795
3796	#if defined(CRYP)
3797
3798	/* Disable the CRYP peripheral */
3799	__HAL_CRYP_DISABLE(hcryp);
3800
3801	/* Select payload phase once the header phase is performed */
3802	CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3803
3804	/* Enable the CRYP peripheral */
3805	__HAL_CRYP_ENABLE(hcryp);
3806
3807	#else /* AES */
3808
3809	/* Select payload phase once the header phase is performed */
3810	CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3811
3812	#endif /* End AES or CRYP */
3813	} /* if (DoKeyIVConfig == 1U) */
3814
3815	if ((hcryp->Size % 16U) != 0U)
3816	{
3817	/* recalculate wordsize */
3818	wordsize = ((wordsize / 4U) * 4U) ;
3819	}
3820
3821	/* Get tick */
3822	tickstart = HAL_GetTick();
3823	/Temporary CrypOutCount Value/
3824	outcount = hcryp->CrypOutCount;
3825
3826	/* Write input data and get output Data */
3827	while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
3828	{
3829	/* Write plain data and get cipher data */
3830	CRYP_AES_ProcessData(hcryp, Timeout);
3831
3832	/Temporary CrypOutCount Value/
3833	outcount = hcryp->CrypOutCount;
3834
3835	/* Check for the Timeout */
3836	if (Timeout != HAL_MAX_DELAY)
3837	{
3838	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
3839	{
3840	/* Disable the CRYP peripheral clock */
3841	__HAL_CRYP_DISABLE(hcryp);
3842
3843	/* Change state & error code */
3844	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
3845	hcryp->State = HAL_CRYP_STATE_READY;
3846
3847	/* Process unlocked */
3848	__HAL_UNLOCK(hcryp);
3849	return HAL_ERROR;
3850	}
3851	}
3852	}
3853
3854	if ((hcryp->Size % 16U) != 0U)
3855	{
3856	/* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
3857	128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
3858	is selected, then the TAG message will be wrong.*/
3859	CRYP_Workaround(hcryp, Timeout);
3860	}
3861
3862	/* Return function status */
3863	return HAL_OK;
3864	}
3865
3866	/**
3867	* @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
3868	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3869	* the configuration information for CRYP module
3870	* @retval HAL status
3871	*/
3872	static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
3873	{
3874	__IO uint32_t count = 0U;
3875	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3876	#if defined(AES)
3877	uint32_t loopcounter;
3878	uint32_t lastwordsize;
3879	uint32_t npblb;
3880	#endif /* AES */
3881
3882	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3883	{
3884	if (hcryp->KeyIVConfig == 1U)
3885	{
3886	/* If the Key and IV configuration has to be done only once
3887	and if it has already been done, skip it */
3888	DoKeyIVConfig = 0U;
3889	hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3890	}
3891	else
3892	{
3893	/* If the Key and IV configuration has to be done only once
3894	and if it has not been done already, do it and set KeyIVConfig
3895	to keep track it won't have to be done again next time */
3896	hcryp->KeyIVConfig = 1U;
3897	hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3898	}
3899	}
3900	else
3901	{
3902	hcryp->SizesSum = hcryp->Size;
3903	}
3904
3905	/* Configure Key, IV and process message (header and payload) */
3906	if (DoKeyIVConfig == 1U)
3907	{
3908	/* Reset CrypHeaderCount */
3909	hcryp->CrypHeaderCount = 0U;
3910
3911	/***************************** Init phase *******************************/
3912
3913	CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3914
3915	/* Set the key */
3916	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3917
3918	#if defined(CRYP)
3919	/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3920	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
3921	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
3922	hcryp->Instance->IV1LR = (uint32_t )(hcryp->Init.pInitVect + 2);
3923	hcryp->Instance->IV1RR = (uint32_t )(hcryp->Init.pInitVect + 3);
3924
3925	/* Enable the CRYP peripheral */
3926	__HAL_CRYP_ENABLE(hcryp);
3927
3928	/Wait for the CRYPEN bit to be cleared/
3929	count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3930	do
3931	{
3932	count-- ;
3933	if (count == 0U)
3934	{
3935	/* Disable the CRYP peripheral clock */
3936	__HAL_CRYP_DISABLE(hcryp);
3937
3938	/* Change state */
3939	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
3940	hcryp->State = HAL_CRYP_STATE_READY;
3941
3942	/* Process unlocked */
3943	__HAL_UNLOCK(hcryp);
3944	return HAL_ERROR;
3945	}
3946	} while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
3947
3948	#else /* AES */
3949
3950	/* Workaround 1 : only AES
3951	Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
3952	enabling the IP, datatype different from 32 bits can be configured.*/
3953	/* Select DATATYPE 32 */
3954	MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3955
3956	/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3957	hcryp->Instance->IVR3 = (uint32_t )(hcryp->Init.pInitVect);
3958	hcryp->Instance->IVR2 = (uint32_t )(hcryp->Init.pInitVect + 1);
3959	hcryp->Instance->IVR1 = (uint32_t )(hcryp->Init.pInitVect + 2);
3960	hcryp->Instance->IVR0 = (uint32_t )(hcryp->Init.pInitVect + 3);
3961
3962	/* Enable the CRYP peripheral */
3963	__HAL_CRYP_ENABLE(hcryp);
3964
3965	/* just wait for hash computation */
3966	count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3967	do
3968	{
3969	count-- ;
3970	if (count == 0U)
3971	{
3972	/* Disable the CRYP peripheral clock */
3973	__HAL_CRYP_DISABLE(hcryp);
3974
3975	/* Change state */
3976	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
3977	hcryp->State = HAL_CRYP_STATE_READY;
3978
3979	/* Process unlocked */
3980	__HAL_UNLOCK(hcryp);
3981	return HAL_ERROR;
3982	}
3983	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
3984
3985	/* Clear CCF flag */
3986	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3987
3988	#endif /* End AES or CRYP */
3989
3990	/*************************** Header phase *******************************/
3991
3992	#if defined(CRYP)
3993
3994	/* Select header phase */
3995	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
3996
3997	/* Enable interrupts */
3998	__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
3999
4000	/* Enable CRYP */
4001	__HAL_CRYP_ENABLE(hcryp);
4002
4003	#else /* AES */
4004
4005	/* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
4006	MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
4007
4008	/* Select header phase */
4009	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4010
4011	/* Enable computation complete flag and error interrupts */
4012	__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE \| CRYP_IT_ERRIE);
4013
4014	/* Enable the CRYP peripheral */
4015	__HAL_CRYP_ENABLE(hcryp);
4016
4017	if (hcryp->Init.HeaderSize == 0U) /header phase is skipped/
4018	{
4019	/* Set the phase */
4020	hcryp->Phase = CRYP_PHASE_PROCESS;
4021
4022	/* Select payload phase once the header phase is performed */
4023	MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
4024
4025	/* Write the payload Input block in the IN FIFO */
4026	if (hcryp->Size == 0U)
4027	{
4028	/* Disable interrupts */
4029	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE \| CRYP_IT_ERRIE);
4030
4031	/* Change the CRYP state */
4032	hcryp->State = HAL_CRYP_STATE_READY;
4033
4034	/* Process unlocked */
4035	__HAL_UNLOCK(hcryp);
4036	}
4037	else if (hcryp->Size >= 16U)
4038	{
4039	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4040	hcryp->CrypInCount++;
4041	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4042	hcryp->CrypInCount++;
4043	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4044	hcryp->CrypInCount++;
4045	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4046	hcryp->CrypInCount++;
4047	if (hcryp->CrypInCount == (hcryp->Size / 4U))
4048	{
4049	/* Call Input transfer complete callback */
4050	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4051	/Call registered Input complete callback/
4052	hcryp->InCpltCallback(hcryp);
4053	#else
4054	/Call legacy weak Input complete callback/
4055	HAL_CRYP_InCpltCallback(hcryp);
4056	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4057	}
4058	}
4059	else /* Size < 16Bytes : first block is the last block*/
4060	{
4061	/* Workaround not implemented*/
4062	/* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4063	Workaround is implemented in polling mode, so if last block of
4064	payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
4065
4066	/* Compute the number of padding bytes in last block of payload */
4067	npblb = 16U - (uint32_t)(hcryp->Size);
4068
4069	/* Number of valid words (lastwordsize) in last block */
4070	if ((npblb % 4U) == 0U)
4071	{
4072	lastwordsize = (16U - npblb) / 4U;
4073	}
4074	else
4075	{
4076	lastwordsize = ((16U - npblb) / 4U) + 1U;
4077	}
4078
4079	/* last block optionally pad the data with zeros*/
4080	for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
4081	{
4082	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4083	hcryp->CrypInCount++;
4084	}
4085	while (loopcounter < 4U)
4086	{
4087	/* pad the data with zeros to have a complete block */
4088	hcryp->Instance->DINR = 0x0U;
4089	loopcounter++;
4090	}
4091	}
4092	}
4093	else if ((hcryp->Init.HeaderSize) < 4U)
4094	{
4095	for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
4096	{
4097	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4098	hcryp->CrypHeaderCount++ ;
4099	}
4100	while (loopcounter < 4U)
4101	{
4102	/* pad the data with zeros to have a complete block */
4103	hcryp->Instance->DINR = 0x0U;
4104	loopcounter++;
4105	}
4106	/* Set the phase */
4107	hcryp->Phase = CRYP_PHASE_PROCESS;
4108
4109	/* Select payload phase once the header phase is performed */
4110	CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4111
4112	/* Call Input transfer complete callback */
4113	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4114	/Call registered Input complete callback/
4115	hcryp->InCpltCallback(hcryp);
4116	#else
4117	/Call legacy weak Input complete callback/
4118	HAL_CRYP_InCpltCallback(hcryp);
4119	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4120	}
4121	else if ((hcryp->Init.HeaderSize) >= 4U)
4122	{
4123	/* Write the input block in the IN FIFO */
4124	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4125	hcryp->CrypHeaderCount++;
4126	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4127	hcryp->CrypHeaderCount++;
4128	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4129	hcryp->CrypHeaderCount++;
4130	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4131	hcryp->CrypHeaderCount++;
4132	}
4133	else
4134	{
4135	/* Nothing to do */
4136	}
4137
4138	#endif /* End AES or CRYP */
4139	} /* end of if (DoKeyIVConfig == 1U) */
4140
4141	/* Return function status */
4142	return HAL_OK;
4143	}
4144
4145
4146	/**
4147	* @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
4148	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4149	* the configuration information for CRYP module
4150	* @retval HAL status
4151	*/
4152	static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4153	{
4154	__IO uint32_t count = 0U;
4155	uint32_t wordsize;
4156	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4157
4158	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4159	{
4160	if (hcryp->KeyIVConfig == 1U)
4161	{
4162	/* If the Key and IV configuration has to be done only once
4163	and if it has already been done, skip it */
4164	DoKeyIVConfig = 0U;
4165	hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4166	}
4167	else
4168	{
4169	/* If the Key and IV configuration has to be done only once
4170	and if it has not been done already, do it and set KeyIVConfig
4171	to keep track it won't have to be done again next time */
4172	hcryp->KeyIVConfig = 1U;
4173	hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4174	}
4175	}
4176	else
4177	{
4178	hcryp->SizesSum = hcryp->Size;
4179	}
4180
4181	if (DoKeyIVConfig == 1U)
4182	{
4183	/* Reset CrypHeaderCount */
4184	hcryp->CrypHeaderCount = 0U;
4185
4186	/************************* Init phase **********************************/
4187
4188	CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4189
4190	/* Set the key */
4191	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4192
4193	#if defined(CRYP)
4194	/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4195	hcryp->Instance->IV0LR = (uint32_t )(hcryp->Init.pInitVect);
4196	hcryp->Instance->IV0RR = (uint32_t )(hcryp->Init.pInitVect + 1);
4197	hcryp->Instance->IV1LR = (uint32_t )(hcryp->Init.pInitVect + 2);
4198	hcryp->Instance->IV1RR = (uint32_t )(hcryp->Init.pInitVect + 3);
4199
4200	/* Enable the CRYP peripheral */
4201	__HAL_CRYP_ENABLE(hcryp);
4202
4203	/Wait for the CRYPEN bit to be cleared/
4204	count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4205	do
4206	{
4207	count-- ;
4208	if (count == 0U)
4209	{
4210	/* Disable the CRYP peripheral clock */
4211	__HAL_CRYP_DISABLE(hcryp);
4212
4213	/* Change state */
4214	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
4215	hcryp->State = HAL_CRYP_STATE_READY;
4216
4217	/* Process unlocked */
4218	__HAL_UNLOCK(hcryp);
4219	return HAL_ERROR;
4220	}
4221	} while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4222
4223	#else /* AES */
4224
4225	/*Workaround 1 : only AES
4226	Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
4227	enabling the IP, datatype different from 32 bits can be configured.*/
4228	/* Select DATATYPE 32 */
4229	MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
4230
4231	/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4232	hcryp->Instance->IVR3 = (uint32_t )(hcryp->Init.pInitVect);
4233	hcryp->Instance->IVR2 = (uint32_t )(hcryp->Init.pInitVect + 1);
4234	hcryp->Instance->IVR1 = (uint32_t )(hcryp->Init.pInitVect + 2);
4235	hcryp->Instance->IVR0 = (uint32_t )(hcryp->Init.pInitVect + 3);
4236
4237	/* Enable the CRYP peripheral */
4238	__HAL_CRYP_ENABLE(hcryp);
4239
4240	/* just wait for hash computation */
4241	count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4242	do
4243	{
4244	count-- ;
4245	if (count == 0U)
4246	{
4247	/* Disable the CRYP peripheral clock */
4248	__HAL_CRYP_DISABLE(hcryp);
4249
4250	/* Change state */
4251	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
4252	hcryp->State = HAL_CRYP_STATE_READY;
4253
4254	/* Process unlocked */
4255	__HAL_UNLOCK(hcryp);
4256	return HAL_ERROR;
4257	}
4258	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
4259
4260	/* Clear CCF flag */
4261	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4262
4263	#endif /* End AES or CRYP */
4264
4265	/********************** Header phase ***********************************/
4266
4267	if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
4268	{
4269	return HAL_ERROR;
4270	}
4271
4272	/********************** Payload phase **********************************/
4273
4274	/* Set the phase */
4275	hcryp->Phase = CRYP_PHASE_PROCESS;
4276
4277	#if defined(CRYP)
4278
4279	/* Disable the CRYP peripheral */
4280	__HAL_CRYP_DISABLE(hcryp);
4281
4282	#endif /* CRYP */
4283
4284	/* Select payload phase once the header phase is performed */
4285	CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4286
4287	} /* if (DoKeyIVConfig == 1U) */
4288
4289	if (hcryp->Size != 0U)
4290	{
4291	/* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4292	Workaround is implemented in polling mode, so if last block of
4293	payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
4294	/* Set the input and output addresses and start DMA transfer */
4295	if ((hcryp->Size % 16U) == 0U)
4296	{
4297	CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
4298	}
4299	else /to compute last word<128bits, otherwise it will not be encrypted/decrypted /
4300	{
4301	wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
4302
4303	/* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
4304	CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
4305	(uint32_t)(hcryp->pCrypOutBuffPtr));
4306	}
4307	}
4308	else
4309	{
4310	/* Process unLocked */
4311	__HAL_UNLOCK(hcryp);
4312
4313	/* Change the CRYP state and phase */
4314	hcryp->State = HAL_CRYP_STATE_READY;
4315	}
4316
4317	/* Return function status */
4318	return HAL_OK;
4319	}
4320
4321
4322	/**
4323	* @brief AES CCM encryption/decryption processing in polling mode
4324	* for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4325	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4326	* the configuration information for CRYP module
4327	* @param Timeout: Timeout duration
4328	* @retval HAL status
4329	*/
4330	static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4331	{
4332	uint32_t tickstart;
4333	uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
4334	uint16_t outcount; /* Temporary CrypOutCount Value */
4335	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4336	#if defined(AES)
4337	uint32_t loopcounter;
4338	uint32_t npblb;
4339	uint32_t lastwordsize;
4340	#endif /* AES */
4341
4342	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4343	{
4344	if (hcryp->KeyIVConfig == 1U)
4345	{
4346	/* If the Key and IV configuration has to be done only once
4347	and if it has already been done, skip it */
4348	DoKeyIVConfig = 0U;
4349	hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4350	}
4351	else
4352	{
4353	/* If the Key and IV configuration has to be done only once
4354	and if it has not been done already, do it and set KeyIVConfig
4355	to keep track it won't have to be done again next time */
4356	hcryp->KeyIVConfig = 1U;
4357	hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4358	}
4359	}
4360	else
4361	{
4362	hcryp->SizesSum = hcryp->Size;
4363	}
4364
4365	if (DoKeyIVConfig == 1U)
4366	{
4367
4368	/* Reset CrypHeaderCount */
4369	hcryp->CrypHeaderCount = 0U;
4370
4371	#if defined(CRYP)
4372
4373	/******************** Init phase ****************************************/
4374
4375	CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4376
4377	/* Set the key */
4378	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4379
4380	/* Set the initialization vector (IV) with CTR1 information */
4381	hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4382	hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4383	hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4384	hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) \| CRYP_CCM_CTR1_2;
4385
4386
4387	/* Enable the CRYP peripheral */
4388	__HAL_CRYP_ENABLE(hcryp);
4389
4390	/Write B0 packet into CRYP_DIN Register/
4391	if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4392	{
4393	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0));
4394	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0 + 1));
4395	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0 + 2));
4396	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0 + 3));
4397	}
4398	else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4399	{
4400	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0), 16);
4401	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0 + 1), 16);
4402	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0 + 2), 16);
4403	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0 + 3), 16);
4404	}
4405	else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4406	{
4407	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0));
4408	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0 + 1));
4409	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0 + 2));
4410	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0 + 3));
4411	}
4412	else
4413	{
4414	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0);
4415	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0 + 1);
4416	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0 + 2);
4417	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0 + 3);
4418	}
4419	/* Get tick */
4420	tickstart = HAL_GetTick();
4421
4422	/Wait for the CRYPEN bit to be cleared/
4423	while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
4424	{
4425	/* Check for the Timeout */
4426	if (Timeout != HAL_MAX_DELAY)
4427	{
4428	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
4429	{
4430	/* Disable the CRYP peripheral clock */
4431	__HAL_CRYP_DISABLE(hcryp);
4432
4433	/* Change state */
4434	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
4435	hcryp->State = HAL_CRYP_STATE_READY;
4436
4437	/* Process unlocked */
4438	__HAL_UNLOCK(hcryp);
4439	return HAL_ERROR;
4440	}
4441	}
4442	}
4443	#else /* AES */
4444	/AES2v1.1.1 : CCM authentication : no init phase, only header and final phase /
4445	/* Select header phase */
4446	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4447
4448	/* configured encryption mode */
4449	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4450
4451	/* Set the key */
4452	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4453
4454	/* Set the initialization vector with zero values*/
4455	hcryp->Instance->IVR3 = 0U;
4456	hcryp->Instance->IVR2 = 0U;
4457	hcryp->Instance->IVR1 = 0U;
4458	hcryp->Instance->IVR0 = 0U;
4459
4460	/* Enable the CRYP peripheral */
4461	__HAL_CRYP_ENABLE(hcryp);
4462
4463	/Write the B0 packet into CRYP_DIN/
4464	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0);
4465	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0 + 1);
4466	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0 + 2);
4467	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0 + 3);
4468
4469	/* wait until the end of computation */
4470	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4471	{
4472	/* Change state */
4473	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
4474	hcryp->State = HAL_CRYP_STATE_READY;
4475
4476	/* Process unlocked & return error */
4477	__HAL_UNLOCK(hcryp);
4478	return HAL_ERROR;
4479	}
4480	/* Clear CCF flag */
4481	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4482
4483	/* Set the phase */
4484	hcryp->Phase = CRYP_PHASE_PROCESS;
4485
4486	/* From that point the whole message must be processed, first the Header then the payload.
4487	First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
4488
4489	if (hcryp->Init.HeaderSize != 0U)
4490	{
4491	if ((hcryp->Init.HeaderSize % 4U) == 0U)
4492	{
4493	/* HeaderSize %4, no padding */
4494	for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
4495	{
4496	/* Write the Input block in the Data Input register */
4497	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4498	hcryp->CrypHeaderCount++ ;
4499	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4500	hcryp->CrypHeaderCount++ ;
4501	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4502	hcryp->CrypHeaderCount++ ;
4503	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4504	hcryp->CrypHeaderCount++ ;
4505
4506	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4507	{
4508	/* Disable the CRYP peripheral clock */
4509	__HAL_CRYP_DISABLE(hcryp);
4510
4511	/* Change state */
4512	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
4513	hcryp->State = HAL_CRYP_STATE_READY;
4514
4515	/* Process unlocked */
4516	__HAL_UNLOCK(hcryp);
4517	return HAL_ERROR;
4518	}
4519	/* Clear CCF Flag */
4520	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4521	}
4522	}
4523	else
4524	{
4525	/Write Header block in the IN FIFO without last block /
4526	for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
4527	{
4528	/* Write the input block in the data input register */
4529	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4530	hcryp->CrypHeaderCount++ ;
4531	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4532	hcryp->CrypHeaderCount++ ;
4533	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4534	hcryp->CrypHeaderCount++ ;
4535	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4536	hcryp->CrypHeaderCount++ ;
4537
4538	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4539	{
4540	/* Disable the CRYP peripheral clock */
4541	__HAL_CRYP_DISABLE(hcryp);
4542
4543	/* Change state */
4544	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
4545	hcryp->State = HAL_CRYP_STATE_READY;
4546
4547	/* Process unlocked */
4548	__HAL_UNLOCK(hcryp);
4549	return HAL_ERROR;
4550	}
4551	/* Clear CCF Flag */
4552	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4553	}
4554	/* Last block optionally pad the data with zeros*/
4555	for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
4556	{
4557	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
4558	hcryp->CrypHeaderCount++ ;
4559	}
4560	while (loopcounter < 4U)
4561	{
4562	/* Pad the data with zeros to have a complete block */
4563	hcryp->Instance->DINR = 0x0U;
4564	loopcounter++;
4565	}
4566
4567	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4568	{
4569	/* Disable the CRYP peripheral clock */
4570	__HAL_CRYP_DISABLE(hcryp);
4571
4572	/* Change state */
4573	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
4574	hcryp->State = HAL_CRYP_STATE_READY;
4575
4576	/* Process unlocked */
4577	__HAL_UNLOCK(hcryp);
4578	return HAL_ERROR;
4579	}
4580	/* Clear CCF flag */
4581	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4582	}
4583	}
4584	} /* if (DoKeyIVConfig == 1U) */
4585	/* Then the payload: cleartext payload (not the ciphertext payload).
4586	Write input Data, no output Data to get */
4587	if (hcryp->Size != 0U)
4588	{
4589	if ((hcryp->Size % 16U) != 0U)
4590	{
4591	/* recalculate wordsize */
4592	wordsize = ((wordsize / 4U) * 4U) ;
4593	}
4594
4595	/* Get tick */
4596	tickstart = HAL_GetTick();
4597	/Temporary CrypOutCount Value/
4598	outcount = hcryp->CrypOutCount;
4599
4600	while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4601	{
4602	/* Write plain data and get cipher data */
4603	CRYP_AES_ProcessData(hcryp, Timeout);
4604
4605	/Temporary CrypOutCount Value/
4606	outcount = hcryp->CrypOutCount;
4607
4608	/* Check for the Timeout */
4609	if (Timeout != HAL_MAX_DELAY)
4610	{
4611	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
4612	{
4613	/* Disable the CRYP peripheral clock */
4614	__HAL_CRYP_DISABLE(hcryp);
4615
4616	/* Change state */
4617	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
4618	hcryp->State = HAL_CRYP_STATE_READY;
4619
4620	/* Process unlocked */
4621	__HAL_UNLOCK(hcryp);
4622	return HAL_ERROR;
4623	}
4624	}
4625	}
4626
4627	if ((hcryp->Size % 16U) != 0U)
4628	{
4629	/* Compute the number of padding bytes in last block of payload */
4630	npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
4631
4632	/* Number of valid words (lastwordsize) in last block */
4633	if ((npblb % 4U) == 0U)
4634	{
4635	lastwordsize = (16U - npblb) / 4U;
4636	}
4637	else
4638	{
4639	lastwordsize = ((16U - npblb) / 4U) + 1U;
4640	}
4641	/* Last block optionally pad the data with zeros*/
4642	for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
4643	{
4644	/* Write the last input block in the IN FIFO */
4645	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4646	hcryp->CrypInCount++;
4647	}
4648	while (loopcounter < 4U)
4649	{
4650	/* Pad the data with zeros to have a complete block */
4651	hcryp->Instance->DINR = 0U;
4652	loopcounter++;
4653	}
4654	/* Wait for CCF flag to be raised */
4655	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4656	{
4657	/* Disable the CRYP peripheral clock */
4658	__HAL_CRYP_DISABLE(hcryp);
4659
4660	/* Change state */
4661	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
4662	hcryp->State = HAL_CRYP_STATE_READY;
4663
4664	/* Process unlocked */
4665	__HAL_UNLOCK(hcryp);
4666	return HAL_ERROR;
4667	}
4668	/* Clear CCF flag */
4669	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4670
4671	}
4672	}
4673	#endif /* End AES or CRYP */
4674
4675	#if defined(CRYP)
4676
4677	/*********************** Header phase ***********************************/
4678	/* Header block(B1) : associated data length expressed in bytes concatenated
4679	with Associated Data (A)*/
4680
4681	if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
4682	{
4683	return HAL_ERROR;
4684	}
4685
4686	/******************** Payload phase *************************************/
4687
4688	/* Set the phase */
4689	hcryp->Phase = CRYP_PHASE_PROCESS;
4690
4691	/* Disable the CRYP peripheral */
4692	__HAL_CRYP_DISABLE(hcryp);
4693
4694	/* Select payload phase once the header phase is performed */
4695	CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4696
4697	/* Enable the CRYP peripheral */
4698	__HAL_CRYP_ENABLE(hcryp);
4699
4700	} /* if (DoKeyIVConfig == 1U) */
4701
4702	if ((hcryp->Size % 16U) != 0U)
4703	{
4704	/* recalculate wordsize */
4705	wordsize = ((wordsize / 4U) * 4U) ;
4706	}
4707	/* Get tick */
4708	tickstart = HAL_GetTick();
4709	/Temporary CrypOutCount Value/
4710	outcount = hcryp->CrypOutCount;
4711
4712	/* Write input data and get output data */
4713	while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4714	{
4715	/* Write plain data and get cipher data */
4716	CRYP_AES_ProcessData(hcryp, Timeout);
4717
4718	/* Check for the Timeout */
4719	if (Timeout != HAL_MAX_DELAY)
4720	{
4721	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
4722	{
4723	/* Disable the CRYP peripheral clock */
4724	__HAL_CRYP_DISABLE(hcryp);
4725
4726	/* Change state */
4727	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
4728	hcryp->State = HAL_CRYP_STATE_READY;
4729
4730	/* Process unlocked */
4731	__HAL_UNLOCK(hcryp);
4732	return HAL_ERROR;
4733	}
4734	}
4735	}
4736
4737	if ((hcryp->Size % 16U) != 0U)
4738	{
4739	/* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
4740	128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
4741	is selected, then the TAG message will be wrong.*/
4742	CRYP_Workaround(hcryp, Timeout);
4743	}
4744	#endif /* CRYP */
4745
4746	/* Return function status */
4747	return HAL_OK;
4748	}
4749
4750	/**
4751	* @brief AES CCM encryption/decryption process in interrupt mode
4752	* for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4753	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4754	* the configuration information for CRYP module
4755	* @retval HAL status
4756	*/
4757	static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
4758	{
4759	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4760	#if defined(CRYP)
4761	__IO uint32_t count = 0U;
4762	#endif /* CRYP */
4763
4764	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4765	{
4766	if (hcryp->KeyIVConfig == 1U)
4767	{
4768	/* If the Key and IV configuration has to be done only once
4769	and if it has already been done, skip it */
4770	DoKeyIVConfig = 0U;
4771	hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4772	}
4773	else
4774	{
4775	/* If the Key and IV configuration has to be done only once
4776	and if it has not been done already, do it and set KeyIVConfig
4777	to keep track it won't have to be done again next time */
4778	hcryp->KeyIVConfig = 1U;
4779	hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4780	}
4781	}
4782	else
4783	{
4784	hcryp->SizesSum = hcryp->Size;
4785	}
4786
4787	/* Configure Key, IV and process message (header and payload) */
4788	if (DoKeyIVConfig == 1U)
4789	{
4790	/* Reset CrypHeaderCount */
4791	hcryp->CrypHeaderCount = 0U;
4792
4793	#if defined(CRYP)
4794
4795	/********** Init phase **********/
4796
4797	CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4798
4799	/* Set the key */
4800	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4801
4802	/* Set the initialization vector (IV) with CTR1 information */
4803	hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4804	hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4805	hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4806	hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) \| CRYP_CCM_CTR1_2;
4807
4808	/* Enable the CRYP peripheral */
4809	__HAL_CRYP_ENABLE(hcryp);
4810
4811	/Write the B0 packet into CRYP_DIN Register/
4812	if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4813	{
4814	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0));
4815	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0 + 1));
4816	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0 + 2));
4817	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0 + 3));
4818	}
4819	else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4820	{
4821	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0), 16);
4822	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0 + 1), 16);
4823	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0 + 2), 16);
4824	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0 + 3), 16);
4825	}
4826	else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4827	{
4828	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0));
4829	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0 + 1));
4830	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0 + 2));
4831	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0 + 3));
4832	}
4833	else
4834	{
4835	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0);
4836	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0 + 1);
4837	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0 + 2);
4838	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0 + 3);
4839	}
4840	/Wait for the CRYPEN bit to be cleared/
4841	count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4842	do
4843	{
4844	count-- ;
4845	if (count == 0U)
4846	{
4847	/* Disable the CRYP peripheral clock */
4848	__HAL_CRYP_DISABLE(hcryp);
4849
4850	/* Change state */
4851	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
4852	hcryp->State = HAL_CRYP_STATE_READY;
4853
4854	/* Process unlocked */
4855	__HAL_UNLOCK(hcryp);
4856	return HAL_ERROR;
4857	}
4858	} while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4859
4860	/* Select header phase */
4861	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4862
4863	} /* end of if (DoKeyIVConfig == 1U) */
4864
4865	/* Enable interrupts */
4866	__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4867
4868	/* Enable CRYP */
4869	__HAL_CRYP_ENABLE(hcryp);
4870
4871	#else /* AES */
4872
4873	/AES2v1.1.1 : CCM authentication : no init phase, only header and final phase /
4874	/* Select header phase */
4875	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4876
4877	/* configured mode and encryption mode */
4878	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4879
4880	/* Set the key */
4881	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4882
4883	/* Set the initialization vector with zero values*/
4884	hcryp->Instance->IVR3 = 0U;
4885	hcryp->Instance->IVR2 = 0U;
4886	hcryp->Instance->IVR1 = 0U;
4887	hcryp->Instance->IVR0 = 0U;
4888
4889	/* Enable interrupts */
4890	__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE \| CRYP_IT_ERRIE);
4891	/* Enable the CRYP peripheral */
4892	__HAL_CRYP_ENABLE(hcryp);
4893
4894	/Write the B0 packet into CRYP_DIN/
4895	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0);
4896	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0 + 1);
4897	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0 + 2);
4898	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0 + 3);
4899
4900	} /* end of if (DoKeyIVConfig == 1U) */
4901	#endif /* End AES or CRYP */
4902
4903	/* Return function status */
4904	return HAL_OK;
4905	}
4906	/**
4907	* @brief AES CCM encryption/decryption process in DMA mode
4908	* for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4909	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4910	* the configuration information for CRYP module
4911	* @retval HAL status
4912	*/
4913	static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4914	{
4915	uint32_t wordsize;
4916	__IO uint32_t count = 0U;
4917	uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4918	#if defined(AES)
4919	uint32_t loopcounter;
4920	uint32_t npblb;
4921	uint32_t lastwordsize;
4922	#endif
4923
4924	if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4925	{
4926	if (hcryp->KeyIVConfig == 1U)
4927	{
4928	/* If the Key and IV configuration has to be done only once
4929	and if it has already been done, skip it */
4930	DoKeyIVConfig = 0U;
4931	hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4932	}
4933	else
4934	{
4935	/* If the Key and IV configuration has to be done only once
4936	and if it has not been done already, do it and set KeyIVConfig
4937	to keep track it won't have to be done again next time */
4938	hcryp->KeyIVConfig = 1U;
4939	hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4940	}
4941	}
4942	else
4943	{
4944	hcryp->SizesSum = hcryp->Size;
4945	}
4946
4947	if (DoKeyIVConfig == 1U)
4948	{
4949
4950	/* Reset CrypHeaderCount */
4951	hcryp->CrypHeaderCount = 0U;
4952
4953	#if defined(CRYP)
4954
4955	/************************ Init phase ************************************/
4956
4957	CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4958
4959	/* Set the key */
4960	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4961
4962	/* Set the initialization vector (IV) with CTR1 information */
4963	hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4964	hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4965	hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4966	hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) \| CRYP_CCM_CTR1_2;
4967
4968	/* Enable the CRYP peripheral */
4969	__HAL_CRYP_ENABLE(hcryp);
4970
4971	/Write the B0 packet into CRYP_DIN Register/
4972	if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4973	{
4974	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0));
4975	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0 + 1));
4976	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0 + 2));
4977	hcryp->Instance->DIN = __REV((uint32_t )(hcryp->Init.B0 + 3));
4978	}
4979	else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4980	{
4981	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0), 16);
4982	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0 + 1), 16);
4983	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0 + 2), 16);
4984	hcryp->Instance->DIN = __ROR((uint32_t )(hcryp->Init.B0 + 3), 16);
4985	}
4986	else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4987	{
4988	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0));
4989	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0 + 1));
4990	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0 + 2));
4991	hcryp->Instance->DIN = __RBIT((uint32_t )(hcryp->Init.B0 + 3));
4992	}
4993	else
4994	{
4995	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0);
4996	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0 + 1);
4997	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0 + 2);
4998	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.B0 + 3);
4999	}
5000
5001	/Wait for the CRYPEN bit to be cleared/
5002	count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5003	do
5004	{
5005	count-- ;
5006	if (count == 0U)
5007	{
5008	/* Disable the CRYP peripheral clock */
5009	__HAL_CRYP_DISABLE(hcryp);
5010
5011	/* Change state */
5012	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5013	hcryp->State = HAL_CRYP_STATE_READY;
5014
5015	/* Process unlocked */
5016	__HAL_UNLOCK(hcryp);
5017	return HAL_ERROR;
5018	}
5019	} while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
5020
5021	#else /* AES */
5022
5023	/AES2v1.1.1 : CCM authentication : no init phase, only header and final phase /
5024	/* Select header phase */
5025	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5026
5027	/* configured encryption mode */
5028	MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
5029
5030	/* Set the key */
5031	CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5032
5033	/* Set the initialization vector with zero values*/
5034	hcryp->Instance->IVR3 = 0U;
5035	hcryp->Instance->IVR2 = 0U;
5036	hcryp->Instance->IVR1 = 0U;
5037	hcryp->Instance->IVR0 = 0U;
5038
5039	/* Enable the CRYP peripheral */
5040	__HAL_CRYP_ENABLE(hcryp);
5041
5042	/Write the B0 packet into CRYP_DIN/
5043	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0);
5044	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0 + 1);
5045	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0 + 2);
5046	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.B0 + 3);
5047
5048	count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5049	do
5050	{
5051	count-- ;
5052	if (count == 0U)
5053	{
5054	/* Disable the CRYP peripheral clock */
5055	__HAL_CRYP_DISABLE(hcryp);
5056
5057	/* Change state */
5058	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5059	hcryp->State = HAL_CRYP_STATE_READY;
5060
5061	/* Process Unlocked */
5062	__HAL_UNLOCK(hcryp);
5063	return HAL_ERROR;
5064	}
5065	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5066	/* Clear CCF flag */
5067	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5068
5069	/* Set the phase */
5070	hcryp->Phase = CRYP_PHASE_PROCESS;
5071
5072	/* From that point the whole message must be processed, first the Header then the payload.
5073	First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
5074
5075	if (hcryp->Init.HeaderSize != 0U)
5076	{
5077	if ((hcryp->Init.HeaderSize % 4U) == 0U)
5078	{
5079	/* HeaderSize %4, no padding */
5080	for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
5081	{
5082	/* Write the Input block in the Data Input register */
5083	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5084	hcryp->CrypHeaderCount++ ;
5085	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5086	hcryp->CrypHeaderCount++ ;
5087	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5088	hcryp->CrypHeaderCount++ ;
5089	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5090	hcryp->CrypHeaderCount++ ;
5091
5092	/* wait until the end of computation */
5093	count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5094	do
5095	{
5096	count-- ;
5097	if (count == 0U)
5098	{
5099	/* Disable the CRYP peripheral clock */
5100	__HAL_CRYP_DISABLE(hcryp);
5101
5102	/* Change state */
5103	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5104	hcryp->State = HAL_CRYP_STATE_READY;
5105
5106	/* Process Unlocked */
5107	__HAL_UNLOCK(hcryp);
5108	return HAL_ERROR;
5109	}
5110	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5111	/* Clear CCF flag */
5112	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5113	}
5114	}
5115	else
5116	{
5117	/Write Header block in the IN FIFO without last block /
5118	for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
5119	{
5120	/* Write the input block in the data input register */
5121	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5122	hcryp->CrypHeaderCount++ ;
5123	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5124	hcryp->CrypHeaderCount++ ;
5125	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5126	hcryp->CrypHeaderCount++ ;
5127	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5128	hcryp->CrypHeaderCount++ ;
5129
5130	count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5131	do
5132	{
5133	count-- ;
5134	if (count == 0U)
5135	{
5136	/* Disable the CRYP peripheral clock */
5137	__HAL_CRYP_DISABLE(hcryp);
5138
5139	/* Change state */
5140	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5141	hcryp->State = HAL_CRYP_STATE_READY;
5142
5143	/* Process Unlocked */
5144	__HAL_UNLOCK(hcryp);
5145	return HAL_ERROR;
5146	}
5147	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5148	/* Clear CCF flag */
5149	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5150	}
5151	/* Last block optionally pad the data with zeros*/
5152	for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
5153	{
5154	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5155	hcryp->CrypHeaderCount++ ;
5156	}
5157	while (loopcounter < 4U)
5158	{
5159	/* Pad the data with zeros to have a complete block */
5160	hcryp->Instance->DINR = 0x0U;
5161	loopcounter++;
5162	}
5163
5164	count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5165	do
5166	{
5167	count-- ;
5168	if (count == 0U)
5169	{
5170	/* Disable the CRYP peripheral clock */
5171	__HAL_CRYP_DISABLE(hcryp);
5172
5173	/* Change state */
5174	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5175	hcryp->State = HAL_CRYP_STATE_READY;
5176
5177	/* Process Unlocked */
5178	__HAL_UNLOCK(hcryp);
5179	return HAL_ERROR;
5180	}
5181	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5182	/* Clear CCF flag */
5183	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5184	}
5185	}
5186	} /* if (DoKeyIVConfig == 1U) */
5187	/* Then the payload: cleartext payload (not the ciphertext payload).
5188	Write input Data, no output Data to get */
5189	if (hcryp->Size != 0U)
5190	{
5191	if (hcryp->Size >= 16U)
5192	{
5193	if ((hcryp->Size % 16U) == 0U)
5194	{
5195	CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
5196	}
5197	else /to compute last word<128bits, otherwise it will not be encrypted/decrypted /
5198	{
5199	wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
5200
5201	/* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
5202	CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
5203	(uint32_t)(hcryp->pCrypOutBuffPtr));
5204	}
5205	}
5206	if ((hcryp->Size < 16U) != 0U)
5207	{
5208	/* Compute the number of padding bytes in last block of payload */
5209	npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5210
5211	/* Number of valid words (lastwordsize) in last block */
5212	if ((npblb % 4U) == 0U)
5213	{
5214	lastwordsize = (16U - npblb) / 4U;
5215	}
5216	else
5217	{
5218	lastwordsize = ((16U - npblb) / 4U) + 1U;
5219	}
5220	/* Last block optionally pad the data with zeros*/
5221	for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
5222	{
5223	/* Write the last input block in the IN FIFO */
5224	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5225	hcryp->CrypInCount++;
5226	}
5227	while (loopcounter < 4U)
5228	{
5229	/* Pad the data with zeros to have a complete block */
5230	hcryp->Instance->DINR = 0U;
5231	loopcounter++;
5232	}
5233	count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5234	do
5235	{
5236	count-- ;
5237	if (count == 0U)
5238	{
5239	/* Disable the CRYP peripheral clock */
5240	__HAL_CRYP_DISABLE(hcryp);
5241
5242	/* Change state */
5243	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5244	hcryp->State = HAL_CRYP_STATE_READY;
5245
5246	/* Process Unlocked */
5247	__HAL_UNLOCK(hcryp);
5248	return HAL_ERROR;
5249	}
5250	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5251	/* Clear CCF flag */
5252	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5253
5254	/* Process unlocked */
5255	__HAL_UNLOCK(hcryp);
5256
5257	/* Change the CRYP state and phase */
5258	hcryp->State = HAL_CRYP_STATE_READY;
5259	}
5260	}
5261	else
5262	{
5263	/* Process unLocked */
5264	__HAL_UNLOCK(hcryp);
5265
5266	/* Change the CRYP state and phase */
5267	hcryp->State = HAL_CRYP_STATE_READY;
5268	}
5269	#endif /* AES */
5270	#if defined(CRYP)
5271	/******************* Header phase ***************************************/
5272
5273	if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
5274	{
5275	return HAL_ERROR;
5276	}
5277
5278	/****************** Payload phase ***************************************/
5279
5280	/* Set the phase */
5281	hcryp->Phase = CRYP_PHASE_PROCESS;
5282
5283	/* Disable the CRYP peripheral */
5284	__HAL_CRYP_DISABLE(hcryp);
5285
5286	/* Select payload phase once the header phase is performed */
5287	CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
5288
5289	} /* if (DoKeyIVConfig == 1U) */
5290	if (hcryp->Size != 0U)
5291	{
5292	/* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
5293	Workaround is implemented in polling mode, so if last block of
5294	payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
5295	/* Set the input and output addresses and start DMA transfer */
5296	if ((hcryp->Size % 16U) == 0U)
5297	{
5298	CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size / 4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
5299	}
5300	else
5301	{
5302	wordsize = (uint32_t)(hcryp->Size) + 16U - ((uint32_t)(hcryp->Size) % 16U) ;
5303
5304	/* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
5305	CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize / 4U,
5306	(uint32_t)(hcryp->pCrypOutBuffPtr));
5307	}
5308	}
5309	else /Size = 0/
5310	{
5311	/* Process unlocked */
5312	__HAL_UNLOCK(hcryp);
5313
5314	/* Change the CRYP state and phase */
5315	hcryp->State = HAL_CRYP_STATE_READY;
5316	}
5317	#endif /* CRYP */
5318	/* Return function status */
5319	return HAL_OK;
5320	}
5321
5322	/**
5323	* @brief Sets the payload phase in iterrupt mode
5324	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5325	* the configuration information for CRYP module
5326	* @retval state
5327	*/
5328	static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
5329	{
5330	uint32_t loopcounter;
5331	uint32_t temp[4]; /* Temporary CrypOutBuff */
5332	uint32_t lastwordsize;
5333	uint32_t npblb;
5334	uint32_t i;
5335	#if defined(AES)
5336	uint16_t outcount; /* Temporary CrypOutCount Value */
5337	#endif /* AES */
5338
5339	/*************************** Payload phase *****************************/
5340
5341	#if defined(CRYP)
5342	if (hcryp->Size == 0U)
5343	{
5344	/* Disable interrupts */
5345	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI \| CRYP_IT_OUTI);
5346
5347	/* Process unlocked */
5348	__HAL_UNLOCK(hcryp);
5349
5350	/* Change the CRYP state */
5351	hcryp->State = HAL_CRYP_STATE_READY;
5352	}
5353
5354	else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5355	{
5356	/* Write the input block in the IN FIFO */
5357	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5358	hcryp->CrypInCount++;
5359	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5360	hcryp->CrypInCount++;
5361	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5362	hcryp->CrypInCount++;
5363	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5364	hcryp->CrypInCount++;
5365	if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
5366	{
5367	/* Disable interrupts */
5368	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5369
5370	/* Call the input data transfer complete callback */
5371	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5372	/Call registered Input complete callback/
5373	hcryp->InCpltCallback(hcryp);
5374	#else
5375	/Call legacy weak Input complete callback/
5376	HAL_CRYP_InCpltCallback(hcryp);
5377	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5378	}
5379	if (hcryp->CrypOutCount < (hcryp->Size / 4U))
5380	{
5381	/* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
5382	for (i = 0U; i < 4U; i++)
5383	{
5384	temp[i] = hcryp->Instance->DOUT;
5385	}
5386	i = 0U;
5387	while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5388	{
5389	(uint32_t )(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5390	hcryp->CrypOutCount++;
5391	i++;
5392	}
5393	if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
5394	{
5395	/* Disable interrupts */
5396	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
5397
5398	/* Change the CRYP state */
5399	hcryp->State = HAL_CRYP_STATE_READY;
5400
5401	/* Disable CRYP */
5402	__HAL_CRYP_DISABLE(hcryp);
5403
5404	/* Process unlocked */
5405	__HAL_UNLOCK(hcryp);
5406
5407	/* Call output transfer complete callback */
5408	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5409	/Call registered Output complete callback/
5410	hcryp->OutCpltCallback(hcryp);
5411	#else
5412	/Call legacy weak Output complete callback/
5413	HAL_CRYP_OutCpltCallback(hcryp);
5414	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5415	}
5416	}
5417	}
5418	else if ((hcryp->Size % 16U) != 0U)
5419	{
5420	/* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
5421	Workaround is implemented in polling mode, so if last block of
5422	payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
5423
5424	/* Compute the number of padding bytes in last block of payload */
5425	npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5426
5427	/* Number of valid words (lastwordsize) in last block */
5428	if ((npblb % 4U) == 0U)
5429	{
5430	lastwordsize = (16U - npblb) / 4U;
5431	}
5432	else
5433	{
5434	lastwordsize = ((16U - npblb) / 4U) + 1U;
5435	}
5436
5437	/* Last block optionally pad the data with zeros*/
5438	for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5439	{
5440	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5441	hcryp->CrypInCount++;
5442	}
5443	while (loopcounter < 4U)
5444	{
5445	/* Pad the data with zeros to have a complete block */
5446	hcryp->Instance->DIN = 0x0U;
5447	loopcounter++;
5448	}
5449	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5450
5451	if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
5452	{
5453	for (i = 0U; i < 4U; i++)
5454	{
5455	temp[i] = hcryp->Instance->DOUT;
5456	}
5457	if (((hcryp->Size) / 4U) == 0U)
5458	{
5459	for (i = 0U; i < ((uint32_t)(hcryp->Size) % 4U); i++)
5460	{
5461	(uint32_t )(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5462	hcryp->CrypOutCount++;
5463	}
5464	}
5465	i = 0x0U;
5466	while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5467	{
5468	(uint32_t )(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5469	hcryp->CrypOutCount++;
5470	i++;
5471	}
5472	}
5473	if (hcryp->CrypOutCount >= (hcryp->Size / 4U))
5474	{
5475	/* Disable interrupts */
5476	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI \| CRYP_IT_INI);
5477
5478	/* Change the CRYP peripheral state */
5479	hcryp->State = HAL_CRYP_STATE_READY;
5480
5481	/* Process unlocked */
5482	__HAL_UNLOCK(hcryp);
5483
5484	/* Call output transfer complete callback */
5485	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5486	/Call registered Output complete callback/
5487	hcryp->OutCpltCallback(hcryp);
5488	#else
5489	/Call legacy weak Output complete callback/
5490	HAL_CRYP_OutCpltCallback(hcryp);
5491	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5492	}
5493	}
5494	else
5495	{
5496	/* Nothing to do */
5497	}
5498	#else /* AES */
5499
5500	/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
5501	for (i = 0U; i < 4U; i++)
5502	{
5503	temp[i] = hcryp->Instance->DOUTR;
5504	}
5505	i = 0U;
5506	while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
5507	{
5508	(uint32_t )(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5509	hcryp->CrypOutCount++;
5510	i++;
5511	}
5512	/Temporary CrypOutCount Value/
5513	outcount = hcryp->CrypOutCount;
5514
5515	if ((hcryp->CrypOutCount >= (hcryp->Size / 4U)) && ((outcount * 4U) >= hcryp->Size))
5516	{
5517	/* Disable computation complete flag and errors interrupts */
5518	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE \| CRYP_IT_ERRIE);
5519
5520	/* Change the CRYP state */
5521	hcryp->State = HAL_CRYP_STATE_READY;
5522
5523	/* Process unlocked */
5524	__HAL_UNLOCK(hcryp);
5525
5526	/* Call output transfer complete callback */
5527	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5528	/Call registered Output complete callback/
5529	hcryp->OutCpltCallback(hcryp);
5530	#else
5531	/Call legacy weak Output complete callback/
5532	HAL_CRYP_OutCpltCallback(hcryp);
5533	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5534	}
5535
5536	else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5537	{
5538	/* Write the input block in the IN FIFO */
5539	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5540	hcryp->CrypInCount++;
5541	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5542	hcryp->CrypInCount++;
5543	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5544	hcryp->CrypInCount++;
5545	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5546	hcryp->CrypInCount++;
5547	if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
5548	{
5549	/* Call Input transfer complete callback */
5550	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5551	/Call registered Input complete callback/
5552	hcryp->InCpltCallback(hcryp);
5553	#else
5554	/Call legacy weak Input complete callback/
5555	HAL_CRYP_InCpltCallback(hcryp);
5556	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5557	}
5558	}
5559	else /* Last block of payload < 128bit*/
5560	{
5561	/* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
5562	generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
5563	payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
5564
5565	/* Compute the number of padding bytes in last block of payload */
5566	npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5567
5568	/* Number of valid words (lastwordsize) in last block */
5569	if ((npblb % 4U) == 0U)
5570	{
5571	lastwordsize = (16U - npblb) / 4U;
5572	}
5573	else
5574	{
5575	lastwordsize = ((16U - npblb) / 4U) + 1U;
5576	}
5577
5578	/* Last block optionally pad the data with zeros*/
5579	for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5580	{
5581	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5582	hcryp->CrypInCount++;
5583	}
5584	while (loopcounter < 4U)
5585	{
5586	/* pad the data with zeros to have a complete block */
5587	hcryp->Instance->DINR = 0x0U;
5588	loopcounter++;
5589	}
5590	}
5591	#endif /* AES */
5592
5593	}
5594
5595
5596	/**
5597	* @brief Sets the header phase in polling mode
5598	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5599	* the configuration information for CRYP module(Header & HeaderSize)
5600	* @param Timeout: Timeout value
5601	* @retval state
5602	*/
5603	static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
5604	{
5605	uint32_t loopcounter;
5606	uint32_t size_in_bytes;
5607	uint32_t tmp;
5608	uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5609	0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5610	0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
5611
5612	/*************************** Header phase for GCM/GMAC or CCM *******************************/
5613
5614	if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
5615	{
5616	size_in_bytes = hcryp->Init.HeaderSize * 4U;
5617	}
5618	else
5619	{
5620	size_in_bytes = hcryp->Init.HeaderSize;
5621	}
5622
5623	if (size_in_bytes != 0U)
5624	{
5625
5626	#if defined(CRYP)
5627
5628	/* Select header phase */
5629	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5630
5631	/* Enable the CRYP peripheral */
5632	__HAL_CRYP_ENABLE(hcryp);
5633
5634	if ((size_in_bytes % 16U) == 0U)
5635	{
5636	/* HeaderSize %4, no padding */
5637	for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
5638	{
5639	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5640	hcryp->CrypHeaderCount++ ;
5641	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5642	hcryp->CrypHeaderCount++ ;
5643	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5644	hcryp->CrypHeaderCount++ ;
5645	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5646	hcryp->CrypHeaderCount++ ;
5647
5648	/* Wait for IFEM to be raised */
5649	if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5650	{
5651	/* Disable the CRYP peripheral clock */
5652	__HAL_CRYP_DISABLE(hcryp);
5653
5654	/* Change state */
5655	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5656	hcryp->State = HAL_CRYP_STATE_READY;
5657
5658	/* Process unlocked */
5659	__HAL_UNLOCK(hcryp);
5660	return HAL_ERROR;
5661	}
5662	}
5663	}
5664	else
5665	{
5666	/Write header block in the IN FIFO without last block /
5667	for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
5668	{
5669	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5670	hcryp->CrypHeaderCount++ ;
5671	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5672	hcryp->CrypHeaderCount++ ;
5673	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5674	hcryp->CrypHeaderCount++ ;
5675	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5676	hcryp->CrypHeaderCount++ ;
5677
5678	/* Wait for IFEM to be raised */
5679	if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5680	{
5681	/* Disable the CRYP peripheral clock */
5682	__HAL_CRYP_DISABLE(hcryp);
5683
5684	/* Change state */
5685	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5686	hcryp->State = HAL_CRYP_STATE_READY;
5687
5688	/* Process unlocked */
5689	__HAL_UNLOCK(hcryp);
5690	return HAL_ERROR;
5691	}
5692	}
5693	/* Last block optionally pad the data with zeros*/
5694	for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
5695	{
5696	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5697	hcryp->CrypHeaderCount++ ;
5698	}
5699	/* If the header size is a multiple of words */
5700	if ((size_in_bytes % 4U) == 0U)
5701	{
5702	/* Pad the data with zeros to have a complete block */
5703	while (loopcounter < 4U)
5704	{
5705	hcryp->Instance->DIN = 0x0U;
5706	loopcounter++;
5707	}
5708	}
5709	else
5710	{
5711	/* Enter last bytes, padded with zeroes */
5712	tmp = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5713	tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
5714	hcryp->Instance->DIN = tmp;
5715	loopcounter++;
5716	/* Pad the data with zeros to have a complete block */
5717	while (loopcounter < 4U)
5718	{
5719	hcryp->Instance->DIN = 0x0U;
5720	loopcounter++;
5721	}
5722	}
5723	/* Wait for CCF IFEM to be raised */
5724	if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5725	{
5726	/* Disable the CRYP peripheral clock */
5727	__HAL_CRYP_DISABLE(hcryp);
5728
5729	/* Change state */
5730	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5731	hcryp->State = HAL_CRYP_STATE_READY;
5732
5733	/* Process unlocked */
5734	__HAL_UNLOCK(hcryp);
5735	return HAL_ERROR;
5736	}
5737	}
5738	/* Wait until the complete message has been processed */
5739	if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
5740	{
5741	/* Disable the CRYP peripheral clock */
5742	__HAL_CRYP_DISABLE(hcryp);
5743
5744	/* Change state */
5745	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5746	hcryp->State = HAL_CRYP_STATE_READY;
5747
5748	/* Process unlocked & return error */
5749	__HAL_UNLOCK(hcryp);
5750	return HAL_ERROR;
5751	}
5752
5753	#else /* AES */
5754
5755	if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5756	{
5757	/* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
5758	MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5759
5760	/* Select header phase */
5761	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5762
5763	/* Enable the CRYP peripheral */
5764	__HAL_CRYP_ENABLE(hcryp);
5765
5766	}
5767	/* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
5768	if ((size_in_bytes % 16U) == 0U)
5769	{
5770	/* No padding */
5771	for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
5772	{
5773	/* Write the input block in the data input register */
5774	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5775	hcryp->CrypHeaderCount++ ;
5776	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5777	hcryp->CrypHeaderCount++ ;
5778	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5779	hcryp->CrypHeaderCount++ ;
5780	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5781	hcryp->CrypHeaderCount++ ;
5782
5783	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5784	{
5785	/* Disable the CRYP peripheral clock */
5786	__HAL_CRYP_DISABLE(hcryp);
5787
5788	/* Change state */
5789	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5790	hcryp->State = HAL_CRYP_STATE_READY;
5791
5792	/* Process unlocked */
5793	__HAL_UNLOCK(hcryp);
5794	return HAL_ERROR;
5795	}
5796	/* Clear CCF flag */
5797	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5798	}
5799	}
5800	else
5801	{
5802	/Write header block in the IN FIFO without last block /
5803	for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
5804	{
5805	/* Write the input block in the data input register */
5806	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5807	hcryp->CrypHeaderCount++ ;
5808	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5809	hcryp->CrypHeaderCount++ ;
5810	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5811	hcryp->CrypHeaderCount++ ;
5812	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5813	hcryp->CrypHeaderCount++ ;
5814
5815	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5816	{
5817	/* Disable the CRYP peripheral clock */
5818	__HAL_CRYP_DISABLE(hcryp);
5819
5820	/* Change state */
5821	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5822	hcryp->State = HAL_CRYP_STATE_READY;
5823
5824	/* Process unlocked */
5825	__HAL_UNLOCK(hcryp);
5826	return HAL_ERROR;
5827	}
5828	/* Clear CCF flag */
5829	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5830	}
5831	/* Write last complete words */
5832	for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
5833	{
5834	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5835	hcryp->CrypHeaderCount++ ;
5836	}
5837	/* If the header size is a multiple of words */
5838	if ((size_in_bytes % 4U) == 0U)
5839	{
5840	/* Pad the data with zeros to have a complete block */
5841	while (loopcounter < 4U)
5842	{
5843	hcryp->Instance->DINR = 0x0U;
5844	loopcounter++;
5845	}
5846	}
5847	else
5848	{
5849	/* Enter last bytes, padded with zeroes */
5850	tmp = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5851	tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
5852	hcryp->Instance->DINR = tmp;
5853	loopcounter++;
5854	/* Pad the data with zeros to have a complete block */
5855	while (loopcounter < 4U)
5856	{
5857	hcryp->Instance->DINR = 0x0U;
5858	loopcounter++;
5859	}
5860	}
5861
5862	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5863	{
5864	/* Disable the CRYP peripheral clock */
5865	__HAL_CRYP_DISABLE(hcryp);
5866
5867	/* Change state */
5868	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5869	hcryp->State = HAL_CRYP_STATE_READY;
5870
5871	/* Process unlocked */
5872	__HAL_UNLOCK(hcryp);
5873	return HAL_ERROR;
5874	}
5875	/* Clear CCF flag */
5876	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5877	}
5878	#endif /* End AES or CRYP */
5879	}
5880	else
5881	{
5882	#if defined(AES)
5883	if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5884	{
5885	/Workaround 1: only AES, before re-enabling the IP, datatype can be configured./
5886	MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5887
5888	/* Select header phase */
5889	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5890
5891	/* Enable the CRYP peripheral */
5892	__HAL_CRYP_ENABLE(hcryp);
5893	}
5894	#endif /* AES */
5895	}
5896	/* Return function status */
5897	return HAL_OK;
5898	}
5899
5900	/**
5901	* @brief Sets the header phase when using DMA in process
5902	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5903	* the configuration information for CRYP module(Header & HeaderSize)
5904	* @retval None
5905	*/
5906	static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
5907	{
5908	__IO uint32_t count = 0U;
5909	uint32_t loopcounter;
5910	uint32_t headersize_in_bytes;
5911	uint32_t tmp;
5912	uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5913	0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5914	0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
5915
5916	/*************************** Header phase for GCM/GMAC or CCM *******************************/
5917	if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
5918	{
5919	headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
5920	}
5921	else
5922	{
5923	headersize_in_bytes = hcryp->Init.HeaderSize;
5924	}
5925
5926	if (headersize_in_bytes != 0U)
5927	{
5928
5929	#if defined(CRYP)
5930
5931	/* Select header phase */
5932	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5933
5934	/* Enable the CRYP peripheral */
5935	__HAL_CRYP_ENABLE(hcryp);
5936
5937	if ((headersize_in_bytes % 16U) == 0U)
5938	{
5939	/* HeaderSize %4, no padding */
5940	for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
5941	{
5942	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5943	hcryp->CrypHeaderCount++ ;
5944	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5945	hcryp->CrypHeaderCount++ ;
5946	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5947	hcryp->CrypHeaderCount++ ;
5948	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5949	hcryp->CrypHeaderCount++ ;
5950
5951	/* Wait for IFEM to be raised */
5952	count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5953	do
5954	{
5955	count-- ;
5956	if (count == 0U)
5957	{
5958	/* Disable the CRYP peripheral clock */
5959	__HAL_CRYP_DISABLE(hcryp);
5960
5961	/* Change state */
5962	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5963	hcryp->State = HAL_CRYP_STATE_READY;
5964
5965	/* Process unlocked */
5966	__HAL_UNLOCK(hcryp);
5967	return HAL_ERROR;
5968	}
5969	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5970	}
5971	}
5972	else
5973	{
5974	/Write header block in the IN FIFO without last block /
5975	for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
5976	{
5977	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5978	hcryp->CrypHeaderCount++ ;
5979	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5980	hcryp->CrypHeaderCount++ ;
5981	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5982	hcryp->CrypHeaderCount++ ;
5983	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
5984	hcryp->CrypHeaderCount++ ;
5985
5986	/* Wait for IFEM to be raised */
5987	count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5988	do
5989	{
5990	count-- ;
5991	if (count == 0U)
5992	{
5993	/* Disable the CRYP peripheral clock */
5994	__HAL_CRYP_DISABLE(hcryp);
5995
5996	/* Change state */
5997	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
5998	hcryp->State = HAL_CRYP_STATE_READY;
5999
6000	/* Process unlocked */
6001	__HAL_UNLOCK(hcryp);
6002	return HAL_ERROR;
6003	}
6004	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
6005	}
6006	/* Last block optionally pad the data with zeros*/
6007	for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
6008	{
6009	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6010	hcryp->CrypHeaderCount++ ;
6011	}
6012	/* If the header size is a multiple of words */
6013	if ((headersize_in_bytes % 4U) == 0U)
6014	{
6015	/* Pad the data with zeros to have a complete block */
6016	while (loopcounter < 4U)
6017	{
6018	hcryp->Instance->DIN = 0x0U;
6019	loopcounter++;
6020	}
6021	}
6022	else
6023	{
6024	/* Enter last bytes, padded with zeroes */
6025	tmp = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6026	tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6027	hcryp->Instance->DIN = tmp;
6028	loopcounter++;
6029	/* Pad the data with zeros to have a complete block */
6030	while (loopcounter < 4U)
6031	{
6032	hcryp->Instance->DIN = 0x0U;
6033	loopcounter++;
6034	}
6035	}
6036	/* Wait for IFEM to be raised */
6037	count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6038	do
6039	{
6040	count-- ;
6041	if (count == 0U)
6042	{
6043	/* Disable the CRYP peripheral clock */
6044	__HAL_CRYP_DISABLE(hcryp);
6045
6046	/* Change state */
6047	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
6048	hcryp->State = HAL_CRYP_STATE_READY;
6049
6050	/* Process unlocked */
6051	__HAL_UNLOCK(hcryp);
6052	return HAL_ERROR;
6053	}
6054	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
6055	}
6056	/* Wait until the complete message has been processed */
6057	count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6058	do
6059	{
6060	count-- ;
6061	if (count == 0U)
6062	{
6063	/* Disable the CRYP peripheral clock */
6064	__HAL_CRYP_DISABLE(hcryp);
6065
6066	/* Change state */
6067	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
6068	hcryp->State = HAL_CRYP_STATE_READY;
6069
6070	/* Process unlocked */
6071	__HAL_UNLOCK(hcryp);
6072	return HAL_ERROR;
6073	}
6074	} while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
6075
6076	#else /* AES */
6077
6078	if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6079	{
6080	/* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
6081	MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
6082
6083	/* Select header phase */
6084	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6085
6086	/* Enable the CRYP peripheral */
6087	__HAL_CRYP_ENABLE(hcryp);
6088	}
6089	if ((headersize_in_bytes % 16U) == 0U)
6090	{
6091	/* HeaderSize %4, no padding */
6092	for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
6093	{
6094	/* Write the input block in the data input register */
6095	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6096	hcryp->CrypHeaderCount++ ;
6097	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6098	hcryp->CrypHeaderCount++ ;
6099	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6100	hcryp->CrypHeaderCount++ ;
6101	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6102	hcryp->CrypHeaderCount++ ;
6103
6104	/Wait on CCF flag/
6105	count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6106	do
6107	{
6108	count-- ;
6109	if (count == 0U)
6110	{
6111	/* Disable the CRYP peripheral clock */
6112	__HAL_CRYP_DISABLE(hcryp);
6113
6114	/* Change state */
6115	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
6116	hcryp->State = HAL_CRYP_STATE_READY;
6117
6118	/* Process unlocked */
6119	__HAL_UNLOCK(hcryp);
6120	return HAL_ERROR;
6121	}
6122	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6123
6124	/* Clear CCF flag */
6125	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6126	}
6127	}
6128	else
6129	{
6130	/Write header block in the IN FIFO without last block /
6131	for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
6132	{
6133	/* Write the Input block in the Data Input register */
6134	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6135	hcryp->CrypHeaderCount++ ;
6136	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6137	hcryp->CrypHeaderCount++ ;
6138	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6139	hcryp->CrypHeaderCount++ ;
6140	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6141	hcryp->CrypHeaderCount++ ;
6142
6143	/Wait on CCF flag/
6144	count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6145	do
6146	{
6147	count-- ;
6148	if (count == 0U)
6149	{
6150	/* Disable the CRYP peripheral clock */
6151	__HAL_CRYP_DISABLE(hcryp);
6152
6153	/* Change state */
6154	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
6155	hcryp->State = HAL_CRYP_STATE_READY;
6156
6157	/* Process unlocked */
6158	__HAL_UNLOCK(hcryp);
6159	return HAL_ERROR;
6160	}
6161	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6162
6163	/* Clear CCF flag */
6164	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6165	}
6166	/* Last block optionally pad the data with zeros*/
6167	for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes /4U) % 4U)); loopcounter++)
6168	{
6169	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6170	hcryp->CrypHeaderCount++ ;
6171	}
6172	/* If the header size is a multiple of words */
6173	if ((headersize_in_bytes % 4U) == 0U)
6174	{
6175	/* Pad the data with zeros to have a complete block */
6176	while (loopcounter < 4U)
6177	{
6178	hcryp->Instance->DINR = 0x0U;
6179	loopcounter++;
6180	}
6181	}
6182	else
6183	{
6184	/* Enter last bytes, padded with zeroes */
6185	tmp = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6186	tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6187	hcryp->Instance->DINR = tmp;
6188	loopcounter++;
6189	/* Pad the data with zeros to have a complete block */
6190	while (loopcounter < 4U)
6191	{
6192	hcryp->Instance->DINR = 0x0U;
6193	loopcounter++;
6194	}
6195	}
6196	/Wait on CCF flag/
6197	count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6198	do
6199	{
6200	count-- ;
6201	if (count == 0U)
6202	{
6203	/* Disable the CRYP peripheral clock */
6204	__HAL_CRYP_DISABLE(hcryp);
6205
6206	/* Change state */
6207	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
6208	hcryp->State = HAL_CRYP_STATE_READY;
6209
6210	/* Process unlocked */
6211	__HAL_UNLOCK(hcryp);
6212	return HAL_ERROR;
6213	}
6214	} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6215
6216	/* Clear CCF flag */
6217	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6218	}
6219	#endif /* End AES or CRYP */
6220	}
6221	else
6222	{
6223	#if defined(AES)
6224	if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6225	{
6226	/Workaround 1: only AES, before re-enabling the IP, datatype can be configured./
6227	MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
6228
6229	/* Select header phase */
6230	CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6231
6232	/* Enable the CRYP peripheral */
6233	__HAL_CRYP_ENABLE(hcryp);
6234	}
6235	#endif /* AES */
6236	}
6237	/* Return function status */
6238	return HAL_OK;
6239	}
6240
6241	/**
6242	* @brief Sets the header phase in interrupt mode
6243	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6244	* the configuration information for CRYP module(Header & HeaderSize)
6245	* @retval None
6246	*/
6247	static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
6248	{
6249	uint32_t loopcounter;
6250	#if defined(AES)
6251	uint32_t lastwordsize;
6252	uint32_t npblb;
6253	#endif
6254	uint32_t headersize_in_bytes;
6255	uint32_t tmp;
6256	uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
6257	0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
6258	0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
6259
6260	if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
6261	{
6262	headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
6263	}
6264	else
6265	{
6266	headersize_in_bytes = hcryp->Init.HeaderSize;
6267	}
6268
6269	/*************************** Header phase *******************************/
6270
6271	#if defined(CRYP)
6272	if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
6273	{
6274	/* Disable interrupts */
6275	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
6276
6277	/* Disable the CRYP peripheral */
6278	__HAL_CRYP_DISABLE(hcryp);
6279
6280	/* Set the phase */
6281	hcryp->Phase = CRYP_PHASE_PROCESS;
6282
6283	/* Select payload phase once the header phase is performed */
6284	CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
6285
6286	/* Enable Interrupts */
6287	__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI \| CRYP_IT_OUTI);
6288
6289	/* Enable the CRYP peripheral */
6290	__HAL_CRYP_ENABLE(hcryp);
6291	}
6292	else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
6293
6294	{
6295	/* HeaderSize %4, no padding */
6296	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6297	hcryp->CrypHeaderCount++ ;
6298	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6299	hcryp->CrypHeaderCount++ ;
6300	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6301	hcryp->CrypHeaderCount++ ;
6302	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6303	hcryp->CrypHeaderCount++ ;
6304	}
6305	else
6306	{
6307	/* Last block optionally pad the data with zeros*/
6308	for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
6309	{
6310	hcryp->Instance->DIN = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6311	hcryp->CrypHeaderCount++ ;
6312	}
6313	if ((headersize_in_bytes % 4U) == 0U)
6314	{
6315	/* Pad the data with zeros to have a complete block */
6316	while (loopcounter < 4U)
6317	{
6318	hcryp->Instance->DIN = 0x0U;
6319	loopcounter++;
6320	hcryp->CrypHeaderCount++;
6321	}
6322	}
6323	else
6324	{
6325	/* Enter last bytes, padded with zeros */
6326	tmp = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6327	tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6328	hcryp->Instance->DIN = tmp;
6329	loopcounter++;
6330	hcryp->CrypHeaderCount++;
6331	/* Pad the data with zeros to have a complete block */
6332	while (loopcounter < 4U)
6333	{
6334	hcryp->Instance->DIN = 0x0U;
6335	loopcounter++;
6336	hcryp->CrypHeaderCount++;
6337	}
6338	}
6339	}
6340	#else /* AES */
6341
6342	if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
6343	{
6344	/* Set the phase */
6345	hcryp->Phase = CRYP_PHASE_PROCESS;
6346
6347	/* Payload phase not supported in CCM AES2 */
6348	if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6349	{
6350	/* Select payload phase once the header phase is performed */
6351	MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
6352	}
6353	if (hcryp->Init.Algorithm == CRYP_AES_CCM)
6354	{
6355	/* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
6356	hcryp->CrypHeaderCount++;
6357	}
6358	/* Write the payload Input block in the IN FIFO */
6359	if (hcryp->Size == 0U)
6360	{
6361	/* Disable interrupts */
6362	__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE \| CRYP_IT_ERRIE);
6363
6364	/* Change the CRYP state */
6365	hcryp->State = HAL_CRYP_STATE_READY;
6366
6367	/* Process unlocked */
6368	__HAL_UNLOCK(hcryp);
6369	}
6370	else if (hcryp->Size >= 16U)
6371	{
6372	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6373	hcryp->CrypInCount++;
6374	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6375	hcryp->CrypInCount++;
6376	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6377	hcryp->CrypInCount++;
6378	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6379	hcryp->CrypInCount++;
6380
6381	if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
6382	{
6383	/* Call the input data transfer complete callback */
6384	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6385	/Call registered Input complete callback/
6386	hcryp->InCpltCallback(hcryp);
6387	#else
6388	/Call legacy weak Input complete callback/
6389	HAL_CRYP_InCpltCallback(hcryp);
6390	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6391	}
6392	}
6393	else /* Size < 4 words : first block is the last block*/
6394	{
6395	/* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
6396	generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
6397	payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
6398
6399	/* Compute the number of padding bytes in last block of payload */
6400	npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6401
6402	/* Number of valid words (lastwordsize) in last block */
6403	if ((npblb % 4U) == 0U)
6404	{
6405	lastwordsize = (16U - npblb) / 4U;
6406	}
6407	else
6408	{
6409	lastwordsize = ((16U - npblb) / 4U) + 1U;
6410	}
6411
6412	/* Last block optionally pad the data with zeros*/
6413	for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6414	{
6415	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6416	hcryp->CrypInCount++;
6417	}
6418	while (loopcounter < 4U)
6419	{
6420	/* Pad the data with zeros to have a complete block */
6421	hcryp->Instance->DINR = 0x0U;
6422	loopcounter++;
6423	}
6424	}
6425	}
6426	else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
6427	{
6428	/* Write the input block in the IN FIFO */
6429	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6430	hcryp->CrypHeaderCount++;
6431	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6432	hcryp->CrypHeaderCount++;
6433	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6434	hcryp->CrypHeaderCount++;
6435	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6436	hcryp->CrypHeaderCount++;
6437	}
6438	else /HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0/
6439	{
6440	/* Last block optionally pad the data with zeros*/
6441	for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
6442	{
6443	hcryp->Instance->DINR = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6444	hcryp->CrypHeaderCount++ ;
6445	}
6446	/* If the header size is a multiple of words */
6447	if ((headersize_in_bytes % 4U) == 0U)
6448	{
6449	/* Pad the data with zeros to have a complete block */
6450	while (loopcounter < 4U)
6451	{
6452	hcryp->Instance->DINR = 0x0U;
6453	loopcounter++;
6454	hcryp->CrypHeaderCount++;
6455	}
6456	}
6457	else
6458	{
6459	/* Enter last bytes, padded with zeros */
6460	tmp = (uint32_t )(hcryp->Init.Header + hcryp->CrypHeaderCount);
6461	tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6462	hcryp->Instance->DINR = tmp;
6463	loopcounter++;
6464	hcryp->CrypHeaderCount++;
6465	/* Pad the data with zeros to have a complete block */
6466	while (loopcounter < 4U)
6467	{
6468	hcryp->Instance->DINR = 0x0U;
6469	loopcounter++;
6470	hcryp->CrypHeaderCount++;
6471	}
6472	}
6473	}
6474	#endif /* End AES or CRYP */
6475	}
6476
6477
6478	/**
6479	* @brief Workaround used for GCM/CCM mode.
6480	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6481	* the configuration information for CRYP module
6482	* @param Timeout: specify Timeout value
6483	* @retval None
6484	*/
6485	static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6486	{
6487	uint32_t lastwordsize;
6488	uint32_t npblb;
6489	#if defined(CRYP)
6490	uint32_t iv1temp;
6491	uint32_t temp[4] = {0};
6492	uint32_t temp2[4] = {0};
6493	#endif /* CRYP */
6494	uint32_t intermediate_data[4] = {0};
6495	uint32_t index;
6496
6497	/* Compute the number of padding bytes in last block of payload */
6498	npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6499
6500	/* Number of valid words (lastwordsize) in last block */
6501	if ((npblb % 4U) == 0U)
6502	{
6503	lastwordsize = (16U - npblb) / 4U;
6504	}
6505	else
6506	{
6507	lastwordsize = ((16U - npblb) / 4U) + 1U;
6508	}
6509
6510	#if defined(CRYP)
6511
6512	/* Workaround 2, case GCM encryption */
6513	if (hcryp->Init.Algorithm == CRYP_AES_GCM)
6514	{
6515	if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6516	{
6517	/*Workaround in order to properly compute authentication tags while doing
6518	a GCM encryption with the last block of payload size inferior to 128 bits*/
6519	/* Disable CRYP to start the final phase */
6520	__HAL_CRYP_DISABLE(hcryp);
6521
6522	/Update CRYP_IV1R register and ALGOMODE/
6523	hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U);
6524	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6525
6526	/* Enable CRYP to start the final phase */
6527	__HAL_CRYP_ENABLE(hcryp);
6528	}
6529	/* Last block optionally pad the data with zeros*/
6530	for (index = 0; index < lastwordsize; index ++)
6531	{
6532	/* Write the last input block in the IN FIFO */
6533	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6534	hcryp->CrypInCount++;
6535	}
6536	while (index < 4U)
6537	{
6538	/* Pad the data with zeros to have a complete block */
6539	hcryp->Instance->DIN = 0U;
6540	index++;
6541	}
6542	/* Wait for OFNE flag to be raised */
6543	if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6544	{
6545	/* Disable the CRYP peripheral clock */
6546	__HAL_CRYP_DISABLE(hcryp);
6547
6548	/* Change state */
6549	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
6550	hcryp->State = HAL_CRYP_STATE_READY;
6551
6552	/* Process Unlocked */
6553	__HAL_UNLOCK(hcryp);
6554	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6555	/Call registered error callback/
6556	hcryp->ErrorCallback(hcryp);
6557	#else
6558	/Call legacy weak error callback/
6559	HAL_CRYP_ErrorCallback(hcryp);
6560	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6561	}
6562	if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6563	{
6564	for (index = 0U; index < 4U; index++)
6565	{
6566	/* Read the output block from the output FIFO */
6567	intermediate_data[index] = hcryp->Instance->DOUT;
6568
6569	/* Intermediate data buffer to be used in for the workaround*/
6570	(uint32_t )(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6571	hcryp->CrypOutCount++;
6572	}
6573	}
6574
6575	if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6576	{
6577	/*workaround in order to properly compute authentication tags while doing
6578	a GCM encryption with the last block of payload size inferior to 128 bits*/
6579	/* Change the AES mode to GCM mode and Select Final phase */
6580	/* configured CHMOD GCM */
6581	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
6582
6583	/* configured final phase */
6584	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
6585
6586	if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
6587	{
6588	if ((npblb % 4U) == 1U)
6589	{
6590	intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6591	}
6592	if ((npblb % 4U) == 2U)
6593	{
6594	intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6595	}
6596	if ((npblb % 4U) == 3U)
6597	{
6598	intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6599	}
6600	}
6601	else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
6602	{
6603	if ((npblb % 4U) == 1U)
6604	{
6605	intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6606	}
6607	if ((npblb % 4U) == 2U)
6608	{
6609	intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6610	}
6611	if ((npblb % 4U) == 3U)
6612	{
6613	intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6614	}
6615	}
6616	else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
6617	{
6618	if ((npblb % 4U) == 1U)
6619	{
6620	intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6621	}
6622	if ((npblb % 4U) == 2U)
6623	{
6624	intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6625	}
6626	if ((npblb % 4U) == 3U)
6627	{
6628	intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6629	}
6630	}
6631	else /CRYP_DATATYPE_1B/
6632	{
6633	if ((npblb % 4U) == 1U)
6634	{
6635	intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6636	}
6637	if ((npblb % 4U) == 2U)
6638	{
6639	intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6640	}
6641	if ((npblb % 4U) == 3U)
6642	{
6643	intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6644	}
6645	}
6646	for (index = 0U; index < lastwordsize; index ++)
6647	{
6648	/Write the intermediate_data in the IN FIFO /
6649	hcryp->Instance->DIN = intermediate_data[index];
6650	}
6651	while (index < 4U)
6652	{
6653	/* Pad the data with zeros to have a complete block */
6654	hcryp->Instance->DIN = 0x0U;
6655	index++;
6656	}
6657	/* Wait for OFNE flag to be raised */
6658	if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6659	{
6660	/* Disable the CRYP peripheral clock */
6661	__HAL_CRYP_DISABLE(hcryp);
6662
6663	/* Change state */
6664	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
6665	hcryp->State = HAL_CRYP_STATE_READY;
6666
6667	/* Process unlocked */
6668	__HAL_UNLOCK(hcryp);
6669	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6670	/Call registered error callback/
6671	hcryp->ErrorCallback(hcryp);
6672	#else
6673	/Call legacy weak error callback/
6674	HAL_CRYP_ErrorCallback(hcryp);
6675	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6676	}
6677
6678	if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6679	{
6680	for (index = 0U; index < 4U; index++)
6681	{
6682	intermediate_data[index] = hcryp->Instance->DOUT;
6683	}
6684	}
6685	}
6686	} /* End of GCM encryption */
6687	else
6688	{
6689	/* Workaround 2, case CCM decryption, in order to properly compute
6690	authentication tags while doing a CCM decryption with the last block
6691	of payload size inferior to 128 bits*/
6692
6693	if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6694	{
6695	iv1temp = hcryp->Instance->CSGCMCCM7R;
6696
6697	/* Disable CRYP to start the final phase */
6698	__HAL_CRYP_DISABLE(hcryp);
6699
6700	temp[0] = hcryp->Instance->CSGCMCCM0R;
6701	temp[1] = hcryp->Instance->CSGCMCCM1R;
6702	temp[2] = hcryp->Instance->CSGCMCCM2R;
6703	temp[3] = hcryp->Instance->CSGCMCCM3R;
6704
6705	hcryp->Instance->IV1RR = iv1temp;
6706
6707	/* Configured CHMOD CTR */
6708	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6709
6710	/* Enable CRYP to start the final phase */
6711	__HAL_CRYP_ENABLE(hcryp);
6712	}
6713	/* Last block optionally pad the data with zeros*/
6714	for (index = 0; index < lastwordsize; index ++)
6715	{
6716	/* Write the last Input block in the IN FIFO */
6717	hcryp->Instance->DIN = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6718	hcryp->CrypInCount++;
6719	}
6720	while (index < 4U)
6721	{
6722	/* Pad the data with zeros to have a complete block */
6723	hcryp->Instance->DIN = 0U;
6724	index++;
6725	}
6726	/* Wait for OFNE flag to be raised */
6727	if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6728	{
6729	/* Disable the CRYP peripheral clock */
6730	__HAL_CRYP_DISABLE(hcryp);
6731
6732	/* Change state */
6733	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
6734	hcryp->State = HAL_CRYP_STATE_READY;
6735
6736	/* Process Unlocked */
6737	__HAL_UNLOCK(hcryp);
6738	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6739	/Call registered error callback/
6740	hcryp->ErrorCallback(hcryp);
6741	#else
6742	/Call legacy weak error callback/
6743	HAL_CRYP_ErrorCallback(hcryp);
6744	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6745	}
6746
6747	if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6748	{
6749	for (index = 0U; index < 4U; index++)
6750	{
6751	/* Read the Output block from the Output FIFO */
6752	intermediate_data[index] = hcryp->Instance->DOUT;
6753
6754	/intermediate data buffer to be used in for the workaround/
6755	(uint32_t )(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6756	hcryp->CrypOutCount++;
6757	}
6758	}
6759
6760	if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6761	{
6762	temp2[0] = hcryp->Instance->CSGCMCCM0R;
6763	temp2[1] = hcryp->Instance->CSGCMCCM1R;
6764	temp2[2] = hcryp->Instance->CSGCMCCM2R;
6765	temp2[3] = hcryp->Instance->CSGCMCCM3R;
6766
6767	/* configured CHMOD CCM */
6768	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
6769
6770	/* configured Header phase */
6771	MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
6772
6773	/set to zero the bits corresponding to the padded bits/
6774	for (index = lastwordsize; index < 4U; index ++)
6775	{
6776	intermediate_data[index] = 0U;
6777	}
6778	if ((npblb % 4U) == 1U)
6779	{
6780	intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6781	}
6782	if ((npblb % 4U) == 2U)
6783	{
6784	intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6785	}
6786	if ((npblb % 4U) == 3U)
6787	{
6788	intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6789	}
6790	for (index = 0U; index < 4U ; index ++)
6791	{
6792	intermediate_data[index] ^= temp[index];
6793	intermediate_data[index] ^= temp2[index];
6794	}
6795	for (index = 0U; index < 4U; index ++)
6796	{
6797	/* Write the last Input block in the IN FIFO */
6798	hcryp->Instance->DIN = intermediate_data[index] ;
6799	}
6800
6801	/* Wait for BUSY flag to be raised */
6802	if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
6803	{
6804	/* Disable the CRYP peripheral clock */
6805	__HAL_CRYP_DISABLE(hcryp);
6806
6807	/* Change state */
6808	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
6809	hcryp->State = HAL_CRYP_STATE_READY;
6810
6811	/* Process Unlocked */
6812	__HAL_UNLOCK(hcryp);
6813	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6814	/Call registered error callback/
6815	hcryp->ErrorCallback(hcryp);
6816	#else
6817	/Call legacy weak error callback/
6818	HAL_CRYP_ErrorCallback(hcryp);
6819	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6820	}
6821	}
6822	} /* End of CCM WKA*/
6823
6824	/* Process Unlocked */
6825	__HAL_UNLOCK(hcryp);
6826
6827	#else /* AES */
6828
6829	/*Workaround 2: case GCM encryption, during payload phase and before inserting
6830	the last block of paylaod, which size is inferior to 128 bits */
6831
6832	if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6833	{
6834	/* configured CHMOD CTR */
6835	MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
6836	}
6837	/* last block optionally pad the data with zeros*/
6838	for (index = 0U; index < lastwordsize; index ++)
6839	{
6840	/* Write the last Input block in the IN FIFO */
6841	hcryp->Instance->DINR = (uint32_t )(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6842	hcryp->CrypInCount++;
6843	}
6844	while (index < 4U)
6845	{
6846	/* pad the data with zeros to have a complete block */
6847	hcryp->Instance->DINR = 0U;
6848	index++;
6849	}
6850	/* Wait for CCF flag to be raised */
6851	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6852	{
6853	hcryp->State = HAL_CRYP_STATE_READY;
6854	__HAL_UNLOCK(hcryp);
6855	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6856	/Call registered error callback/
6857	hcryp->ErrorCallback(hcryp);
6858	#else
6859	/Call legacy weak error callback/
6860	HAL_CRYP_ErrorCallback(hcryp);
6861	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6862	}
6863
6864	/* Clear CCF Flag */
6865	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6866
6867	for (index = 0U; index < 4U; index++)
6868	{
6869	/* Read the Output block from the Output FIFO */
6870	intermediate_data[index] = hcryp->Instance->DOUTR;
6871
6872	/intermediate data buffer to be used in the workaround/
6873	(uint32_t )(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6874	hcryp->CrypOutCount++;
6875	}
6876
6877	if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6878	{
6879	/* configured CHMOD GCM */
6880	MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
6881
6882	/* Select final phase */
6883	MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
6884
6885	if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B)
6886	{
6887	if ((npblb % 4U) == 1U)
6888	{
6889	intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6890	}
6891	if ((npblb % 4U) == 2U)
6892	{
6893	intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6894	}
6895	if ((npblb % 4U) == 3U)
6896	{
6897	intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6898	}
6899	}
6900	else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B)
6901	{
6902	if ((npblb % 4U) == 1U)
6903	{
6904	intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6905	}
6906	if ((npblb % 4U) == 2U)
6907	{
6908	intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6909	}
6910	if ((npblb % 4U) == 3U)
6911	{
6912	intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6913	}
6914	}
6915	else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B)
6916	{
6917	if ((npblb % 4U) == 1U)
6918	{
6919	intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6920	}
6921	if ((npblb % 4U) == 2U)
6922	{
6923	intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6924	}
6925	if ((npblb % 4U) == 3U)
6926	{
6927	intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6928	}
6929	}
6930	else /CRYP_DATATYPE_1B/
6931	{
6932	if ((npblb % 4U) == 1U)
6933	{
6934	intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6935	}
6936	if ((npblb % 4U) == 2U)
6937	{
6938	intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6939	}
6940	if ((npblb % 4U) == 3U)
6941	{
6942	intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6943	}
6944	}
6945
6946	/Write the intermediate_data in the IN FIFO /
6947	for (index = 0U; index < lastwordsize; index ++)
6948	{
6949	hcryp->Instance->DINR = intermediate_data[index];
6950	}
6951	while (index < 4U)
6952	{
6953	/* pad the data with zeros to have a complete block */
6954	hcryp->Instance->DINR = 0U;
6955	index++;
6956	}
6957	/* Wait for CCF flag to be raised */
6958	if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6959	{
6960	/* Disable the CRYP peripheral clock */
6961	__HAL_CRYP_DISABLE(hcryp);
6962
6963	/* Change state */
6964	hcryp->ErrorCode \|= HAL_CRYP_ERROR_TIMEOUT;
6965	hcryp->State = HAL_CRYP_STATE_READY;
6966
6967	/* Process Unlocked */
6968	__HAL_UNLOCK(hcryp);
6969	#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6970	/Call registered error callback/
6971	hcryp->ErrorCallback(hcryp);
6972	#else
6973	/Call legacy weak error callback/
6974	HAL_CRYP_ErrorCallback(hcryp);
6975	#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6976	}
6977	/* Clear CCF Flag */
6978	__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6979
6980	for (index = 0U; index < 4U; index++)
6981	{
6982	intermediate_data[index] = hcryp->Instance->DOUTR;
6983	}
6984	}/End of Workaround 2/
6985	#endif /* End AES or CRYP */
6986	}
6987	#endif /* AES or GCM CCM defined*/
6988	#if defined (CRYP)
6989	#if defined (CRYP_CR_ALGOMODE_AES_GCM)
6990	/**
6991	* @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
6992	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6993	* the configuration information for CRYP module.
6994	* @param Timeout: Timeout duration.
6995	* @retval HAL status
6996	*/
6997	static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6998	{
6999	uint32_t tickstart;
7000
7001	/* Get timeout */
7002	tickstart = HAL_GetTick();
7003
7004	while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
7005	{
7006	/* Check for the Timeout */
7007	if (Timeout != HAL_MAX_DELAY)
7008	{
7009	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
7010	{
7011	return HAL_ERROR;
7012	}
7013	}
7014	}
7015	return HAL_OK;
7016	}
7017	#endif /* GCM CCM defined*/
7018	/**
7019	* @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
7020	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7021	* the configuration information for CRYP module.
7022	* @param Timeout: Timeout duration.
7023	* @retval HAL status
7024	*/
7025	static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7026	{
7027	uint32_t tickstart;
7028
7029	/* Get timeout */
7030	tickstart = HAL_GetTick();
7031
7032	while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
7033	{
7034	/* Check for the Timeout */
7035	if (Timeout != HAL_MAX_DELAY)
7036	{
7037	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
7038	{
7039	return HAL_ERROR;
7040	}
7041	}
7042	}
7043	return HAL_OK;
7044	}
7045
7046
7047	/**
7048	* @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
7049	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7050	* the configuration information for CRYP module.
7051	* @param Timeout: Timeout duration.
7052	* @retval HAL status
7053	*/
7054	static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7055	{
7056	uint32_t tickstart;
7057
7058	/* Get timeout */
7059	tickstart = HAL_GetTick();
7060
7061	while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
7062	{
7063	/* Check for the Timeout */
7064	if (Timeout != HAL_MAX_DELAY)
7065	{
7066	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
7067	{
7068	return HAL_ERROR;
7069	}
7070	}
7071	}
7072	return HAL_OK;
7073	}
7074
7075	#else /* AES */
7076
7077	/**
7078	* @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
7079	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7080	* the configuration information for CRYP module.
7081	* @param Timeout: Timeout duration.
7082	* @retval HAL status
7083	*/
7084	static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7085	{
7086	uint32_t tickstart;
7087
7088	/* Get timeout */
7089	tickstart = HAL_GetTick();
7090
7091	while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
7092	{
7093	/* Check for the Timeout */
7094	if (Timeout != HAL_MAX_DELAY)
7095	{
7096	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
7097	{
7098	return HAL_ERROR;
7099	}
7100	}
7101	}
7102	return HAL_OK;
7103	}
7104
7105	#endif /* End AES or CRYP */
7106
7107
7108	/**
7109	* @}
7110	*/
7111
7112
7113
7114	/**
7115	* @}
7116	*/
7117
7118	/**
7119	* @}
7120	*/
7121
7122	#endif /* HAL_CRYP_MODULE_ENABLED */
7123
7124
7125	/**
7126	* @}
7127	*/
7128	#endif /* TinyAES or CRYP*/
7129	/**
7130	* @}
7131	*/
7132
7133	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c

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