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stm32f4xx_hal_dsi.c

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_hal_dsi.c
4	* @author MCD Application Team
5	* @brief DSI HAL module driver.
6	* This file provides firmware functions to manage the following
7	* functionalities of the DSI peripheral:
8	* + Initialization and de-initialization functions
9	* + IO operation functions
10	* + Peripheral Control functions
11	* + Peripheral State and Errors functions
12	@verbatim
13	==============================================================================
14	##### How to use this driver #####
15	==============================================================================
16	[..]
17	The DSI HAL driver can be used as follows:
18
19	(#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef hdsi;
20
21	(#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API:
22	(##) Enable the DSI interface clock
23	(##) NVIC configuration if you need to use interrupt process
24	(+++) Configure the DSI interrupt priority
25	(+++) Enable the NVIC DSI IRQ Channel
26
27	(#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and
28	TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit().
29
30	* Configuration *
31	=========================
32	[..]
33	(#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
34	command mode.
35
36	(#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host.
37
38	(#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
39
40	(#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer().
41
42	(#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop().
43	Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively
44	to write DSI short packets, long packets and to read DSI packets.
45
46	(#) The DSI Host Offers two Low power modes :
47	(++) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
48	It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData()
49	and HAL_DSI_ExitULPMData()
50
51	(++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
52	It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM()
53	and HAL_DSI_ExitULPM()
54
55	(#) To control DSI state you can use the following function: HAL_DSI_GetState()
56
57	* Error management *
58	========================
59	[..]
60	(#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor()
61	When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve
62	the error code by calling function HAL_DSI_GetError()
63
64	* DSI HAL driver macros list *
65	=============================================
66	[..]
67	Below the list of most used macros in DSI HAL driver.
68
69	(+) __HAL_DSI_ENABLE: Enable the DSI Host.
70	(+) __HAL_DSI_DISABLE: Disable the DSI Host.
71	(+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper.
72	(+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper.
73	(+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL.
74	(+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL.
75	(+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator.
76	(+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator.
77	(+) __HAL_DSI_GET_FLAG: Get the DSI pending flags.
78	(+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags.
79	(+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts.
80	(+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
81	(+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.
82
83	[..]
84	(@) You can refer to the DSI HAL driver header file for more useful macros
85
86	* Callback registration *
87	=============================================
88	[..]
89	The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
90	allows the user to configure dynamically the driver callbacks.
91	Use Function HAL_DSI_RegisterCallback() to register a callback.
92
93	[..]
94	Function HAL_DSI_RegisterCallback() allows to register following callbacks:
95	(+) TearingEffectCallback : DSI Tearing Effect Callback.
96	(+) EndOfRefreshCallback : DSI End Of Refresh Callback.
97	(+) ErrorCallback : DSI Error Callback
98	(+) MspInitCallback : DSI MspInit.
99	(+) MspDeInitCallback : DSI MspDeInit.
100	[..]
101	This function takes as parameters the HAL peripheral handle, the callback ID
102	and a pointer to the user callback function.
103
104	[..]
105	Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default
106	weak function.
107	HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
108	and the callback ID.
109	[..]
110	This function allows to reset following callbacks:
111	(+) TearingEffectCallback : DSI Tearing Effect Callback.
112	(+) EndOfRefreshCallback : DSI End Of Refresh Callback.
113	(+) ErrorCallback : DSI Error Callback
114	(+) MspInitCallback : DSI MspInit.
115	(+) MspDeInitCallback : DSI MspDeInit.
116
117	[..]
118	By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
119	all callbacks are set to the corresponding weak functions:
120	examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
121	Exception done for MspInit and MspDeInit functions that are respectively
122	reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
123	and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
124	If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
125	keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
126
127	[..]
128	Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
129	Exception done MspInit/MspDeInit that can be registered/unregistered
130	in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
131	thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
132	In that case first register the MspInit/MspDeInit user callbacks
133	using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit()
134	or HAL_DSI_Init() function.
135
136	[..]
137	When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
138	not defined, the callback registration feature is not available and all callbacks
139	are set to the corresponding weak functions.
140
141	@endverbatim
142	******************************************************************************
143	* @attention
144	*
145	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
146	* All rights reserved.</center></h2>
147	*
148	* This software component is licensed by ST under BSD 3-Clause license,
149	* the "License"; You may not use this file except in compliance with the
150	* License. You may obtain a copy of the License at:
151	* opensource.org/licenses/BSD-3-Clause
152	*
153	******************************************************************************
154	*/
155
156	/* Includes ------------------------------------------------------------------*/
157	#include "stm32f4xx_hal.h"
158
159	/** @addtogroup STM32F4xx_HAL_Driver
160	* @{
161	*/
162
163	#ifdef HAL_DSI_MODULE_ENABLED
164
165	#if defined(DSI)
166
167	/** @addtogroup DSI
168	* @{
169	*/
170
171	/* Private types -------------------------------------------------------------*/
172	/* Private defines -----------------------------------------------------------*/
173	/** @addtogroup DSI_Private_Constants
174	* @{
175	*/
176	#define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
177
178	#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 \| DSI_ISR0_AE1 \| DSI_ISR0_AE2 \| DSI_ISR0_AE3 \| \
179	DSI_ISR0_AE4 \| DSI_ISR0_AE5 \| DSI_ISR0_AE6 \| DSI_ISR0_AE7 \| \
180	DSI_ISR0_AE8 \| DSI_ISR0_AE9 \| DSI_ISR0_AE10 \| DSI_ISR0_AE11 \| \
181	DSI_ISR0_AE12 \| DSI_ISR0_AE13 \| DSI_ISR0_AE14 \| DSI_ISR0_AE15)
182	#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 \| DSI_ISR0_PE1 \| DSI_ISR0_PE2 \| DSI_ISR0_PE3 \| DSI_ISR0_PE4)
183	#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
184	#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
185	#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE \| DSI_ISR1_ECCME)
186	#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
187	#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
188	#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
189	#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
190	#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE \| DSI_ISR1_GPWRE \| DSI_ISR1_GPTXE \| DSI_ISR1_GPRDE \| DSI_ISR1_GPRXE)
191	/**
192	* @}
193	*/
194
195	/* Private variables ---------------------------------------------------------*/
196	/* Private constants ---------------------------------------------------------*/
197	/* Private macros ------------------------------------------------------------*/
198	/* Private function prototypes -----------------------------------------------*/
199	static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0,
200	uint32_t Data1);
201
202	static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
203	uint32_t ChannelID,
204	uint32_t Mode,
205	uint32_t Param1,
206	uint32_t Param2);
207
208	/* Private functions ---------------------------------------------------------*/
209	/**
210	* @brief Generic DSI packet header configuration
211	* @param DSIx Pointer to DSI register base
212	* @param ChannelID Virtual channel ID of the header packet
213	* @param DataType Packet data type of the header packet
214	* This parameter can be any value of :
215	* @arg DSI_SHORT_WRITE_PKT_Data_Type
216	* @arg DSI_LONG_WRITE_PKT_Data_Type
217	* @arg DSI_SHORT_READ_PKT_Data_Type
218	* @arg DSI_MAX_RETURN_PKT_SIZE
219	* @param Data0 Word count LSB
220	* @param Data1 Word count MSB
221	* @retval None
222	*/
223	static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
224	uint32_t ChannelID,
225	uint32_t DataType,
226	uint32_t Data0,
227	uint32_t Data1)
228	{
229	/* Update the DSI packet header with new information */
230	DSIx->GHCR = (DataType \| (ChannelID << 6U) \| (Data0 << 8U) \| (Data1 << 16U));
231	}
232
233	/**
234	* @brief write short DCS or short Generic command
235	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
236	* the configuration information for the DSI.
237	* @param ChannelID Virtual channel ID.
238	* @param Mode DSI short packet data type.
239	* This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
240	* @param Param1 DSC command or first generic parameter.
241	* This parameter can be any value of @arg DSI_DCS_Command or a
242	* generic command code.
243	* @param Param2 DSC parameter or second generic parameter.
244	* @retval HAL status
245	*/
246	static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
247	uint32_t ChannelID,
248	uint32_t Mode,
249	uint32_t Param1,
250	uint32_t Param2)
251	{
252	uint32_t tickstart;
253
254	/* Get tick */
255	tickstart = HAL_GetTick();
256
257	/* Wait for Command FIFO Empty */
258	while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
259	{
260	/* Check for the Timeout */
261	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
262	{
263	return HAL_TIMEOUT;
264	}
265	}
266
267	/* Configure the packet to send a short DCS command with 0 or 1 parameter */
268	/* Update the DSI packet header with new information */
269	hdsi->Instance->GHCR = (Mode \| (ChannelID << 6U) \| (Param1 << 8U) \| (Param2 << 16U));
270
271	return HAL_OK;
272	}
273
274	/* Exported functions --------------------------------------------------------*/
275	/** @addtogroup DSI_Exported_Functions
276	* @{
277	*/
278
279	/** @defgroup DSI_Group1 Initialization and Configuration functions
280	* @brief Initialization and Configuration functions
281	*
282	@verbatim
283	===============================================================================
284	##### Initialization and Configuration functions #####
285	===============================================================================
286	[..] This section provides functions allowing to:
287	(+) Initialize and configure the DSI
288	(+) De-initialize the DSI
289
290	@endverbatim
291	* @{
292	*/
293
294	/**
295	* @brief Initializes the DSI according to the specified
296	* parameters in the DSI_InitTypeDef and create the associated handle.
297	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
298	* the configuration information for the DSI.
299	* @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains
300	* the PLL Clock structure definition for the DSI.
301	* @retval HAL status
302	*/
303	HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef hdsi, DSI_PLLInitTypeDef PLLInit)
304	{
305	uint32_t tickstart;
306	uint32_t unitIntervalx4;
307	uint32_t tempIDF;
308
309	/* Check the DSI handle allocation */
310	if (hdsi == NULL)
311	{
312	return HAL_ERROR;
313	}
314
315	/* Check function parameters */
316	assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
317	assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
318	assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
319	assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
320	assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
321
322	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
323	if (hdsi->State == HAL_DSI_STATE_RESET)
324	{
325	/* Reset the DSI callback to the legacy weak callbacks */
326	hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
327	hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
328	hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
329
330	if (hdsi->MspInitCallback == NULL)
331	{
332	hdsi->MspInitCallback = HAL_DSI_MspInit;
333	}
334	/* Initialize the low level hardware */
335	hdsi->MspInitCallback(hdsi);
336	}
337	#else
338	if (hdsi->State == HAL_DSI_STATE_RESET)
339	{
340	/* Initialize the low level hardware */
341	HAL_DSI_MspInit(hdsi);
342	}
343	#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
344
345	/* Change DSI peripheral state */
346	hdsi->State = HAL_DSI_STATE_BUSY;
347
348	/************** Turn on the regulator and enable the DSI PLL **************/
349
350	/* Enable the regulator */
351	__HAL_DSI_REG_ENABLE(hdsi);
352
353	/* Get tick */
354	tickstart = HAL_GetTick();
355
356	/* Wait until the regulator is ready */
357	while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U)
358	{
359	/* Check for the Timeout */
360	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
361	{
362	return HAL_TIMEOUT;
363	}
364	}
365
366	/* Set the PLL division factors */
367	hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV \| DSI_WRPCR_PLL_IDF \| DSI_WRPCR_PLL_ODF);
368	hdsi->Instance->WRPCR \|= (((PLLInit->PLLNDIV) << 2U) \| ((PLLInit->PLLIDF) << 11U) \| ((PLLInit->PLLODF) << 16U));
369
370	/* Enable the DSI PLL */
371	__HAL_DSI_PLL_ENABLE(hdsi);
372
373	/* Get tick */
374	tickstart = HAL_GetTick();
375
376	/* Wait for the lock of the PLL */
377	while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
378	{
379	/* Check for the Timeout */
380	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
381	{
382	return HAL_TIMEOUT;
383	}
384	}
385
386	/************************* Set the PHY parameters *************************/
387
388	/* D-PHY clock and digital enable*/
389	hdsi->Instance->PCTLR \|= (DSI_PCTLR_CKE \| DSI_PCTLR_DEN);
390
391	/* Clock lane configuration */
392	hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC \| DSI_CLCR_ACR);
393	hdsi->Instance->CLCR \|= (DSI_CLCR_DPCC \| hdsi->Init.AutomaticClockLaneControl);
394
395	/* Configure the number of active data lanes */
396	hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
397	hdsi->Instance->PCONFR \|= hdsi->Init.NumberOfLanes;
398
399	/********************** Set the DSI clock parameters **********************/
400
401	/* Set the TX escape clock division factor */
402	hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
403	hdsi->Instance->CCR \|= hdsi->Init.TXEscapeCkdiv;
404
405	/* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
406	/* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
407	/* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
408	tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
409	unitIntervalx4 = (4000000U * tempIDF * ((1UL << (0x3U & PLLInit->PLLODF)))) / ((HSE_VALUE / 1000U) * PLLInit->PLLNDIV);
410
411	/* Set the bit period in high-speed mode */
412	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
413	hdsi->Instance->WPCR[0U] \|= unitIntervalx4;
414
415	/**************************** Error management ***************************/
416
417	/* Disable all error interrupts and reset the Error Mask */
418	hdsi->Instance->IER[0U] = 0U;
419	hdsi->Instance->IER[1U] = 0U;
420	hdsi->ErrorMsk = 0U;
421
422	/* Initialise the error code */
423	hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
424
425	/* Initialize the DSI state*/
426	hdsi->State = HAL_DSI_STATE_READY;
427
428	return HAL_OK;
429	}
430
431	/**
432	* @brief De-initializes the DSI peripheral registers to their default reset
433	* values.
434	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
435	* the configuration information for the DSI.
436	* @retval HAL status
437	*/
438	HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
439	{
440	/* Check the DSI handle allocation */
441	if (hdsi == NULL)
442	{
443	return HAL_ERROR;
444	}
445
446	/* Change DSI peripheral state */
447	hdsi->State = HAL_DSI_STATE_BUSY;
448
449	/* Disable the DSI wrapper */
450	__HAL_DSI_WRAPPER_DISABLE(hdsi);
451
452	/* Disable the DSI host */
453	__HAL_DSI_DISABLE(hdsi);
454
455	/* D-PHY clock and digital disable */
456	hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE \| DSI_PCTLR_DEN);
457
458	/* Turn off the DSI PLL */
459	__HAL_DSI_PLL_DISABLE(hdsi);
460
461	/* Disable the regulator */
462	__HAL_DSI_REG_DISABLE(hdsi);
463
464	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
465	if (hdsi->MspDeInitCallback == NULL)
466	{
467	hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;
468	}
469	/* DeInit the low level hardware */
470	hdsi->MspDeInitCallback(hdsi);
471	#else
472	/* DeInit the low level hardware */
473	HAL_DSI_MspDeInit(hdsi);
474	#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
475
476	/* Initialise the error code */
477	hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
478
479	/* Initialize the DSI state*/
480	hdsi->State = HAL_DSI_STATE_RESET;
481
482	/* Release Lock */
483	__HAL_UNLOCK(hdsi);
484
485	return HAL_OK;
486	}
487
488	/**
489	* @brief Enable the error monitor flags
490	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
491	* the configuration information for the DSI.
492	* @param ActiveErrors indicates which error interrupts will be enabled.
493	* This parameter can be any combination of @arg DSI_Error_Data_Type.
494	* @retval HAL status
495	*/
496	HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
497	{
498	/* Process locked */
499	__HAL_LOCK(hdsi);
500
501	hdsi->Instance->IER[0U] = 0U;
502	hdsi->Instance->IER[1U] = 0U;
503
504	/* Store active errors to the handle */
505	hdsi->ErrorMsk = ActiveErrors;
506
507	if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U)
508	{
509	/* Enable the interrupt generation on selected errors */
510	hdsi->Instance->IER[0U] \|= DSI_ERROR_ACK_MASK;
511	}
512
513	if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U)
514	{
515	/* Enable the interrupt generation on selected errors */
516	hdsi->Instance->IER[0U] \|= DSI_ERROR_PHY_MASK;
517	}
518
519	if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U)
520	{
521	/* Enable the interrupt generation on selected errors */
522	hdsi->Instance->IER[1U] \|= DSI_ERROR_TX_MASK;
523	}
524
525	if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U)
526	{
527	/* Enable the interrupt generation on selected errors */
528	hdsi->Instance->IER[1U] \|= DSI_ERROR_RX_MASK;
529	}
530
531	if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U)
532	{
533	/* Enable the interrupt generation on selected errors */
534	hdsi->Instance->IER[1U] \|= DSI_ERROR_ECC_MASK;
535	}
536
537	if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U)
538	{
539	/* Enable the interrupt generation on selected errors */
540	hdsi->Instance->IER[1U] \|= DSI_ERROR_CRC_MASK;
541	}
542
543	if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U)
544	{
545	/* Enable the interrupt generation on selected errors */
546	hdsi->Instance->IER[1U] \|= DSI_ERROR_PSE_MASK;
547	}
548
549	if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U)
550	{
551	/* Enable the interrupt generation on selected errors */
552	hdsi->Instance->IER[1U] \|= DSI_ERROR_EOT_MASK;
553	}
554
555	if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U)
556	{
557	/* Enable the interrupt generation on selected errors */
558	hdsi->Instance->IER[1U] \|= DSI_ERROR_OVF_MASK;
559	}
560
561	if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U)
562	{
563	/* Enable the interrupt generation on selected errors */
564	hdsi->Instance->IER[1U] \|= DSI_ERROR_GEN_MASK;
565	}
566
567	/* Process Unlocked */
568	__HAL_UNLOCK(hdsi);
569
570	return HAL_OK;
571	}
572
573	/**
574	* @brief Initializes the DSI MSP.
575	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
576	* the configuration information for the DSI.
577	* @retval None
578	*/
579	__weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi)
580	{
581	/* Prevent unused argument(s) compilation warning */
582	UNUSED(hdsi);
583	/* NOTE : This function Should not be modified, when the callback is needed,
584	the HAL_DSI_MspInit could be implemented in the user file
585	*/
586	}
587
588	/**
589	* @brief De-initializes the DSI MSP.
590	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
591	* the configuration information for the DSI.
592	* @retval None
593	*/
594	__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi)
595	{
596	/* Prevent unused argument(s) compilation warning */
597	UNUSED(hdsi);
598	/* NOTE : This function Should not be modified, when the callback is needed,
599	the HAL_DSI_MspDeInit could be implemented in the user file
600	*/
601	}
602
603	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
604	/**
605	* @brief Register a User DSI Callback
606	* To be used instead of the weak predefined callback
607	* @param hdsi dsi handle
608	* @param CallbackID ID of the callback to be registered
609	* This parameter can be one of the following values:
610	* @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
611	* @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
612	* @arg HAL_DSI_ERROR_CB_ID Error Callback ID
613	* @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
614	* @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
615	* @param pCallback pointer to the Callback function
616	* @retval status
617	*/
618	HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
619	pDSI_CallbackTypeDef pCallback)
620	{
621	HAL_StatusTypeDef status = HAL_OK;
622
623	if (pCallback == NULL)
624	{
625	/* Update the error code */
626	hdsi->ErrorCode \|= HAL_DSI_ERROR_INVALID_CALLBACK;
627
628	return HAL_ERROR;
629	}
630	/* Process locked */
631	__HAL_LOCK(hdsi);
632
633	if (hdsi->State == HAL_DSI_STATE_READY)
634	{
635	switch (CallbackID)
636	{
637	case HAL_DSI_TEARING_EFFECT_CB_ID :
638	hdsi->TearingEffectCallback = pCallback;
639	break;
640
641	case HAL_DSI_ENDOF_REFRESH_CB_ID :
642	hdsi->EndOfRefreshCallback = pCallback;
643	break;
644
645	case HAL_DSI_ERROR_CB_ID :
646	hdsi->ErrorCallback = pCallback;
647	break;
648
649	case HAL_DSI_MSPINIT_CB_ID :
650	hdsi->MspInitCallback = pCallback;
651	break;
652
653	case HAL_DSI_MSPDEINIT_CB_ID :
654	hdsi->MspDeInitCallback = pCallback;
655	break;
656
657	default :
658	/* Update the error code */
659	hdsi->ErrorCode \|= HAL_DSI_ERROR_INVALID_CALLBACK;
660	/* Return error status */
661	status = HAL_ERROR;
662	break;
663	}
664	}
665	else if (hdsi->State == HAL_DSI_STATE_RESET)
666	{
667	switch (CallbackID)
668	{
669	case HAL_DSI_MSPINIT_CB_ID :
670	hdsi->MspInitCallback = pCallback;
671	break;
672
673	case HAL_DSI_MSPDEINIT_CB_ID :
674	hdsi->MspDeInitCallback = pCallback;
675	break;
676
677	default :
678	/* Update the error code */
679	hdsi->ErrorCode \|= HAL_DSI_ERROR_INVALID_CALLBACK;
680	/* Return error status */
681	status = HAL_ERROR;
682	break;
683	}
684	}
685	else
686	{
687	/* Update the error code */
688	hdsi->ErrorCode \|= HAL_DSI_ERROR_INVALID_CALLBACK;
689	/* Return error status */
690	status = HAL_ERROR;
691	}
692
693	/* Release Lock */
694	__HAL_UNLOCK(hdsi);
695
696	return status;
697	}
698
699	/**
700	* @brief Unregister a DSI Callback
701	* DSI callabck is redirected to the weak predefined callback
702	* @param hdsi dsi handle
703	* @param CallbackID ID of the callback to be unregistered
704	* This parameter can be one of the following values:
705	* @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
706	* @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
707	* @arg HAL_DSI_ERROR_CB_ID Error Callback ID
708	* @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
709	* @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
710	* @retval status
711	*/
712	HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID)
713	{
714	HAL_StatusTypeDef status = HAL_OK;
715
716	/* Process locked */
717	__HAL_LOCK(hdsi);
718
719	if (hdsi->State == HAL_DSI_STATE_READY)
720	{
721	switch (CallbackID)
722	{
723	case HAL_DSI_TEARING_EFFECT_CB_ID :
724	hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
725	break;
726
727	case HAL_DSI_ENDOF_REFRESH_CB_ID :
728	hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
729	break;
730
731	case HAL_DSI_ERROR_CB_ID :
732	hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
733	break;
734
735	case HAL_DSI_MSPINIT_CB_ID :
736	hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
737	break;
738
739	case HAL_DSI_MSPDEINIT_CB_ID :
740	hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
741	break;
742
743	default :
744	/* Update the error code */
745	hdsi->ErrorCode \|= HAL_DSI_ERROR_INVALID_CALLBACK;
746	/* Return error status */
747	status = HAL_ERROR;
748	break;
749	}
750	}
751	else if (hdsi->State == HAL_DSI_STATE_RESET)
752	{
753	switch (CallbackID)
754	{
755	case HAL_DSI_MSPINIT_CB_ID :
756	hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
757	break;
758
759	case HAL_DSI_MSPDEINIT_CB_ID :
760	hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
761	break;
762
763	default :
764	/* Update the error code */
765	hdsi->ErrorCode \|= HAL_DSI_ERROR_INVALID_CALLBACK;
766	/* Return error status */
767	status = HAL_ERROR;
768	break;
769	}
770	}
771	else
772	{
773	/* Update the error code */
774	hdsi->ErrorCode \|= HAL_DSI_ERROR_INVALID_CALLBACK;
775	/* Return error status */
776	status = HAL_ERROR;
777	}
778
779	/* Release Lock */
780	__HAL_UNLOCK(hdsi);
781
782	return status;
783	}
784	#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
785
786	/**
787	* @}
788	*/
789
790	/** @defgroup DSI_Group2 IO operation functions
791	* @brief IO operation functions
792	*
793	@verbatim
794	===============================================================================
795	##### IO operation functions #####
796	===============================================================================
797	[..] This section provides function allowing to:
798	(+) Handle DSI interrupt request
799
800	@endverbatim
801	* @{
802	*/
803	/**
804	* @brief Handles DSI interrupt request.
805	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
806	* the configuration information for the DSI.
807	* @retval HAL status
808	*/
809	void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
810	{
811	uint32_t ErrorStatus0, ErrorStatus1;
812
813	/* Tearing Effect Interrupt management ***************************************/
814	if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
815	{
816	if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U)
817	{
818	/* Clear the Tearing Effect Interrupt Flag */
819	__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
820
821	/* Tearing Effect Callback */
822	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
823	/Call registered Tearing Effect callback /
824	hdsi->TearingEffectCallback(hdsi);
825	#else
826	/Call legacy Tearing Effect callback/
827	HAL_DSI_TearingEffectCallback(hdsi);
828	#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
829	}
830	}
831
832	/* End of Refresh Interrupt management ***************************************/
833	if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U)
834	{
835	if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U)
836	{
837	/* Clear the End of Refresh Interrupt Flag */
838	__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
839
840	/* End of Refresh Callback */
841	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
842	/Call registered End of refresh callback /
843	hdsi->EndOfRefreshCallback(hdsi);
844	#else
845	/Call Legacy End of refresh callback /
846	HAL_DSI_EndOfRefreshCallback(hdsi);
847	#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
848	}
849	}
850
851	/* Error Interrupts management ***********************************************/
852	if (hdsi->ErrorMsk != 0U)
853	{
854	ErrorStatus0 = hdsi->Instance->ISR[0U];
855	ErrorStatus0 &= hdsi->Instance->IER[0U];
856	ErrorStatus1 = hdsi->Instance->ISR[1U];
857	ErrorStatus1 &= hdsi->Instance->IER[1U];
858
859	if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U)
860	{
861	hdsi->ErrorCode \|= HAL_DSI_ERROR_ACK;
862	}
863
864	if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U)
865	{
866	hdsi->ErrorCode \|= HAL_DSI_ERROR_PHY;
867	}
868
869	if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U)
870	{
871	hdsi->ErrorCode \|= HAL_DSI_ERROR_TX;
872	}
873
874	if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U)
875	{
876	hdsi->ErrorCode \|= HAL_DSI_ERROR_RX;
877	}
878
879	if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U)
880	{
881	hdsi->ErrorCode \|= HAL_DSI_ERROR_ECC;
882	}
883
884	if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U)
885	{
886	hdsi->ErrorCode \|= HAL_DSI_ERROR_CRC;
887	}
888
889	if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U)
890	{
891	hdsi->ErrorCode \|= HAL_DSI_ERROR_PSE;
892	}
893
894	if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U)
895	{
896	hdsi->ErrorCode \|= HAL_DSI_ERROR_EOT;
897	}
898
899	if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U)
900	{
901	hdsi->ErrorCode \|= HAL_DSI_ERROR_OVF;
902	}
903
904	if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U)
905	{
906	hdsi->ErrorCode \|= HAL_DSI_ERROR_GEN;
907	}
908
909	/* Check only selected errors */
910	if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
911	{
912	/* DSI error interrupt callback */
913	#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
914	/Call registered Error callback /
915	hdsi->ErrorCallback(hdsi);
916	#else
917	/Call Legacy Error callback /
918	HAL_DSI_ErrorCallback(hdsi);
919	#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
920	}
921	}
922	}
923
924	/**
925	* @brief Tearing Effect DSI callback.
926	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
927	* the configuration information for the DSI.
928	* @retval None
929	*/
930	__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
931	{
932	/* Prevent unused argument(s) compilation warning */
933	UNUSED(hdsi);
934	/* NOTE : This function Should not be modified, when the callback is needed,
935	the HAL_DSI_TearingEffectCallback could be implemented in the user file
936	*/
937	}
938
939	/**
940	* @brief End of Refresh DSI callback.
941	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
942	* the configuration information for the DSI.
943	* @retval None
944	*/
945	__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
946	{
947	/* Prevent unused argument(s) compilation warning */
948	UNUSED(hdsi);
949	/* NOTE : This function Should not be modified, when the callback is needed,
950	the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
951	*/
952	}
953
954	/**
955	* @brief Operation Error DSI callback.
956	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
957	* the configuration information for the DSI.
958	* @retval None
959	*/
960	__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
961	{
962	/* Prevent unused argument(s) compilation warning */
963	UNUSED(hdsi);
964	/* NOTE : This function Should not be modified, when the callback is needed,
965	the HAL_DSI_ErrorCallback could be implemented in the user file
966	*/
967	}
968
969	/**
970	* @}
971	*/
972
973	/** @defgroup DSI_Group3 Peripheral Control functions
974	* @brief Peripheral Control functions
975	*
976	@verbatim
977	===============================================================================
978	##### Peripheral Control functions #####
979	===============================================================================
980	[..] This section provides functions allowing to:
981	(+) Configure the Generic interface read-back Virtual Channel ID
982	(+) Select video mode and configure the corresponding parameters
983	(+) Configure command transmission mode: High-speed or Low-power
984	(+) Configure the flow control
985	(+) Configure the DSI PHY timer
986	(+) Configure the DSI HOST timeout
987	(+) Configure the DSI HOST timeout
988	(+) Start/Stop the DSI module
989	(+) Refresh the display in command mode
990	(+) Controls the display color mode in Video mode
991	(+) Control the display shutdown in Video mode
992	(+) write short DCS or short Generic command
993	(+) write long DCS or long Generic command
994	(+) Read command (DCS or generic)
995	(+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running)
996	(+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off)
997	(+) Start/Stop test pattern generation
998	(+) Slew-Rate And Delay Tuning
999	(+) Low-Power Reception Filter Tuning
1000	(+) Activate an additional current path on all lanes to meet the SDDTx parameter
1001	(+) Custom lane pins configuration
1002	(+) Set custom timing for the PHY
1003	(+) Force the Clock/Data Lane in TX Stop Mode
1004	(+) Force LP Receiver in Low-Power Mode
1005	(+) Force Data Lanes in RX Mode after a BTA
1006	(+) Enable a pull-down on the lanes to prevent from floating states when unused
1007	(+) Switch off the contention detection on data lanes
1008
1009	@endverbatim
1010	* @{
1011	*/
1012
1013	/**
1014	* @brief Configure the Generic interface read-back Virtual Channel ID.
1015	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1016	* the configuration information for the DSI.
1017	* @param VirtualChannelID Virtual channel ID
1018	* @retval HAL status
1019	*/
1020	HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
1021	{
1022	/* Process locked */
1023	__HAL_LOCK(hdsi);
1024
1025	/* Update the GVCID register */
1026	hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
1027	hdsi->Instance->GVCIDR \|= VirtualChannelID;
1028
1029	/* Process unlocked */
1030	__HAL_UNLOCK(hdsi);
1031
1032	return HAL_OK;
1033	}
1034
1035	/**
1036	* @brief Select video mode and configure the corresponding parameters
1037	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1038	* the configuration information for the DSI.
1039	* @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
1040	* the DSI video mode configuration parameters
1041	* @retval HAL status
1042	*/
1043	HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef hdsi, DSI_VidCfgTypeDef VidCfg)
1044	{
1045	/* Process locked */
1046	__HAL_LOCK(hdsi);
1047
1048	/* Check the parameters */
1049	assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
1050	assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
1051	assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
1052	assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
1053	assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
1054	assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
1055	assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
1056	assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
1057	assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
1058	assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
1059	assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
1060	assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
1061	assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
1062	/* Check the LooselyPacked variant only in 18-bit mode */
1063	if (VidCfg->ColorCoding == DSI_RGB666)
1064	{
1065	assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
1066	}
1067
1068	/* Select video mode by resetting CMDM and DSIM bits */
1069	hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
1070	hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
1071
1072	/* Configure the video mode transmission type */
1073	hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
1074	hdsi->Instance->VMCR \|= VidCfg->Mode;
1075
1076	/* Configure the video packet size */
1077	hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
1078	hdsi->Instance->VPCR \|= VidCfg->PacketSize;
1079
1080	/* Set the chunks number to be transmitted through the DSI link */
1081	hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
1082	hdsi->Instance->VCCR \|= VidCfg->NumberOfChunks;
1083
1084	/* Set the size of the null packet */
1085	hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
1086	hdsi->Instance->VNPCR \|= VidCfg->NullPacketSize;
1087
1088	/* Select the virtual channel for the LTDC interface traffic */
1089	hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
1090	hdsi->Instance->LVCIDR \|= VidCfg->VirtualChannelID;
1091
1092	/* Configure the polarity of control signals */
1093	hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP \| DSI_LPCR_VSP \| DSI_LPCR_HSP);
1094	hdsi->Instance->LPCR \|= (VidCfg->DEPolarity \| VidCfg->VSPolarity \| VidCfg->HSPolarity);
1095
1096	/* Select the color coding for the host */
1097	hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
1098	hdsi->Instance->LCOLCR \|= VidCfg->ColorCoding;
1099
1100	/* Select the color coding for the wrapper */
1101	hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
1102	hdsi->Instance->WCFGR \|= ((VidCfg->ColorCoding) << 1U);
1103
1104	/* Enable/disable the loosely packed variant to 18-bit configuration */
1105	if (VidCfg->ColorCoding == DSI_RGB666)
1106	{
1107	hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
1108	hdsi->Instance->LCOLCR \|= VidCfg->LooselyPacked;
1109	}
1110
1111	/* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
1112	hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
1113	hdsi->Instance->VHSACR \|= VidCfg->HorizontalSyncActive;
1114
1115	/* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
1116	hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
1117	hdsi->Instance->VHBPCR \|= VidCfg->HorizontalBackPorch;
1118
1119	/* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
1120	hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
1121	hdsi->Instance->VLCR \|= VidCfg->HorizontalLine;
1122
1123	/* Set the Vertical Synchronization Active (VSA) */
1124	hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
1125	hdsi->Instance->VVSACR \|= VidCfg->VerticalSyncActive;
1126
1127	/* Set the Vertical Back Porch (VBP)*/
1128	hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
1129	hdsi->Instance->VVBPCR \|= VidCfg->VerticalBackPorch;
1130
1131	/* Set the Vertical Front Porch (VFP)*/
1132	hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
1133	hdsi->Instance->VVFPCR \|= VidCfg->VerticalFrontPorch;
1134
1135	/* Set the Vertical Active period*/
1136	hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
1137	hdsi->Instance->VVACR \|= VidCfg->VerticalActive;
1138
1139	/* Configure the command transmission mode */
1140	hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
1141	hdsi->Instance->VMCR \|= VidCfg->LPCommandEnable;
1142
1143	/* Low power largest packet size */
1144	hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
1145	hdsi->Instance->LPMCR \|= ((VidCfg->LPLargestPacketSize) << 16U);
1146
1147	/* Low power VACT largest packet size */
1148	hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
1149	hdsi->Instance->LPMCR \|= VidCfg->LPVACTLargestPacketSize;
1150
1151	/* Enable LP transition in HFP period */
1152	hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
1153	hdsi->Instance->VMCR \|= VidCfg->LPHorizontalFrontPorchEnable;
1154
1155	/* Enable LP transition in HBP period */
1156	hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
1157	hdsi->Instance->VMCR \|= VidCfg->LPHorizontalBackPorchEnable;
1158
1159	/* Enable LP transition in VACT period */
1160	hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
1161	hdsi->Instance->VMCR \|= VidCfg->LPVerticalActiveEnable;
1162
1163	/* Enable LP transition in VFP period */
1164	hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
1165	hdsi->Instance->VMCR \|= VidCfg->LPVerticalFrontPorchEnable;
1166
1167	/* Enable LP transition in VBP period */
1168	hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
1169	hdsi->Instance->VMCR \|= VidCfg->LPVerticalBackPorchEnable;
1170
1171	/* Enable LP transition in vertical sync period */
1172	hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
1173	hdsi->Instance->VMCR \|= VidCfg->LPVerticalSyncActiveEnable;
1174
1175	/* Enable the request for an acknowledge response at the end of a frame */
1176	hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
1177	hdsi->Instance->VMCR \|= VidCfg->FrameBTAAcknowledgeEnable;
1178
1179	/* Process unlocked */
1180	__HAL_UNLOCK(hdsi);
1181
1182	return HAL_OK;
1183	}
1184
1185	/**
1186	* @brief Select adapted command mode and configure the corresponding parameters
1187	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1188	* the configuration information for the DSI.
1189	* @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
1190	* the DSI command mode configuration parameters
1191	* @retval HAL status
1192	*/
1193	HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef hdsi, DSI_CmdCfgTypeDef CmdCfg)
1194	{
1195	/* Process locked */
1196	__HAL_LOCK(hdsi);
1197
1198	/* Check the parameters */
1199	assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
1200	assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
1201	assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
1202	assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
1203	assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
1204	assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
1205	assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
1206	assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
1207	assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
1208
1209	/* Select command mode by setting CMDM and DSIM bits */
1210	hdsi->Instance->MCR \|= DSI_MCR_CMDM;
1211	hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
1212	hdsi->Instance->WCFGR \|= DSI_WCFGR_DSIM;
1213
1214	/* Select the virtual channel for the LTDC interface traffic */
1215	hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
1216	hdsi->Instance->LVCIDR \|= CmdCfg->VirtualChannelID;
1217
1218	/* Configure the polarity of control signals */
1219	hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP \| DSI_LPCR_VSP \| DSI_LPCR_HSP);
1220	hdsi->Instance->LPCR \|= (CmdCfg->DEPolarity \| CmdCfg->VSPolarity \| CmdCfg->HSPolarity);
1221
1222	/* Select the color coding for the host */
1223	hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
1224	hdsi->Instance->LCOLCR \|= CmdCfg->ColorCoding;
1225
1226	/* Select the color coding for the wrapper */
1227	hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
1228	hdsi->Instance->WCFGR \|= ((CmdCfg->ColorCoding) << 1U);
1229
1230	/* Configure the maximum allowed size for write memory command */
1231	hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
1232	hdsi->Instance->LCCR \|= CmdCfg->CommandSize;
1233
1234	/* Configure the tearing effect source and polarity and select the refresh mode */
1235	hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC \| DSI_WCFGR_TEPOL \| DSI_WCFGR_AR \| DSI_WCFGR_VSPOL);
1236	hdsi->Instance->WCFGR \|= (CmdCfg->TearingEffectSource \| CmdCfg->TearingEffectPolarity \| CmdCfg->AutomaticRefresh \|
1237	CmdCfg->VSyncPol);
1238
1239	/* Configure the tearing effect acknowledge request */
1240	hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
1241	hdsi->Instance->CMCR \|= CmdCfg->TEAcknowledgeRequest;
1242
1243	/* Enable the Tearing Effect interrupt */
1244	__HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
1245
1246	/* Enable the End of Refresh interrupt */
1247	__HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
1248
1249	/* Process unlocked */
1250	__HAL_UNLOCK(hdsi);
1251
1252	return HAL_OK;
1253	}
1254
1255	/**
1256	* @brief Configure command transmission mode: High-speed or Low-power
1257	* and enable/disable acknowledge request after packet transmission
1258	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1259	* the configuration information for the DSI.
1260	* @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains
1261	* the DSI command transmission mode configuration parameters
1262	* @retval HAL status
1263	*/
1264	HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef hdsi, DSI_LPCmdTypeDef LPCmd)
1265	{
1266	/* Process locked */
1267	__HAL_LOCK(hdsi);
1268
1269	assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
1270	assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
1271	assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
1272	assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
1273	assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
1274	assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
1275	assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
1276	assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
1277	assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
1278	assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
1279	assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
1280	assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
1281	assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
1282
1283	/* Select High-speed or Low-power for command transmission */
1284	hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX \| \
1285	DSI_CMCR_GSW1TX \| \
1286	DSI_CMCR_GSW2TX \| \
1287	DSI_CMCR_GSR0TX \| \
1288	DSI_CMCR_GSR1TX \| \
1289	DSI_CMCR_GSR2TX \| \
1290	DSI_CMCR_GLWTX \| \
1291	DSI_CMCR_DSW0TX \| \
1292	DSI_CMCR_DSW1TX \| \
1293	DSI_CMCR_DSR0TX \| \
1294	DSI_CMCR_DLWTX \| \
1295	DSI_CMCR_MRDPS);
1296	hdsi->Instance->CMCR \|= (LPCmd->LPGenShortWriteNoP \| \
1297	LPCmd->LPGenShortWriteOneP \| \
1298	LPCmd->LPGenShortWriteTwoP \| \
1299	LPCmd->LPGenShortReadNoP \| \
1300	LPCmd->LPGenShortReadOneP \| \
1301	LPCmd->LPGenShortReadTwoP \| \
1302	LPCmd->LPGenLongWrite \| \
1303	LPCmd->LPDcsShortWriteNoP \| \
1304	LPCmd->LPDcsShortWriteOneP \| \
1305	LPCmd->LPDcsShortReadNoP \| \
1306	LPCmd->LPDcsLongWrite \| \
1307	LPCmd->LPMaxReadPacket);
1308
1309	/* Configure the acknowledge request after each packet transmission */
1310	hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
1311	hdsi->Instance->CMCR \|= LPCmd->AcknowledgeRequest;
1312
1313	/* Process unlocked */
1314	__HAL_UNLOCK(hdsi);
1315
1316	return HAL_OK;
1317	}
1318
1319	/**
1320	* @brief Configure the flow control parameters
1321	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1322	* the configuration information for the DSI.
1323	* @param FlowControl flow control feature(s) to be enabled.
1324	* This parameter can be any combination of @arg DSI_FlowControl.
1325	* @retval HAL status
1326	*/
1327	HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
1328	{
1329	/* Process locked */
1330	__HAL_LOCK(hdsi);
1331
1332	/* Check the parameters */
1333	assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
1334
1335	/* Set the DSI Host Protocol Configuration Register */
1336	hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
1337	hdsi->Instance->PCR \|= FlowControl;
1338
1339	/* Process unlocked */
1340	__HAL_UNLOCK(hdsi);
1341
1342	return HAL_OK;
1343	}
1344
1345	/**
1346	* @brief Configure the DSI PHY timer parameters
1347	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1348	* the configuration information for the DSI.
1349	* @param PhyTimers DSI_PHY_TimerTypeDef structure that contains
1350	* the DSI PHY timing parameters
1351	* @retval HAL status
1352	*/
1353	HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef hdsi, DSI_PHY_TimerTypeDef PhyTimers)
1354	{
1355	uint32_t maxTime;
1356	/* Process locked */
1357	__HAL_LOCK(hdsi);
1358
1359	maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime :
1360	PhyTimers->ClockLaneHS2LPTime;
1361
1362	/* Clock lane timer configuration */
1363
1364	/* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
1365	High-Speed transmission.
1366	To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
1367	to Low-Power and from Low-Power to High-Speed.
1368	This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
1369	But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
1370
1371	Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
1372	*/
1373	hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME \| DSI_CLTCR_HS2LP_TIME);
1374	hdsi->Instance->CLTCR \|= (maxTime \| ((maxTime) << 16U));
1375
1376	/* Data lane timer configuration */
1377	hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME \| DSI_DLTCR_LP2HS_TIME \| DSI_DLTCR_HS2LP_TIME);
1378	hdsi->Instance->DLTCR \|= (PhyTimers->DataLaneMaxReadTime \| ((PhyTimers->DataLaneLP2HSTime) << 16U) \| ((
1379	PhyTimers->DataLaneHS2LPTime) << 24U));
1380
1381	/* Configure the wait period to request HS transmission after a stop state */
1382	hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
1383	hdsi->Instance->PCONFR \|= ((PhyTimers->StopWaitTime) << 8U);
1384
1385	/* Process unlocked */
1386	__HAL_UNLOCK(hdsi);
1387
1388	return HAL_OK;
1389	}
1390
1391	/**
1392	* @brief Configure the DSI HOST timeout parameters
1393	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1394	* the configuration information for the DSI.
1395	* @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains
1396	* the DSI host timeout parameters
1397	* @retval HAL status
1398	*/
1399	HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef hdsi, DSI_HOST_TimeoutTypeDef HostTimeouts)
1400	{
1401	/* Process locked */
1402	__HAL_LOCK(hdsi);
1403
1404	/* Set the timeout clock division factor */
1405	hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
1406	hdsi->Instance->CCR \|= ((HostTimeouts->TimeoutCkdiv) << 8U);
1407
1408	/* High-speed transmission timeout */
1409	hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
1410	hdsi->Instance->TCCR[0U] \|= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U);
1411
1412	/* Low-power reception timeout */
1413	hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
1414	hdsi->Instance->TCCR[0U] \|= HostTimeouts->LowPowerReceptionTimeout;
1415
1416	/* High-speed read timeout */
1417	hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
1418	hdsi->Instance->TCCR[1U] \|= HostTimeouts->HighSpeedReadTimeout;
1419
1420	/* Low-power read timeout */
1421	hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
1422	hdsi->Instance->TCCR[2U] \|= HostTimeouts->LowPowerReadTimeout;
1423
1424	/* High-speed write timeout */
1425	hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
1426	hdsi->Instance->TCCR[3U] \|= HostTimeouts->HighSpeedWriteTimeout;
1427
1428	/* High-speed write presp mode */
1429	hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
1430	hdsi->Instance->TCCR[3U] \|= HostTimeouts->HighSpeedWritePrespMode;
1431
1432	/* Low-speed write timeout */
1433	hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
1434	hdsi->Instance->TCCR[4U] \|= HostTimeouts->LowPowerWriteTimeout;
1435
1436	/* BTA timeout */
1437	hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
1438	hdsi->Instance->TCCR[5U] \|= HostTimeouts->BTATimeout;
1439
1440	/* Process unlocked */
1441	__HAL_UNLOCK(hdsi);
1442
1443	return HAL_OK;
1444	}
1445
1446	/**
1447	* @brief Start the DSI module
1448	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1449	* the configuration information for the DSI.
1450	* @retval HAL status
1451	*/
1452	HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
1453	{
1454	/* Process locked */
1455	__HAL_LOCK(hdsi);
1456
1457	/* Enable the DSI host */
1458	__HAL_DSI_ENABLE(hdsi);
1459
1460	/* Enable the DSI wrapper */
1461	__HAL_DSI_WRAPPER_ENABLE(hdsi);
1462
1463	/* Process unlocked */
1464	__HAL_UNLOCK(hdsi);
1465
1466	return HAL_OK;
1467	}
1468
1469	/**
1470	* @brief Stop the DSI module
1471	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1472	* the configuration information for the DSI.
1473	* @retval HAL status
1474	*/
1475	HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
1476	{
1477	/* Process locked */
1478	__HAL_LOCK(hdsi);
1479
1480	/* Disable the DSI host */
1481	__HAL_DSI_DISABLE(hdsi);
1482
1483	/* Disable the DSI wrapper */
1484	__HAL_DSI_WRAPPER_DISABLE(hdsi);
1485
1486	/* Process unlocked */
1487	__HAL_UNLOCK(hdsi);
1488
1489	return HAL_OK;
1490	}
1491
1492	/**
1493	* @brief Refresh the display in command mode
1494	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1495	* the configuration information for the DSI.
1496	* @retval HAL status
1497	*/
1498	HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
1499	{
1500	/* Process locked */
1501	__HAL_LOCK(hdsi);
1502
1503	/* Update the display */
1504	hdsi->Instance->WCR \|= DSI_WCR_LTDCEN;
1505
1506	/* Process unlocked */
1507	__HAL_UNLOCK(hdsi);
1508
1509	return HAL_OK;
1510	}
1511
1512	/**
1513	* @brief Controls the display color mode in Video mode
1514	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1515	* the configuration information for the DSI.
1516	* @param ColorMode Color mode (full or 8-colors).
1517	* This parameter can be any value of @arg DSI_Color_Mode
1518	* @retval HAL status
1519	*/
1520	HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
1521	{
1522	/* Process locked */
1523	__HAL_LOCK(hdsi);
1524
1525	/* Check the parameters */
1526	assert_param(IS_DSI_COLOR_MODE(ColorMode));
1527
1528	/* Update the display color mode */
1529	hdsi->Instance->WCR &= ~DSI_WCR_COLM;
1530	hdsi->Instance->WCR \|= ColorMode;
1531
1532	/* Process unlocked */
1533	__HAL_UNLOCK(hdsi);
1534
1535	return HAL_OK;
1536	}
1537
1538	/**
1539	* @brief Control the display shutdown in Video mode
1540	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1541	* the configuration information for the DSI.
1542	* @param Shutdown Shut-down (Display-ON or Display-OFF).
1543	* This parameter can be any value of @arg DSI_ShutDown
1544	* @retval HAL status
1545	*/
1546	HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
1547	{
1548	/* Process locked */
1549	__HAL_LOCK(hdsi);
1550
1551	/* Check the parameters */
1552	assert_param(IS_DSI_SHUT_DOWN(Shutdown));
1553
1554	/* Update the display Shutdown */
1555	hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
1556	hdsi->Instance->WCR \|= Shutdown;
1557
1558	/* Process unlocked */
1559	__HAL_UNLOCK(hdsi);
1560
1561	return HAL_OK;
1562	}
1563
1564	/**
1565	* @brief write short DCS or short Generic command
1566	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1567	* the configuration information for the DSI.
1568	* @param ChannelID Virtual channel ID.
1569	* @param Mode DSI short packet data type.
1570	* This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
1571	* @param Param1 DSC command or first generic parameter.
1572	* This parameter can be any value of @arg DSI_DCS_Command or a
1573	* generic command code.
1574	* @param Param2 DSC parameter or second generic parameter.
1575	* @retval HAL status
1576	*/
1577	HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1578	uint32_t ChannelID,
1579	uint32_t Mode,
1580	uint32_t Param1,
1581	uint32_t Param2)
1582	{
1583	HAL_StatusTypeDef status;
1584	/* Check the parameters */
1585	assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
1586
1587	/* Process locked */
1588	__HAL_LOCK(hdsi);
1589
1590	status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
1591
1592	/* Process unlocked */
1593	__HAL_UNLOCK(hdsi);
1594
1595	return status;
1596	}
1597
1598	/**
1599	* @brief write long DCS or long Generic command
1600	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1601	* the configuration information for the DSI.
1602	* @param ChannelID Virtual channel ID.
1603	* @param Mode DSI long packet data type.
1604	* This parameter can be any value of @arg DSI_LONG_WRITE_PKT_Data_Type.
1605	* @param NbParams Number of parameters.
1606	* @param Param1 DSC command or first generic parameter.
1607	* This parameter can be any value of @arg DSI_DCS_Command or a
1608	* generic command code
1609	* @param ParametersTable Pointer to parameter values table.
1610	* @retval HAL status
1611	*/
1612	HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1613	uint32_t ChannelID,
1614	uint32_t Mode,
1615	uint32_t NbParams,
1616	uint32_t Param1,
1617	uint8_t *ParametersTable)
1618	{
1619	uint32_t uicounter, nbBytes, count;
1620	uint32_t tickstart;
1621	uint32_t fifoword;
1622	uint8_t *pparams = ParametersTable;
1623
1624	/* Process locked */
1625	__HAL_LOCK(hdsi);
1626
1627	/* Check the parameters */
1628	assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
1629
1630	/* Get tick */
1631	tickstart = HAL_GetTick();
1632
1633	/* Wait for Command FIFO Empty */
1634	while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
1635	{
1636	/* Check for the Timeout */
1637	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1638	{
1639	/* Process Unlocked */
1640	__HAL_UNLOCK(hdsi);
1641
1642	return HAL_TIMEOUT;
1643	}
1644	}
1645
1646	/* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
1647	fifoword = Param1;
1648	nbBytes = (NbParams < 3U) ? NbParams : 3U;
1649
1650	for (count = 0U; count < nbBytes; count++)
1651	{
1652	fifoword \|= (((uint32_t)((pparams + count))) << (8U + (8U count)));
1653	}
1654	hdsi->Instance->GPDR = fifoword;
1655
1656	uicounter = NbParams - nbBytes;
1657	pparams += nbBytes;
1658	/* Set the Next parameters on the write FIFO command*/
1659	while (uicounter != 0U)
1660	{
1661	nbBytes = (uicounter < 4U) ? uicounter : 4U;
1662	fifoword = 0U;
1663	for (count = 0U; count < nbBytes; count++)
1664	{
1665	fifoword \|= (((uint32_t)((pparams + count))) << (8U count));
1666	}
1667	hdsi->Instance->GPDR = fifoword;
1668
1669	uicounter -= nbBytes;
1670	pparams += nbBytes;
1671	}
1672
1673	/* Configure the packet to send a long DCS command */
1674	DSI_ConfigPacketHeader(hdsi->Instance,
1675	ChannelID,
1676	Mode,
1677	((NbParams + 1U) & 0x00FFU),
1678	(((NbParams + 1U) & 0xFF00U) >> 8U));
1679
1680	/* Process unlocked */
1681	__HAL_UNLOCK(hdsi);
1682
1683	return HAL_OK;
1684	}
1685
1686	/**
1687	* @brief Read command (DCS or generic)
1688	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1689	* the configuration information for the DSI.
1690	* @param ChannelNbr Virtual channel ID
1691	* @param Array pointer to a buffer to store the payload of a read back operation.
1692	* @param Size Data size to be read (in byte).
1693	* @param Mode DSI read packet data type.
1694	* This parameter can be any value of @arg DSI_SHORT_READ_PKT_Data_Type.
1695	* @param DCSCmd DCS get/read command.
1696	* @param ParametersTable Pointer to parameter values table.
1697	* @retval HAL status
1698	*/
1699	HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1700	uint32_t ChannelNbr,
1701	uint8_t *Array,
1702	uint32_t Size,
1703	uint32_t Mode,
1704	uint32_t DCSCmd,
1705	uint8_t *ParametersTable)
1706	{
1707	uint32_t tickstart;
1708	uint8_t *pdata = Array;
1709	uint32_t datasize = Size;
1710	uint32_t fifoword;
1711	uint32_t nbbytes;
1712	uint32_t count;
1713
1714	/* Process locked */
1715	__HAL_LOCK(hdsi);
1716
1717	/* Check the parameters */
1718	assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
1719
1720	if (datasize > 2U)
1721	{
1722	/* set max return packet size */
1723	if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
1724	(((datasize) >> 8U) & 0xFFU)) != HAL_OK)
1725	{
1726	/* Process Unlocked */
1727	__HAL_UNLOCK(hdsi);
1728
1729	return HAL_ERROR;
1730	}
1731	}
1732
1733	/* Configure the packet to read command */
1734	if (Mode == DSI_DCS_SHORT_PKT_READ)
1735	{
1736	DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
1737	}
1738	else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
1739	{
1740	DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
1741	}
1742	else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
1743	{
1744	DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
1745	}
1746	else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
1747	{
1748	DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
1749	}
1750	else
1751	{
1752	/* Process Unlocked */
1753	__HAL_UNLOCK(hdsi);
1754
1755	return HAL_ERROR;
1756	}
1757
1758	/* Get tick */
1759	tickstart = HAL_GetTick();
1760
1761	/* If DSI fifo is not empty, read requested bytes */
1762	while (((int32_t)(datasize)) > 0)
1763	{
1764	if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
1765	{
1766	fifoword = hdsi->Instance->GPDR;
1767	nbbytes = (datasize < 4U) ? datasize : 4U;
1768
1769	for (count = 0U; count < nbbytes; count++)
1770	{
1771	pdata = (uint8_t)(fifoword >> (8U count));
1772	pdata++;
1773	datasize--;
1774	}
1775	}
1776
1777	/* Check for the Timeout */
1778	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1779	{
1780	/* Process Unlocked */
1781	__HAL_UNLOCK(hdsi);
1782
1783	return HAL_TIMEOUT;
1784	}
1785	}
1786
1787	/* Process unlocked */
1788	__HAL_UNLOCK(hdsi);
1789
1790	return HAL_OK;
1791	}
1792
1793	/**
1794	* @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1795	* (only data lanes are in ULPM)
1796	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1797	* the configuration information for the DSI.
1798	* @retval HAL status
1799	*/
1800	HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
1801	{
1802	uint32_t tickstart;
1803
1804	/* Process locked */
1805	__HAL_LOCK(hdsi);
1806
1807	/* ULPS Request on Data Lanes */
1808	hdsi->Instance->PUCR \|= DSI_PUCR_URDL;
1809
1810	/* Get tick */
1811	tickstart = HAL_GetTick();
1812
1813	/* Wait until the D-PHY active lanes enter into ULPM */
1814	if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1815	{
1816	while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U)
1817	{
1818	/* Check for the Timeout */
1819	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1820	{
1821	/* Process Unlocked */
1822	__HAL_UNLOCK(hdsi);
1823
1824	return HAL_TIMEOUT;
1825	}
1826	}
1827	}
1828	else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1829	{
1830	while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UAN1)) != 0U)
1831	{
1832	/* Check for the Timeout */
1833	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1834	{
1835	/* Process Unlocked */
1836	__HAL_UNLOCK(hdsi);
1837
1838	return HAL_TIMEOUT;
1839	}
1840	}
1841	}
1842	else
1843	{
1844	/* Process unlocked */
1845	__HAL_UNLOCK(hdsi);
1846
1847	return HAL_ERROR;
1848	}
1849
1850	/* Process unlocked */
1851	__HAL_UNLOCK(hdsi);
1852
1853	return HAL_OK;
1854	}
1855
1856	/**
1857	* @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1858	* (only data lanes are in ULPM)
1859	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1860	* the configuration information for the DSI.
1861	* @retval HAL status
1862	*/
1863	HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
1864	{
1865	uint32_t tickstart;
1866
1867	/* Process locked */
1868	__HAL_LOCK(hdsi);
1869
1870	/* Exit ULPS on Data Lanes */
1871	hdsi->Instance->PUCR \|= DSI_PUCR_UEDL;
1872
1873	/* Get tick */
1874	tickstart = HAL_GetTick();
1875
1876	/* Wait until all active lanes exit ULPM */
1877	if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1878	{
1879	while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
1880	{
1881	/* Check for the Timeout */
1882	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1883	{
1884	/* Process Unlocked */
1885	__HAL_UNLOCK(hdsi);
1886
1887	return HAL_TIMEOUT;
1888	}
1889	}
1890	}
1891	else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1892	{
1893	while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UAN1)) != (DSI_PSR_UAN0 \| DSI_PSR_UAN1))
1894	{
1895	/* Check for the Timeout */
1896	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1897	{
1898	/* Process Unlocked */
1899	__HAL_UNLOCK(hdsi);
1900
1901	return HAL_TIMEOUT;
1902	}
1903	}
1904	}
1905	else
1906	{
1907	/* Process unlocked */
1908	__HAL_UNLOCK(hdsi);
1909
1910	return HAL_ERROR;
1911	}
1912
1913	/* wait for 1 ms*/
1914	HAL_Delay(1U);
1915
1916	/* De-assert the ULPM requests and the ULPM exit bits */
1917	hdsi->Instance->PUCR = 0U;
1918
1919	/* Process unlocked */
1920	__HAL_UNLOCK(hdsi);
1921
1922	return HAL_OK;
1923	}
1924
1925	/**
1926	* @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1927	* (both data and clock lanes are in ULPM)
1928	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1929	* the configuration information for the DSI.
1930	* @retval HAL status
1931	*/
1932	HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
1933	{
1934	uint32_t tickstart;
1935
1936	/* Process locked */
1937	__HAL_LOCK(hdsi);
1938
1939	/* Clock lane configuration: no more HS request */
1940	hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
1941
1942	/* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
1943	__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
1944
1945	/* ULPS Request on Clock and Data Lanes */
1946	hdsi->Instance->PUCR \|= (DSI_PUCR_URCL \| DSI_PUCR_URDL);
1947
1948	/* Get tick */
1949	tickstart = HAL_GetTick();
1950
1951	/* Wait until all active lanes exit ULPM */
1952	if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1953	{
1954	while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UANC)) != 0U)
1955	{
1956	/* Check for the Timeout */
1957	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1958	{
1959	/* Process Unlocked */
1960	__HAL_UNLOCK(hdsi);
1961
1962	return HAL_TIMEOUT;
1963	}
1964	}
1965	}
1966	else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1967	{
1968	while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UAN1 \| DSI_PSR_UANC)) != 0U)
1969	{
1970	/* Check for the Timeout */
1971	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
1972	{
1973	/* Process Unlocked */
1974	__HAL_UNLOCK(hdsi);
1975
1976	return HAL_TIMEOUT;
1977	}
1978	}
1979	}
1980	else
1981	{
1982	/* Process unlocked */
1983	__HAL_UNLOCK(hdsi);
1984
1985	return HAL_ERROR;
1986	}
1987
1988	/* Turn off the DSI PLL */
1989	__HAL_DSI_PLL_DISABLE(hdsi);
1990
1991	/* Process unlocked */
1992	__HAL_UNLOCK(hdsi);
1993
1994	return HAL_OK;
1995	}
1996
1997	/**
1998	* @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1999	* (both data and clock lanes are in ULPM)
2000	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2001	* the configuration information for the DSI.
2002	* @retval HAL status
2003	*/
2004	HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
2005	{
2006	uint32_t tickstart;
2007
2008	/* Process locked */
2009	__HAL_LOCK(hdsi);
2010
2011	/* Turn on the DSI PLL */
2012	__HAL_DSI_PLL_ENABLE(hdsi);
2013
2014	/* Get tick */
2015	tickstart = HAL_GetTick();
2016
2017	/* Wait for the lock of the PLL */
2018	while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
2019	{
2020	/* Check for the Timeout */
2021	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
2022	{
2023	/* Process Unlocked */
2024	__HAL_UNLOCK(hdsi);
2025
2026	return HAL_TIMEOUT;
2027	}
2028	}
2029
2030	/* Exit ULPS on Clock and Data Lanes */
2031	hdsi->Instance->PUCR \|= (DSI_PUCR_UECL \| DSI_PUCR_UEDL);
2032
2033	/* Get tick */
2034	tickstart = HAL_GetTick();
2035
2036	/* Wait until all active lanes exit ULPM */
2037	if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
2038	{
2039	while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UANC)) != (DSI_PSR_UAN0 \| DSI_PSR_UANC))
2040	{
2041	/* Check for the Timeout */
2042	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
2043	{
2044	/* Process Unlocked */
2045	__HAL_UNLOCK(hdsi);
2046
2047	return HAL_TIMEOUT;
2048	}
2049	}
2050	}
2051	else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
2052	{
2053	while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UAN1 \| DSI_PSR_UANC)) != (DSI_PSR_UAN0 \| DSI_PSR_UAN1 \|
2054	DSI_PSR_UANC))
2055	{
2056	/* Check for the Timeout */
2057	if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
2058	{
2059	/* Process Unlocked */
2060	__HAL_UNLOCK(hdsi);
2061
2062	return HAL_TIMEOUT;
2063	}
2064	}
2065	}
2066	else
2067	{
2068	/* Process unlocked */
2069	__HAL_UNLOCK(hdsi);
2070
2071	return HAL_ERROR;
2072	}
2073
2074	/* wait for 1 ms */
2075	HAL_Delay(1U);
2076
2077	/* De-assert the ULPM requests and the ULPM exit bits */
2078	hdsi->Instance->PUCR = 0U;
2079
2080	/* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
2081	__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
2082
2083	/* Restore clock lane configuration to HS */
2084	hdsi->Instance->CLCR \|= DSI_CLCR_DPCC;
2085
2086	/* Process unlocked */
2087	__HAL_UNLOCK(hdsi);
2088
2089	return HAL_OK;
2090	}
2091
2092	/**
2093	* @brief Start test pattern generation
2094	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2095	* the configuration information for the DSI.
2096	* @param Mode Pattern generator mode
2097	* This parameter can be one of the following values:
2098	* 0 : Color bars (horizontal or vertical)
2099	* 1 : BER pattern (vertical only)
2100	* @param Orientation Pattern generator orientation
2101	* This parameter can be one of the following values:
2102	* 0 : Vertical color bars
2103	* 1 : Horizontal color bars
2104	* @retval HAL status
2105	*/
2106	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
2107	{
2108	/* Process locked */
2109	__HAL_LOCK(hdsi);
2110
2111	/* Configure pattern generator mode and orientation */
2112	hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM \| DSI_VMCR_PGO);
2113	hdsi->Instance->VMCR \|= ((Mode << 20U) \| (Orientation << 24U));
2114
2115	/* Enable pattern generator by setting PGE bit */
2116	hdsi->Instance->VMCR \|= DSI_VMCR_PGE;
2117
2118	/* Process unlocked */
2119	__HAL_UNLOCK(hdsi);
2120
2121	return HAL_OK;
2122	}
2123
2124	/**
2125	* @brief Stop test pattern generation
2126	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2127	* the configuration information for the DSI.
2128	* @retval HAL status
2129	*/
2130	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
2131	{
2132	/* Process locked */
2133	__HAL_LOCK(hdsi);
2134
2135	/* Disable pattern generator by clearing PGE bit */
2136	hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
2137
2138	/* Process unlocked */
2139	__HAL_UNLOCK(hdsi);
2140
2141	return HAL_OK;
2142	}
2143
2144	/**
2145	* @brief Set Slew-Rate And Delay Tuning
2146	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2147	* the configuration information for the DSI.
2148	* @param CommDelay Communication delay to be adjusted.
2149	* This parameter can be any value of @arg DSI_Communication_Delay
2150	* @param Lane select between clock or data lanes.
2151	* This parameter can be any value of @arg DSI_Lane_Group
2152	* @param Value Custom value of the slew-rate or delay
2153	* @retval HAL status
2154	*/
2155	HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
2156	uint32_t Value)
2157	{
2158	/* Process locked */
2159	__HAL_LOCK(hdsi);
2160
2161	/* Check function parameters */
2162	assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
2163	assert_param(IS_DSI_LANE_GROUP(Lane));
2164
2165	switch (CommDelay)
2166	{
2167	case DSI_SLEW_RATE_HSTX:
2168	if (Lane == DSI_CLOCK_LANE)
2169	{
2170	/* High-Speed Transmission Slew Rate Control on Clock Lane */
2171	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
2172	hdsi->Instance->WPCR[1U] \|= Value << 16U;
2173	}
2174	else if (Lane == DSI_DATA_LANES)
2175	{
2176	/* High-Speed Transmission Slew Rate Control on Data Lanes */
2177	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
2178	hdsi->Instance->WPCR[1U] \|= Value << 18U;
2179	}
2180	else
2181	{
2182	/* Process unlocked */
2183	__HAL_UNLOCK(hdsi);
2184
2185	return HAL_ERROR;
2186	}
2187	break;
2188	case DSI_SLEW_RATE_LPTX:
2189	if (Lane == DSI_CLOCK_LANE)
2190	{
2191	/* Low-Power transmission Slew Rate Compensation on Clock Lane */
2192	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
2193	hdsi->Instance->WPCR[1U] \|= Value << 6U;
2194	}
2195	else if (Lane == DSI_DATA_LANES)
2196	{
2197	/* Low-Power transmission Slew Rate Compensation on Data Lanes */
2198	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
2199	hdsi->Instance->WPCR[1U] \|= Value << 8U;
2200	}
2201	else
2202	{
2203	/* Process unlocked */
2204	__HAL_UNLOCK(hdsi);
2205
2206	return HAL_ERROR;
2207	}
2208	break;
2209	case DSI_HS_DELAY:
2210	if (Lane == DSI_CLOCK_LANE)
2211	{
2212	/* High-Speed Transmission Delay on Clock Lane */
2213	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
2214	hdsi->Instance->WPCR[1U] \|= Value;
2215	}
2216	else if (Lane == DSI_DATA_LANES)
2217	{
2218	/* High-Speed Transmission Delay on Data Lanes */
2219	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
2220	hdsi->Instance->WPCR[1U] \|= Value << 2U;
2221	}
2222	else
2223	{
2224	/* Process unlocked */
2225	__HAL_UNLOCK(hdsi);
2226
2227	return HAL_ERROR;
2228	}
2229	break;
2230	default:
2231	break;
2232	}
2233
2234	/* Process unlocked */
2235	__HAL_UNLOCK(hdsi);
2236
2237	return HAL_OK;
2238	}
2239
2240	/**
2241	* @brief Low-Power Reception Filter Tuning
2242	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2243	* the configuration information for the DSI.
2244	* @param Frequency cutoff frequency of low-pass filter at the input of LPRX
2245	* @retval HAL status
2246	*/
2247	HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
2248	{
2249	/* Process locked */
2250	__HAL_LOCK(hdsi);
2251
2252	/* Low-Power RX low-pass Filtering Tuning */
2253	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
2254	hdsi->Instance->WPCR[1U] \|= Frequency << 25U;
2255
2256	/* Process unlocked */
2257	__HAL_UNLOCK(hdsi);
2258
2259	return HAL_OK;
2260	}
2261
2262	/**
2263	* @brief Activate an additional current path on all lanes to meet the SDDTx parameter
2264	* defined in the MIPI D-PHY specification
2265	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2266	* the configuration information for the DSI.
2267	* @param State ENABLE or DISABLE
2268	* @retval HAL status
2269	*/
2270	HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
2271	{
2272	/* Process locked */
2273	__HAL_LOCK(hdsi);
2274
2275	/* Check function parameters */
2276	assert_param(IS_FUNCTIONAL_STATE(State));
2277
2278	/* Activate/Disactivate additional current path on all lanes */
2279	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
2280	hdsi->Instance->WPCR[1U] \|= ((uint32_t)State << 12U);
2281
2282	/* Process unlocked */
2283	__HAL_UNLOCK(hdsi);
2284
2285	return HAL_OK;
2286	}
2287
2288	/**
2289	* @brief Custom lane pins configuration
2290	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2291	* the configuration information for the DSI.
2292	* @param CustomLane Function to be applied on selected lane.
2293	* This parameter can be any value of @arg DSI_CustomLane
2294	* @param Lane select between clock or data lane 0 or data lane 1.
2295	* This parameter can be any value of @arg DSI_Lane_Select
2296	* @param State ENABLE or DISABLE
2297	* @retval HAL status
2298	*/
2299	HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
2300	FunctionalState State)
2301	{
2302	/* Process locked */
2303	__HAL_LOCK(hdsi);
2304
2305	/* Check function parameters */
2306	assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
2307	assert_param(IS_DSI_LANE(Lane));
2308	assert_param(IS_FUNCTIONAL_STATE(State));
2309
2310	switch (CustomLane)
2311	{
2312	case DSI_SWAP_LANE_PINS:
2313	if (Lane == DSI_CLK_LANE)
2314	{
2315	/* Swap pins on clock lane */
2316	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
2317	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 6U);
2318	}
2319	else if (Lane == DSI_DATA_LANE0)
2320	{
2321	/* Swap pins on data lane 0 */
2322	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
2323	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 7U);
2324	}
2325	else if (Lane == DSI_DATA_LANE1)
2326	{
2327	/* Swap pins on data lane 1 */
2328	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
2329	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 8U);
2330	}
2331	else
2332	{
2333	/* Process unlocked */
2334	__HAL_UNLOCK(hdsi);
2335
2336	return HAL_ERROR;
2337	}
2338	break;
2339	case DSI_INVERT_HS_SIGNAL:
2340	if (Lane == DSI_CLK_LANE)
2341	{
2342	/* Invert HS signal on clock lane */
2343	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
2344	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 9U);
2345	}
2346	else if (Lane == DSI_DATA_LANE0)
2347	{
2348	/* Invert HS signal on data lane 0 */
2349	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
2350	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 10U);
2351	}
2352	else if (Lane == DSI_DATA_LANE1)
2353	{
2354	/* Invert HS signal on data lane 1 */
2355	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
2356	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 11U);
2357	}
2358	else
2359	{
2360	/* Process unlocked */
2361	__HAL_UNLOCK(hdsi);
2362
2363	return HAL_ERROR;
2364	}
2365	break;
2366	default:
2367	break;
2368	}
2369
2370	/* Process unlocked */
2371	__HAL_UNLOCK(hdsi);
2372
2373	return HAL_OK;
2374	}
2375
2376	/**
2377	* @brief Set custom timing for the PHY
2378	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2379	* the configuration information for the DSI.
2380	* @param Timing PHY timing to be adjusted.
2381	* This parameter can be any value of @arg DSI_PHY_Timing
2382	* @param State ENABLE or DISABLE
2383	* @param Value Custom value of the timing
2384	* @retval HAL status
2385	*/
2386	HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
2387	{
2388	/* Process locked */
2389	__HAL_LOCK(hdsi);
2390
2391	/* Check function parameters */
2392	assert_param(IS_DSI_PHY_TIMING(Timing));
2393	assert_param(IS_FUNCTIONAL_STATE(State));
2394
2395	switch (Timing)
2396	{
2397	case DSI_TCLK_POST:
2398	/* Enable/Disable custom timing setting */
2399	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
2400	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 27U);
2401
2402	if (State != DISABLE)
2403	{
2404	/* Set custom value */
2405	hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
2406	hdsi->Instance->WPCR[4U] \|= Value & DSI_WPCR4_TCLKPOST;
2407	}
2408
2409	break;
2410	case DSI_TLPX_CLK:
2411	/* Enable/Disable custom timing setting */
2412	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
2413	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 26U);
2414
2415	if (State != DISABLE)
2416	{
2417	/* Set custom value */
2418	hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
2419	hdsi->Instance->WPCR[3U] \|= (Value << 24U) & DSI_WPCR3_TLPXC;
2420	}
2421
2422	break;
2423	case DSI_THS_EXIT:
2424	/* Enable/Disable custom timing setting */
2425	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
2426	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 25U);
2427
2428	if (State != DISABLE)
2429	{
2430	/* Set custom value */
2431	hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
2432	hdsi->Instance->WPCR[3U] \|= (Value << 16U) & DSI_WPCR3_THSEXIT;
2433	}
2434
2435	break;
2436	case DSI_TLPX_DATA:
2437	/* Enable/Disable custom timing setting */
2438	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
2439	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 24U);
2440
2441	if (State != DISABLE)
2442	{
2443	/* Set custom value */
2444	hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
2445	hdsi->Instance->WPCR[3U] \|= (Value << 8U) & DSI_WPCR3_TLPXD;
2446	}
2447
2448	break;
2449	case DSI_THS_ZERO:
2450	/* Enable/Disable custom timing setting */
2451	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
2452	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 23U);
2453
2454	if (State != DISABLE)
2455	{
2456	/* Set custom value */
2457	hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
2458	hdsi->Instance->WPCR[3U] \|= Value & DSI_WPCR3_THSZERO;
2459	}
2460
2461	break;
2462	case DSI_THS_TRAIL:
2463	/* Enable/Disable custom timing setting */
2464	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
2465	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 22U);
2466
2467	if (State != DISABLE)
2468	{
2469	/* Set custom value */
2470	hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
2471	hdsi->Instance->WPCR[2U] \|= (Value << 24U) & DSI_WPCR2_THSTRAIL;
2472	}
2473
2474	break;
2475	case DSI_THS_PREPARE:
2476	/* Enable/Disable custom timing setting */
2477	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
2478	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 21U);
2479
2480	if (State != DISABLE)
2481	{
2482	/* Set custom value */
2483	hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
2484	hdsi->Instance->WPCR[2U] \|= (Value << 16U) & DSI_WPCR2_THSPREP;
2485	}
2486
2487	break;
2488	case DSI_TCLK_ZERO:
2489	/* Enable/Disable custom timing setting */
2490	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
2491	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 20U);
2492
2493	if (State != DISABLE)
2494	{
2495	/* Set custom value */
2496	hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
2497	hdsi->Instance->WPCR[2U] \|= (Value << 8U) & DSI_WPCR2_TCLKZERO;
2498	}
2499
2500	break;
2501	case DSI_TCLK_PREPARE:
2502	/* Enable/Disable custom timing setting */
2503	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
2504	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 19U);
2505
2506	if (State != DISABLE)
2507	{
2508	/* Set custom value */
2509	hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
2510	hdsi->Instance->WPCR[2U] \|= Value & DSI_WPCR2_TCLKPREP;
2511	}
2512
2513	break;
2514	default:
2515	break;
2516	}
2517
2518	/* Process unlocked */
2519	__HAL_UNLOCK(hdsi);
2520
2521	return HAL_OK;
2522	}
2523
2524	/**
2525	* @brief Force the Clock/Data Lane in TX Stop Mode
2526	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2527	* the configuration information for the DSI.
2528	* @param Lane select between clock or data lanes.
2529	* This parameter can be any value of @arg DSI_Lane_Group
2530	* @param State ENABLE or DISABLE
2531	* @retval HAL status
2532	*/
2533	HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
2534	{
2535	/* Process locked */
2536	__HAL_LOCK(hdsi);
2537
2538	/* Check function parameters */
2539	assert_param(IS_DSI_LANE_GROUP(Lane));
2540	assert_param(IS_FUNCTIONAL_STATE(State));
2541
2542	if (Lane == DSI_CLOCK_LANE)
2543	{
2544	/* Force/Unforce the Clock Lane in TX Stop Mode */
2545	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
2546	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 12U);
2547	}
2548	else if (Lane == DSI_DATA_LANES)
2549	{
2550	/* Force/Unforce the Data Lanes in TX Stop Mode */
2551	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
2552	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 13U);
2553	}
2554	else
2555	{
2556	/* Process unlocked */
2557	__HAL_UNLOCK(hdsi);
2558
2559	return HAL_ERROR;
2560	}
2561
2562	/* Process unlocked */
2563	__HAL_UNLOCK(hdsi);
2564
2565	return HAL_OK;
2566	}
2567
2568	/**
2569	* @brief Force LP Receiver in Low-Power Mode
2570	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2571	* the configuration information for the DSI.
2572	* @param State ENABLE or DISABLE
2573	* @retval HAL status
2574	*/
2575	HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
2576	{
2577	/* Process locked */
2578	__HAL_LOCK(hdsi);
2579
2580	/* Check function parameters */
2581	assert_param(IS_FUNCTIONAL_STATE(State));
2582
2583	/* Force/Unforce LP Receiver in Low-Power Mode */
2584	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
2585	hdsi->Instance->WPCR[1U] \|= ((uint32_t)State << 22U);
2586
2587	/* Process unlocked */
2588	__HAL_UNLOCK(hdsi);
2589
2590	return HAL_OK;
2591	}
2592
2593	/**
2594	* @brief Force Data Lanes in RX Mode after a BTA
2595	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2596	* the configuration information for the DSI.
2597	* @param State ENABLE or DISABLE
2598	* @retval HAL status
2599	*/
2600	HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
2601	{
2602	/* Process locked */
2603	__HAL_LOCK(hdsi);
2604
2605	/* Check function parameters */
2606	assert_param(IS_FUNCTIONAL_STATE(State));
2607
2608	/* Force Data Lanes in RX Mode */
2609	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
2610	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 16U);
2611
2612	/* Process unlocked */
2613	__HAL_UNLOCK(hdsi);
2614
2615	return HAL_OK;
2616	}
2617
2618	/**
2619	* @brief Enable a pull-down on the lanes to prevent from floating states when unused
2620	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2621	* the configuration information for the DSI.
2622	* @param State ENABLE or DISABLE
2623	* @retval HAL status
2624	*/
2625	HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
2626	{
2627	/* Process locked */
2628	__HAL_LOCK(hdsi);
2629
2630	/* Check function parameters */
2631	assert_param(IS_FUNCTIONAL_STATE(State));
2632
2633	/* Enable/Disable pull-down on lanes */
2634	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
2635	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 18U);
2636
2637	/* Process unlocked */
2638	__HAL_UNLOCK(hdsi);
2639
2640	return HAL_OK;
2641	}
2642
2643	/**
2644	* @brief Switch off the contention detection on data lanes
2645	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2646	* the configuration information for the DSI.
2647	* @param State ENABLE or DISABLE
2648	* @retval HAL status
2649	*/
2650	HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
2651	{
2652	/* Process locked */
2653	__HAL_LOCK(hdsi);
2654
2655	/* Check function parameters */
2656	assert_param(IS_FUNCTIONAL_STATE(State));
2657
2658	/* Contention Detection on Data Lanes OFF */
2659	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
2660	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 14U);
2661
2662	/* Process unlocked */
2663	__HAL_UNLOCK(hdsi);
2664
2665	return HAL_OK;
2666	}
2667
2668	/**
2669	* @}
2670	*/
2671
2672	/** @defgroup DSI_Group4 Peripheral State and Errors functions
2673	* @brief Peripheral State and Errors functions
2674	*
2675	@verbatim
2676	===============================================================================
2677	##### Peripheral State and Errors functions #####
2678	===============================================================================
2679	[..]
2680	This subsection provides functions allowing to
2681	(+) Check the DSI state.
2682	(+) Get error code.
2683
2684	@endverbatim
2685	* @{
2686	*/
2687
2688	/**
2689	* @brief Return the DSI state
2690	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2691	* the configuration information for the DSI.
2692	* @retval HAL state
2693	*/
2694	HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
2695	{
2696	return hdsi->State;
2697	}
2698
2699	/**
2700	* @brief Return the DSI error code
2701	* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2702	* the configuration information for the DSI.
2703	* @retval DSI Error Code
2704	*/
2705	uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
2706	{
2707	/* Get the error code */
2708	return hdsi->ErrorCode;
2709	}
2710
2711	/**
2712	* @}
2713	*/
2714
2715	/**
2716	* @}
2717	*/
2718
2719	/**
2720	* @}
2721	*/
2722
2723	#endif /* DSI */
2724
2725	#endif /* HAL_DSI_MODULE_ENABLED */
2726
2727	/**
2728	* @}
2729	*/
2730
2731	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c

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