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stm32f4xx_hal_eth.c

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_hal_eth.c
4	* @author MCD Application Team
5	* @brief ETH HAL module driver.
6	* This file provides firmware functions to manage the following
7	* functionalities of the Ethernet (ETH) peripheral:
8	* + Initialization and de-initialization functions
9	* + IO operation functions
10	* + Peripheral Control functions
11	* + Peripheral State and Errors functions
12	*
13	@verbatim
14	==============================================================================
15	##### How to use this driver #####
16	==============================================================================
17	[..]
18	(#)Declare a ETH_HandleTypeDef handle structure, for example:
19	ETH_HandleTypeDef heth;
20
21	(#)Fill parameters of Init structure in heth handle
22
23	(#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
24
25	(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
26	(##) Enable the Ethernet interface clock using
27	(+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
28	(+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
29	(+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
30
31	(##) Initialize the related GPIO clocks
32	(##) Configure Ethernet pin-out
33	(##) Configure Ethernet NVIC interrupt (IT mode)
34
35	(#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
36	(##) HAL_ETH_DMATxDescListInit(); for Transmission process
37	(##) HAL_ETH_DMARxDescListInit(); for Reception process
38
39	(#)Enable MAC and DMA transmission and reception:
40	(##) HAL_ETH_Start();
41
42	(#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
43	the frame to MAC TX FIFO:
44	(##) HAL_ETH_TransmitFrame();
45
46	(#)Poll for a received frame in ETH RX DMA Descriptors and get received
47	frame parameters
48	(##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
49
50	(#) Get a received frame when an ETH RX interrupt occurs:
51	(##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
52
53	(#) Communicate with external PHY device:
54	(##) Read a specific register from the PHY
55	HAL_ETH_ReadPHYRegister();
56	(##) Write data to a specific RHY register:
57	HAL_ETH_WritePHYRegister();
58
59	(#) Configure the Ethernet MAC after ETH peripheral initialization
60	HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
61
62	(#) Configure the Ethernet DMA after ETH peripheral initialization
63	HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
64
65	-@- The PTP protocol and the DMA descriptors ring mode are not supported
66	in this driver
67	* Callback registration *
68	=============================================
69
70	The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
71	allows the user to configure dynamically the driver callbacks.
72	Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
73
74	Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
75	(+) TxCpltCallback : Tx Complete Callback.
76	(+) RxCpltCallback : Rx Complete Callback.
77	(+) DMAErrorCallback : DMA Error Callback.
78	(+) MspInitCallback : MspInit Callback.
79	(+) MspDeInitCallback: MspDeInit Callback.
80
81	This function takes as parameters the HAL peripheral handle, the Callback ID
82	and a pointer to the user callback function.
83
84	Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
85	weak function.
86	@ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
87	and the Callback ID.
88	This function allows to reset following callbacks:
89	(+) TxCpltCallback : Tx Complete Callback.
90	(+) RxCpltCallback : Rx Complete Callback.
91	(+) DMAErrorCallback : DMA Error Callback.
92	(+) MspInitCallback : MspInit Callback.
93	(+) MspDeInitCallback: MspDeInit Callback.
94
95	By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
96	all callbacks are set to the corresponding weak functions:
97	examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
98	Exception done for MspInit and MspDeInit functions that are
99	reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
100	these callbacks are null (not registered beforehand).
101	if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
102	keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
103
104	Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
105	Exception done MspInit/MspDeInit that can be registered/unregistered
106	in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
107	thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
108	In that case first register the MspInit/MspDeInit user callbacks
109	using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
110	or HAL_ETH_Init function.
111
112	When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
113	not defined, the callback registration feature is not available and all callbacks
114	are set to the corresponding weak functions.
115
116	@endverbatim
117	******************************************************************************
118	* @attention
119	*
120	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
121	* All rights reserved.</center></h2>
122	*
123	* This software component is licensed by ST under BSD 3-Clause license,
124	* the "License"; You may not use this file except in compliance with the
125	* License. You may obtain a copy of the License at:
126	* opensource.org/licenses/BSD-3-Clause
127	*
128	******************************************************************************
129	*/
130
131	/* Includes ------------------------------------------------------------------*/
132	#include "stm32f4xx_hal.h"
133
134	/** @addtogroup STM32F4xx_HAL_Driver
135	* @{
136	*/
137
138	/** @defgroup ETH ETH
139	* @brief ETH HAL module driver
140	* @{
141	*/
142
143	#ifdef HAL_ETH_MODULE_ENABLED
144
145	#if defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\|\
146	defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
147
148	/* Private typedef -----------------------------------------------------------*/
149	/* Private define ------------------------------------------------------------*/
150	/** @defgroup ETH_Private_Constants ETH Private Constants
151	* @{
152	*/
153	#define ETH_TIMEOUT_SWRESET 500U
154	#define ETH_TIMEOUT_LINKED_STATE 5000U
155	#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
156
157	/**
158	* @}
159	*/
160	/* Private macro -------------------------------------------------------------*/
161	/* Private variables ---------------------------------------------------------*/
162	/* Private function prototypes -----------------------------------------------*/
163	/** @defgroup ETH_Private_Functions ETH Private Functions
164	* @{
165	*/
166	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
167	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr);
168	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
169	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
170	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
171	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
172	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
173	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
174	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
175	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
176	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
177	static void ETH_Delay(uint32_t mdelay);
178	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
179	static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
180	#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
181
182	/**
183	* @}
184	*/
185	/* Private functions ---------------------------------------------------------*/
186
187	/** @defgroup ETH_Exported_Functions ETH Exported Functions
188	* @{
189	*/
190
191	/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
192	* @brief Initialization and Configuration functions
193	*
194	@verbatim
195	===============================================================================
196	##### Initialization and de-initialization functions #####
197	===============================================================================
198	[..] This section provides functions allowing to:
199	(+) Initialize and configure the Ethernet peripheral
200	(+) De-initialize the Ethernet peripheral
201
202	@endverbatim
203	* @{
204	*/
205
206	/**
207	* @brief Initializes the Ethernet MAC and DMA according to default
208	* parameters.
209	* @param heth pointer to a ETH_HandleTypeDef structure that contains
210	* the configuration information for ETHERNET module
211	* @retval HAL status
212	*/
213	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
214	{
215	uint32_t tmpreg1 = 0U, phyreg = 0U;
216	uint32_t hclk = 60000000U;
217	uint32_t tickstart = 0U;
218	uint32_t err = ETH_SUCCESS;
219
220	/* Check the ETH peripheral state */
221	if(heth == NULL)
222	{
223	return HAL_ERROR;
224	}
225
226	/* Check parameters */
227	assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
228	assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
229	assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
230	assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
231
232	if(heth->State == HAL_ETH_STATE_RESET)
233	{
234	/* Allocate lock resource and initialize it */
235	heth->Lock = HAL_UNLOCKED;
236	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
237	ETH_InitCallbacksToDefault(heth);
238
239	if(heth->MspInitCallback == NULL)
240	{
241	/* Init the low level hardware : GPIO, CLOCK, NVIC. */
242	heth->MspInitCallback = HAL_ETH_MspInit;
243	}
244	heth->MspInitCallback(heth);
245
246	#else
247	/* Init the low level hardware : GPIO, CLOCK, NVIC. */
248	HAL_ETH_MspInit(heth);
249	#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
250	}
251
252	/* Enable SYSCFG Clock */
253	__HAL_RCC_SYSCFG_CLK_ENABLE();
254
255	/* Select MII or RMII Mode*/
256	SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
257	SYSCFG->PMC \|= (uint32_t)heth->Init.MediaInterface;
258
259	/* Ethernet Software reset */
260	/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
261	/* After reset all the registers holds their respective reset values */
262	(heth->Instance)->DMABMR \|= ETH_DMABMR_SR;
263
264	/* Get tick */
265	tickstart = HAL_GetTick();
266
267	/* Wait for software reset */
268	while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
269	{
270	/* Check for the Timeout */
271	if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
272	{
273	heth->State= HAL_ETH_STATE_TIMEOUT;
274
275	/* Process Unlocked */
276	__HAL_UNLOCK(heth);
277
278	/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
279	not available, please check your external PHY or the IO configuration */
280	return HAL_TIMEOUT;
281	}
282	}
283
284	/-------------------------------- MAC Initialization ----------------------/
285	/* Get the ETHERNET MACMIIAR value */
286	tmpreg1 = (heth->Instance)->MACMIIAR;
287	/* Clear CSR Clock Range CR[2:0] bits */
288	tmpreg1 &= ETH_MACMIIAR_CR_MASK;
289
290	/* Get hclk frequency value */
291	hclk = HAL_RCC_GetHCLKFreq();
292
293	/* Set CR bits depending on hclk value */
294	if((hclk >= 20000000U)&&(hclk < 35000000U))
295	{
296	/* CSR Clock Range between 20-35 MHz */
297	tmpreg1 \|= (uint32_t)ETH_MACMIIAR_CR_Div16;
298	}
299	else if((hclk >= 35000000U)&&(hclk < 60000000U))
300	{
301	/* CSR Clock Range between 35-60 MHz */
302	tmpreg1 \|= (uint32_t)ETH_MACMIIAR_CR_Div26;
303	}
304	else if((hclk >= 60000000U)&&(hclk < 100000000U))
305	{
306	/* CSR Clock Range between 60-100 MHz */
307	tmpreg1 \|= (uint32_t)ETH_MACMIIAR_CR_Div42;
308	}
309	else if((hclk >= 100000000U)&&(hclk < 150000000U))
310	{
311	/* CSR Clock Range between 100-150 MHz */
312	tmpreg1 \|= (uint32_t)ETH_MACMIIAR_CR_Div62;
313	}
314	else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */
315	{
316	/* CSR Clock Range between 150-183 MHz */
317	tmpreg1 \|= (uint32_t)ETH_MACMIIAR_CR_Div102;
318	}
319
320	/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
321	(heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
322
323	/-------------------- PHY initialization and configuration ----------------/
324	/* Put the PHY in reset mode */
325	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
326	{
327	/* In case of write timeout */
328	err = ETH_ERROR;
329
330	/* Config MAC and DMA */
331	ETH_MACDMAConfig(heth, err);
332
333	/* Set the ETH peripheral state to READY */
334	heth->State = HAL_ETH_STATE_READY;
335
336	/* Return HAL_ERROR */
337	return HAL_ERROR;
338	}
339
340	/* Delay to assure PHY reset */
341	HAL_Delay(PHY_RESET_DELAY);
342
343	if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
344	{
345	/* Get tick */
346	tickstart = HAL_GetTick();
347
348	/* We wait for linked status */
349	do
350	{
351	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
352
353	/* Check for the Timeout */
354	if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
355	{
356	/* In case of write timeout */
357	err = ETH_ERROR;
358
359	/* Config MAC and DMA */
360	ETH_MACDMAConfig(heth, err);
361
362	heth->State= HAL_ETH_STATE_READY;
363
364	/* Process Unlocked */
365	__HAL_UNLOCK(heth);
366
367	return HAL_TIMEOUT;
368	}
369	} while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
370
371
372	/* Enable Auto-Negotiation */
373	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
374	{
375	/* In case of write timeout */
376	err = ETH_ERROR;
377
378	/* Config MAC and DMA */
379	ETH_MACDMAConfig(heth, err);
380
381	/* Set the ETH peripheral state to READY */
382	heth->State = HAL_ETH_STATE_READY;
383
384	/* Return HAL_ERROR */
385	return HAL_ERROR;
386	}
387
388	/* Get tick */
389	tickstart = HAL_GetTick();
390
391	/* Wait until the auto-negotiation will be completed */
392	do
393	{
394	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
395
396	/* Check for the Timeout */
397	if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
398	{
399	/* In case of write timeout */
400	err = ETH_ERROR;
401
402	/* Config MAC and DMA */
403	ETH_MACDMAConfig(heth, err);
404
405	heth->State= HAL_ETH_STATE_READY;
406
407	/* Process Unlocked */
408	__HAL_UNLOCK(heth);
409
410	return HAL_TIMEOUT;
411	}
412
413	} while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
414
415	/* Read the result of the auto-negotiation */
416	if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
417	{
418	/* In case of write timeout */
419	err = ETH_ERROR;
420
421	/* Config MAC and DMA */
422	ETH_MACDMAConfig(heth, err);
423
424	/* Set the ETH peripheral state to READY */
425	heth->State = HAL_ETH_STATE_READY;
426
427	/* Return HAL_ERROR */
428	return HAL_ERROR;
429	}
430
431	/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
432	if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
433	{
434	/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
435	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
436	}
437	else
438	{
439	/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
440	(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
441	}
442	/* Configure the MAC with the speed fixed by the auto-negotiation process */
443	if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
444	{
445	/* Set Ethernet speed to 10M following the auto-negotiation */
446	(heth->Init).Speed = ETH_SPEED_10M;
447	}
448	else
449	{
450	/* Set Ethernet speed to 100M following the auto-negotiation */
451	(heth->Init).Speed = ETH_SPEED_100M;
452	}
453	}
454	else /* AutoNegotiation Disable */
455	{
456	/* Check parameters */
457	assert_param(IS_ETH_SPEED(heth->Init.Speed));
458	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
459
460	/* Set MAC Speed and Duplex Mode */
461	if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) \|
462	(uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
463	{
464	/* In case of write timeout */
465	err = ETH_ERROR;
466
467	/* Config MAC and DMA */
468	ETH_MACDMAConfig(heth, err);
469
470	/* Set the ETH peripheral state to READY */
471	heth->State = HAL_ETH_STATE_READY;
472
473	/* Return HAL_ERROR */
474	return HAL_ERROR;
475	}
476
477	/* Delay to assure PHY configuration */
478	HAL_Delay(PHY_CONFIG_DELAY);
479	}
480
481	/* Config MAC and DMA */
482	ETH_MACDMAConfig(heth, err);
483
484	/* Set ETH HAL State to Ready */
485	heth->State= HAL_ETH_STATE_READY;
486
487	/* Return function status */
488	return HAL_OK;
489	}
490
491	/**
492	* @brief De-Initializes the ETH peripheral.
493	* @param heth pointer to a ETH_HandleTypeDef structure that contains
494	* the configuration information for ETHERNET module
495	* @retval HAL status
496	*/
497	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
498	{
499	/* Set the ETH peripheral state to BUSY */
500	heth->State = HAL_ETH_STATE_BUSY;
501
502	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
503	if(heth->MspDeInitCallback == NULL)
504	{
505	heth->MspDeInitCallback = HAL_ETH_MspDeInit;
506	}
507	/* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
508	heth->MspDeInitCallback(heth);
509	#else
510	/* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
511	HAL_ETH_MspDeInit(heth);
512	#endif
513
514	/* Set ETH HAL state to Disabled */
515	heth->State= HAL_ETH_STATE_RESET;
516
517	/* Release Lock */
518	__HAL_UNLOCK(heth);
519
520	/* Return function status */
521	return HAL_OK;
522	}
523
524	/**
525	* @brief Initializes the DMA Tx descriptors in chain mode.
526	* @param heth pointer to a ETH_HandleTypeDef structure that contains
527	* the configuration information for ETHERNET module
528	* @param DMATxDescTab Pointer to the first Tx desc list
529	* @param TxBuff Pointer to the first TxBuffer list
530	* @param TxBuffCount Number of the used Tx desc in the list
531	* @retval HAL status
532	*/
533	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
534	{
535	uint32_t i = 0U;
536	ETH_DMADescTypeDef *dmatxdesc;
537
538	/* Process Locked */
539	__HAL_LOCK(heth);
540
541	/* Set the ETH peripheral state to BUSY */
542	heth->State = HAL_ETH_STATE_BUSY;
543
544	/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
545	heth->TxDesc = DMATxDescTab;
546
547	/* Fill each DMATxDesc descriptor with the right values */
548	for(i=0U; i < TxBuffCount; i++)
549	{
550	/* Get the pointer on the ith member of the Tx Desc list */
551	dmatxdesc = DMATxDescTab + i;
552
553	/* Set Second Address Chained bit */
554	dmatxdesc->Status = ETH_DMATXDESC_TCH;
555
556	/* Set Buffer1 address pointer */
557	dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
558
559	if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
560	{
561	/* Set the DMA Tx descriptors checksum insertion */
562	dmatxdesc->Status \|= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
563	}
564
565	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
566	if(i < (TxBuffCount-1U))
567	{
568	/* Set next descriptor address register with next descriptor base address */
569	dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
570	}
571	else
572	{
573	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
574	dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
575	}
576	}
577
578	/* Set Transmit Descriptor List Address Register */
579	(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
580
581	/* Set ETH HAL State to Ready */
582	heth->State= HAL_ETH_STATE_READY;
583
584	/* Process Unlocked */
585	__HAL_UNLOCK(heth);
586
587	/* Return function status */
588	return HAL_OK;
589	}
590
591	/**
592	* @brief Initializes the DMA Rx descriptors in chain mode.
593	* @param heth pointer to a ETH_HandleTypeDef structure that contains
594	* the configuration information for ETHERNET module
595	* @param DMARxDescTab Pointer to the first Rx desc list
596	* @param RxBuff Pointer to the first RxBuffer list
597	* @param RxBuffCount Number of the used Rx desc in the list
598	* @retval HAL status
599	*/
600	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
601	{
602	uint32_t i = 0U;
603	ETH_DMADescTypeDef *DMARxDesc;
604
605	/* Process Locked */
606	__HAL_LOCK(heth);
607
608	/* Set the ETH peripheral state to BUSY */
609	heth->State = HAL_ETH_STATE_BUSY;
610
611	/* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
612	heth->RxDesc = DMARxDescTab;
613
614	/* Fill each DMARxDesc descriptor with the right values */
615	for(i=0U; i < RxBuffCount; i++)
616	{
617	/* Get the pointer on the ith member of the Rx Desc list */
618	DMARxDesc = DMARxDescTab+i;
619
620	/* Set Own bit of the Rx descriptor Status */
621	DMARxDesc->Status = ETH_DMARXDESC_OWN;
622
623	/* Set Buffer1 size and Second Address Chained bit */
624	DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH \| ETH_RX_BUF_SIZE;
625
626	/* Set Buffer1 address pointer */
627	DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
628
629	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
630	{
631	/* Enable Ethernet DMA Rx Descriptor interrupt */
632	DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
633	}
634
635	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
636	if(i < (RxBuffCount-1U))
637	{
638	/* Set next descriptor address register with next descriptor base address */
639	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
640	}
641	else
642	{
643	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
644	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
645	}
646	}
647
648	/* Set Receive Descriptor List Address Register */
649	(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
650
651	/* Set ETH HAL State to Ready */
652	heth->State= HAL_ETH_STATE_READY;
653
654	/* Process Unlocked */
655	__HAL_UNLOCK(heth);
656
657	/* Return function status */
658	return HAL_OK;
659	}
660
661	/**
662	* @brief Initializes the ETH MSP.
663	* @param heth pointer to a ETH_HandleTypeDef structure that contains
664	* the configuration information for ETHERNET module
665	* @retval None
666	*/
667	__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
668	{
669	/* Prevent unused argument(s) compilation warning */
670	UNUSED(heth);
671	/* NOTE : This function Should not be modified, when the callback is needed,
672	the HAL_ETH_MspInit could be implemented in the user file
673	*/
674	}
675
676	/**
677	* @brief DeInitializes ETH MSP.
678	* @param heth pointer to a ETH_HandleTypeDef structure that contains
679	* the configuration information for ETHERNET module
680	* @retval None
681	*/
682	__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
683	{
684	/* Prevent unused argument(s) compilation warning */
685	UNUSED(heth);
686	/* NOTE : This function Should not be modified, when the callback is needed,
687	the HAL_ETH_MspDeInit could be implemented in the user file
688	*/
689	}
690
691	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
692	/**
693	* @brief Register a User ETH Callback
694	* To be used instead of the weak predefined callback
695	* @param heth eth handle
696	* @param CallbackID ID of the callback to be registered
697	* This parameter can be one of the following values:
698	* @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
699	* @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
700	* @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
701	* @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
702	* @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
703	* @param pCallback pointer to the Callback function
704	* @retval status
705	*/
706	HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
707	{
708	HAL_StatusTypeDef status = HAL_OK;
709
710	if(pCallback == NULL)
711	{
712	return HAL_ERROR;
713	}
714	/* Process locked */
715	__HAL_LOCK(heth);
716
717	if(heth->State == HAL_ETH_STATE_READY)
718	{
719	switch (CallbackID)
720	{
721	case HAL_ETH_TX_COMPLETE_CB_ID :
722	heth->TxCpltCallback = pCallback;
723	break;
724
725	case HAL_ETH_RX_COMPLETE_CB_ID :
726	heth->RxCpltCallback = pCallback;
727	break;
728
729	case HAL_ETH_DMA_ERROR_CB_ID :
730	heth->DMAErrorCallback = pCallback;
731	break;
732
733	case HAL_ETH_MSPINIT_CB_ID :
734	heth->MspInitCallback = pCallback;
735	break;
736
737	case HAL_ETH_MSPDEINIT_CB_ID :
738	heth->MspDeInitCallback = pCallback;
739	break;
740
741	default :
742	/* Return error status */
743	status = HAL_ERROR;
744	break;
745	}
746	}
747	else if(heth->State == HAL_ETH_STATE_RESET)
748	{
749	switch (CallbackID)
750	{
751	case HAL_ETH_MSPINIT_CB_ID :
752	heth->MspInitCallback = pCallback;
753	break;
754
755	case HAL_ETH_MSPDEINIT_CB_ID :
756	heth->MspDeInitCallback = pCallback;
757	break;
758
759	default :
760	/* Return error status */
761	status = HAL_ERROR;
762	break;
763	}
764	}
765	else
766	{
767	/* Return error status */
768	status = HAL_ERROR;
769	}
770
771	/* Release Lock */
772	__HAL_UNLOCK(heth);
773
774	return status;
775	}
776
777	/**
778	* @brief Unregister an ETH Callback
779	* ETH callabck is redirected to the weak predefined callback
780	* @param heth eth handle
781	* @param CallbackID ID of the callback to be unregistered
782	* This parameter can be one of the following values:
783	* @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
784	* @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
785	* @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
786	* @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
787	* @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
788	* @retval status
789	*/
790	HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
791	{
792	HAL_StatusTypeDef status = HAL_OK;
793
794	/* Process locked */
795	__HAL_LOCK(heth);
796
797	if(heth->State == HAL_ETH_STATE_READY)
798	{
799	switch (CallbackID)
800	{
801	case HAL_ETH_TX_COMPLETE_CB_ID :
802	heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
803	break;
804
805	case HAL_ETH_RX_COMPLETE_CB_ID :
806	heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
807	break;
808
809	case HAL_ETH_DMA_ERROR_CB_ID :
810	heth->DMAErrorCallback = HAL_ETH_ErrorCallback;
811	break;
812
813	case HAL_ETH_MSPINIT_CB_ID :
814	heth->MspInitCallback = HAL_ETH_MspInit;
815	break;
816
817	case HAL_ETH_MSPDEINIT_CB_ID :
818	heth->MspDeInitCallback = HAL_ETH_MspDeInit;
819	break;
820
821	default :
822	/* Return error status */
823	status = HAL_ERROR;
824	break;
825	}
826	}
827	else if(heth->State == HAL_ETH_STATE_RESET)
828	{
829	switch (CallbackID)
830	{
831	case HAL_ETH_MSPINIT_CB_ID :
832	heth->MspInitCallback = HAL_ETH_MspInit;
833	break;
834
835	case HAL_ETH_MSPDEINIT_CB_ID :
836	heth->MspDeInitCallback = HAL_ETH_MspDeInit;
837	break;
838
839	default :
840	/* Return error status */
841	status = HAL_ERROR;
842	break;
843	}
844	}
845	else
846	{
847	/* Return error status */
848	status = HAL_ERROR;
849	}
850
851	/* Release Lock */
852	__HAL_UNLOCK(heth);
853
854	return status;
855	}
856	#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
857
858	/**
859	* @}
860	*/
861
862	/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
863	* @brief Data transfers functions
864	*
865	@verbatim
866	==============================================================================
867	##### IO operation functions #####
868	==============================================================================
869	[..] This section provides functions allowing to:
870	(+) Transmit a frame
871	HAL_ETH_TransmitFrame();
872	(+) Receive a frame
873	HAL_ETH_GetReceivedFrame();
874	HAL_ETH_GetReceivedFrame_IT();
875	(+) Read from an External PHY register
876	HAL_ETH_ReadPHYRegister();
877	(+) Write to an External PHY register
878	HAL_ETH_WritePHYRegister();
879
880	@endverbatim
881
882	* @{
883	*/
884
885	/**
886	* @brief Sends an Ethernet frame.
887	* @param heth pointer to a ETH_HandleTypeDef structure that contains
888	* the configuration information for ETHERNET module
889	* @param FrameLength Amount of data to be sent
890	* @retval HAL status
891	*/
892	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
893	{
894	uint32_t bufcount = 0U, size = 0U, i = 0U;
895
896	/* Process Locked */
897	__HAL_LOCK(heth);
898
899	/* Set the ETH peripheral state to BUSY */
900	heth->State = HAL_ETH_STATE_BUSY;
901
902	if (FrameLength == 0U)
903	{
904	/* Set ETH HAL state to READY */
905	heth->State = HAL_ETH_STATE_READY;
906
907	/* Process Unlocked */
908	__HAL_UNLOCK(heth);
909
910	return HAL_ERROR;
911	}
912
913	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
914	if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
915	{
916	/* OWN bit set */
917	heth->State = HAL_ETH_STATE_BUSY_TX;
918
919	/* Process Unlocked */
920	__HAL_UNLOCK(heth);
921
922	return HAL_ERROR;
923	}
924
925	/* Get the number of needed Tx buffers for the current frame */
926	if (FrameLength > ETH_TX_BUF_SIZE)
927	{
928	bufcount = FrameLength/ETH_TX_BUF_SIZE;
929	if (FrameLength % ETH_TX_BUF_SIZE)
930	{
931	bufcount++;
932	}
933	}
934	else
935	{
936	bufcount = 1U;
937	}
938	if (bufcount == 1U)
939	{
940	/* Set LAST and FIRST segment */
941	heth->TxDesc->Status \|=ETH_DMATXDESC_FS\|ETH_DMATXDESC_LS;
942	/* Set frame size */
943	heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
944	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
945	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
946	/* Point to next descriptor */
947	heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
948	}
949	else
950	{
951	for (i=0U; i< bufcount; i++)
952	{
953	/* Clear FIRST and LAST segment bits */
954	heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS \| ETH_DMATXDESC_LS);
955
956	if (i == 0U)
957	{
958	/* Setting the first segment bit */
959	heth->TxDesc->Status \|= ETH_DMATXDESC_FS;
960	}
961
962	/* Program size */
963	heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
964
965	if (i == (bufcount-1U))
966	{
967	/* Setting the last segment bit */
968	heth->TxDesc->Status \|= ETH_DMATXDESC_LS;
969	size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
970	heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
971	}
972
973
974	/* point to next descriptor */
975	heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
976	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
977	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
978	}
979	}
980	__DSB();
981	/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
982	if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
983	{
984	/* Clear TBUS ETHERNET DMA flag */
985	(heth->Instance)->DMASR = ETH_DMASR_TBUS;
986	/* Resume DMA transmission*/
987	(heth->Instance)->DMATPDR = 0U;
988	}
989
990	/* Set ETH HAL State to Ready */
991	heth->State = HAL_ETH_STATE_READY;
992
993	/* Process Unlocked */
994	__HAL_UNLOCK(heth);
995
996	/* Return function status */
997	return HAL_OK;
998	}
999
1000	/**
1001	* @brief Checks for received frames.
1002	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1003	* the configuration information for ETHERNET module
1004	* @retval HAL status
1005	*/
1006	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
1007	{
1008	uint32_t framelength = 0U;
1009
1010	/* Process Locked */
1011	__HAL_LOCK(heth);
1012
1013	/* Check the ETH state to BUSY */
1014	heth->State = HAL_ETH_STATE_BUSY;
1015
1016	/* Check if segment is not owned by DMA */
1017	/* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
1018	if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
1019	{
1020	__DSB();
1021	/* Check if last segment */
1022	if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
1023	{
1024	/* increment segment count */
1025	(heth->RxFrameInfos).SegCount++;
1026
1027	/* Check if last segment is first segment: one segment contains the frame */
1028	if ((heth->RxFrameInfos).SegCount == 1U)
1029	{
1030	(heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
1031	}
1032
1033	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
1034
1035	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
1036	framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
1037	heth->RxFrameInfos.length = framelength;
1038
1039	/* Get the address of the buffer start address */
1040	heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
1041	/* point to next descriptor */
1042	heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
1043
1044	/* Set HAL State to Ready */
1045	heth->State = HAL_ETH_STATE_READY;
1046
1047	/* Process Unlocked */
1048	__HAL_UNLOCK(heth);
1049
1050	/* Return function status */
1051	return HAL_OK;
1052	}
1053	/* Check if first segment */
1054	else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
1055	{
1056	(heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
1057	(heth->RxFrameInfos).LSRxDesc = NULL;
1058	(heth->RxFrameInfos).SegCount = 1U;
1059	/* Point to next descriptor */
1060	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
1061	}
1062	/* Check if intermediate segment */
1063	else
1064	{
1065	(heth->RxFrameInfos).SegCount++;
1066	/* Point to next descriptor */
1067	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
1068	}
1069	}
1070
1071	/* Set ETH HAL State to Ready */
1072	heth->State = HAL_ETH_STATE_READY;
1073
1074	/* Process Unlocked */
1075	__HAL_UNLOCK(heth);
1076
1077	/* Return function status */
1078	return HAL_ERROR;
1079	}
1080
1081	/**
1082	* @brief Gets the Received frame in interrupt mode.
1083	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1084	* the configuration information for ETHERNET module
1085	* @retval HAL status
1086	*/
1087	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
1088	{
1089	uint32_t descriptorscancounter = 0U;
1090
1091	/* Process Locked */
1092	__HAL_LOCK(heth);
1093
1094	/* Set ETH HAL State to BUSY */
1095	heth->State = HAL_ETH_STATE_BUSY;
1096
1097	/* Scan descriptors owned by CPU */
1098	while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
1099	{
1100	/* Just for security */
1101	descriptorscancounter++;
1102
1103	/* Check if first segment in frame */
1104	/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
1105	if((heth->RxDesc->Status & (ETH_DMARXDESC_FS \| ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
1106	{
1107	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
1108	heth->RxFrameInfos.SegCount = 1U;
1109	/* Point to next descriptor */
1110	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
1111	}
1112	/* Check if intermediate segment */
1113	/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
1114	else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS \| ETH_DMARXDESC_FS)) == (uint32_t)RESET)
1115	{
1116	/* Increment segment count */
1117	(heth->RxFrameInfos.SegCount)++;
1118	/* Point to next descriptor */
1119	heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
1120	}
1121	/* Should be last segment */
1122	else
1123	{
1124	/* Last segment */
1125	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
1126
1127	/* Increment segment count */
1128	(heth->RxFrameInfos.SegCount)++;
1129
1130	/* Check if last segment is first segment: one segment contains the frame */
1131	if ((heth->RxFrameInfos.SegCount) == 1U)
1132	{
1133	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
1134	}
1135
1136	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
1137	heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
1138
1139	/* Get the address of the buffer start address */
1140	heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
1141
1142	/* Point to next descriptor */
1143	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
1144
1145	/* Set HAL State to Ready */
1146	heth->State = HAL_ETH_STATE_READY;
1147
1148	/* Process Unlocked */
1149	__HAL_UNLOCK(heth);
1150
1151	/* Return function status */
1152	return HAL_OK;
1153	}
1154	}
1155
1156	/* Set HAL State to Ready */
1157	heth->State = HAL_ETH_STATE_READY;
1158
1159	/* Process Unlocked */
1160	__HAL_UNLOCK(heth);
1161
1162	/* Return function status */
1163	return HAL_ERROR;
1164	}
1165
1166	/**
1167	* @brief This function handles ETH interrupt request.
1168	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1169	* the configuration information for ETHERNET module
1170	* @retval HAL status
1171	*/
1172	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
1173	{
1174	/* Frame received */
1175	if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
1176	{
1177	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1178	/Call registered Receive complete callback/
1179	heth->RxCpltCallback(heth);
1180	#else
1181	/* Receive complete callback */
1182	HAL_ETH_RxCpltCallback(heth);
1183	#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1184
1185	/* Clear the Eth DMA Rx IT pending bits */
1186	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
1187
1188	/* Set HAL State to Ready */
1189	heth->State = HAL_ETH_STATE_READY;
1190
1191	/* Process Unlocked */
1192	__HAL_UNLOCK(heth);
1193
1194	}
1195	/* Frame transmitted */
1196	else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
1197	{
1198	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1199	/* Call resgistered Transfer complete callback*/
1200	heth->TxCpltCallback(heth);
1201	#else
1202	/* Transfer complete callback */
1203	HAL_ETH_TxCpltCallback(heth);
1204	#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1205
1206	/* Clear the Eth DMA Tx IT pending bits */
1207	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
1208
1209	/* Set HAL State to Ready */
1210	heth->State = HAL_ETH_STATE_READY;
1211
1212	/* Process Unlocked */
1213	__HAL_UNLOCK(heth);
1214	}
1215
1216	/* Clear the interrupt flags */
1217	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
1218
1219	/* ETH DMA Error */
1220	if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
1221	{
1222	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1223	heth->DMAErrorCallback(heth);
1224	#else
1225	/* Ethernet Error callback */
1226	HAL_ETH_ErrorCallback(heth);
1227	#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1228
1229	/* Clear the interrupt flags */
1230	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
1231
1232	/* Set HAL State to Ready */
1233	heth->State = HAL_ETH_STATE_READY;
1234
1235	/* Process Unlocked */
1236	__HAL_UNLOCK(heth);
1237	}
1238	}
1239
1240	/**
1241	* @brief Tx Transfer completed callbacks.
1242	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1243	* the configuration information for ETHERNET module
1244	* @retval None
1245	*/
1246	__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
1247	{
1248	/* Prevent unused argument(s) compilation warning */
1249	UNUSED(heth);
1250	/* NOTE : This function Should not be modified, when the callback is needed,
1251	the HAL_ETH_TxCpltCallback could be implemented in the user file
1252	*/
1253	}
1254
1255	/**
1256	* @brief Rx Transfer completed callbacks.
1257	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1258	* the configuration information for ETHERNET module
1259	* @retval None
1260	*/
1261	__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
1262	{
1263	/* Prevent unused argument(s) compilation warning */
1264	UNUSED(heth);
1265	/* NOTE : This function Should not be modified, when the callback is needed,
1266	the HAL_ETH_TxCpltCallback could be implemented in the user file
1267	*/
1268	}
1269
1270	/**
1271	* @brief Ethernet transfer error callbacks
1272	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1273	* the configuration information for ETHERNET module
1274	* @retval None
1275	*/
1276	__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
1277	{
1278	/* Prevent unused argument(s) compilation warning */
1279	UNUSED(heth);
1280	/* NOTE : This function Should not be modified, when the callback is needed,
1281	the HAL_ETH_TxCpltCallback could be implemented in the user file
1282	*/
1283	}
1284
1285	/**
1286	* @brief Reads a PHY register
1287	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1288	* the configuration information for ETHERNET module
1289	* @param PHYReg PHY register address, is the index of one of the 32 PHY register.
1290	* This parameter can be one of the following values:
1291	* PHY_BCR: Transceiver Basic Control Register,
1292	* PHY_BSR: Transceiver Basic Status Register.
1293	* More PHY register could be read depending on the used PHY
1294	* @param RegValue PHY register value
1295	* @retval HAL status
1296	*/
1297	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue)
1298	{
1299	uint32_t tmpreg1 = 0U;
1300	uint32_t tickstart = 0U;
1301
1302	/* Check parameters */
1303	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1304
1305	/* Check the ETH peripheral state */
1306	if(heth->State == HAL_ETH_STATE_BUSY_RD)
1307	{
1308	return HAL_BUSY;
1309	}
1310	/* Set ETH HAL State to BUSY_RD */
1311	heth->State = HAL_ETH_STATE_BUSY_RD;
1312
1313	/* Get the ETHERNET MACMIIAR value */
1314	tmpreg1 = heth->Instance->MACMIIAR;
1315
1316	/* Keep only the CSR Clock Range CR[2:0] bits value */
1317	tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
1318
1319	/* Prepare the MII address register value */
1320	tmpreg1 \|=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1321	tmpreg1 \|=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1322	tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
1323	tmpreg1 \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1324
1325	/* Write the result value into the MII Address register */
1326	heth->Instance->MACMIIAR = tmpreg1;
1327
1328	/* Get tick */
1329	tickstart = HAL_GetTick();
1330
1331	/* Check for the Busy flag */
1332	while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1333	{
1334	/* Check for the Timeout */
1335	if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
1336	{
1337	heth->State= HAL_ETH_STATE_READY;
1338
1339	/* Process Unlocked */
1340	__HAL_UNLOCK(heth);
1341
1342	return HAL_TIMEOUT;
1343	}
1344
1345	tmpreg1 = heth->Instance->MACMIIAR;
1346	}
1347
1348	/* Get MACMIIDR value */
1349	*RegValue = (uint16_t)(heth->Instance->MACMIIDR);
1350
1351	/* Set ETH HAL State to READY */
1352	heth->State = HAL_ETH_STATE_READY;
1353
1354	/* Return function status */
1355	return HAL_OK;
1356	}
1357
1358	/**
1359	* @brief Writes to a PHY register.
1360	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1361	* the configuration information for ETHERNET module
1362	* @param PHYReg PHY register address, is the index of one of the 32 PHY register.
1363	* This parameter can be one of the following values:
1364	* PHY_BCR: Transceiver Control Register.
1365	* More PHY register could be written depending on the used PHY
1366	* @param RegValue the value to write
1367	* @retval HAL status
1368	*/
1369	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
1370	{
1371	uint32_t tmpreg1 = 0U;
1372	uint32_t tickstart = 0U;
1373
1374	/* Check parameters */
1375	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1376
1377	/* Check the ETH peripheral state */
1378	if(heth->State == HAL_ETH_STATE_BUSY_WR)
1379	{
1380	return HAL_BUSY;
1381	}
1382	/* Set ETH HAL State to BUSY_WR */
1383	heth->State = HAL_ETH_STATE_BUSY_WR;
1384
1385	/* Get the ETHERNET MACMIIAR value */
1386	tmpreg1 = heth->Instance->MACMIIAR;
1387
1388	/* Keep only the CSR Clock Range CR[2:0] bits value */
1389	tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
1390
1391	/* Prepare the MII register address value */
1392	tmpreg1 \|=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1393	tmpreg1 \|=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1394	tmpreg1 \|= ETH_MACMIIAR_MW; /* Set the write mode */
1395	tmpreg1 \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1396
1397	/* Give the value to the MII data register */
1398	heth->Instance->MACMIIDR = (uint16_t)RegValue;
1399
1400	/* Write the result value into the MII Address register */
1401	heth->Instance->MACMIIAR = tmpreg1;
1402
1403	/* Get tick */
1404	tickstart = HAL_GetTick();
1405
1406	/* Check for the Busy flag */
1407	while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1408	{
1409	/* Check for the Timeout */
1410	if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
1411	{
1412	heth->State= HAL_ETH_STATE_READY;
1413
1414	/* Process Unlocked */
1415	__HAL_UNLOCK(heth);
1416
1417	return HAL_TIMEOUT;
1418	}
1419
1420	tmpreg1 = heth->Instance->MACMIIAR;
1421	}
1422
1423	/* Set ETH HAL State to READY */
1424	heth->State = HAL_ETH_STATE_READY;
1425
1426	/* Return function status */
1427	return HAL_OK;
1428	}
1429
1430	/**
1431	* @}
1432	*/
1433
1434	/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
1435	* @brief Peripheral Control functions
1436	*
1437	@verbatim
1438	===============================================================================
1439	##### Peripheral Control functions #####
1440	===============================================================================
1441	[..] This section provides functions allowing to:
1442	(+) Enable MAC and DMA transmission and reception.
1443	HAL_ETH_Start();
1444	(+) Disable MAC and DMA transmission and reception.
1445	HAL_ETH_Stop();
1446	(+) Set the MAC configuration in runtime mode
1447	HAL_ETH_ConfigMAC();
1448	(+) Set the DMA configuration in runtime mode
1449	HAL_ETH_ConfigDMA();
1450
1451	@endverbatim
1452	* @{
1453	*/
1454
1455	/**
1456	* @brief Enables Ethernet MAC and DMA reception/transmission
1457	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1458	* the configuration information for ETHERNET module
1459	* @retval HAL status
1460	*/
1461	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
1462	{
1463	/* Process Locked */
1464	__HAL_LOCK(heth);
1465
1466	/* Set the ETH peripheral state to BUSY */
1467	heth->State = HAL_ETH_STATE_BUSY;
1468
1469	/* Enable transmit state machine of the MAC for transmission on the MII */
1470	ETH_MACTransmissionEnable(heth);
1471
1472	/* Enable receive state machine of the MAC for reception from the MII */
1473	ETH_MACReceptionEnable(heth);
1474
1475	/* Flush Transmit FIFO */
1476	ETH_FlushTransmitFIFO(heth);
1477
1478	/* Start DMA transmission */
1479	ETH_DMATransmissionEnable(heth);
1480
1481	/* Start DMA reception */
1482	ETH_DMAReceptionEnable(heth);
1483
1484	/* Set the ETH state to READY*/
1485	heth->State= HAL_ETH_STATE_READY;
1486
1487	/* Process Unlocked */
1488	__HAL_UNLOCK(heth);
1489
1490	/* Return function status */
1491	return HAL_OK;
1492	}
1493
1494	/**
1495	* @brief Stop Ethernet MAC and DMA reception/transmission
1496	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1497	* the configuration information for ETHERNET module
1498	* @retval HAL status
1499	*/
1500	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
1501	{
1502	/* Process Locked */
1503	__HAL_LOCK(heth);
1504
1505	/* Set the ETH peripheral state to BUSY */
1506	heth->State = HAL_ETH_STATE_BUSY;
1507
1508	/* Stop DMA transmission */
1509	ETH_DMATransmissionDisable(heth);
1510
1511	/* Stop DMA reception */
1512	ETH_DMAReceptionDisable(heth);
1513
1514	/* Disable receive state machine of the MAC for reception from the MII */
1515	ETH_MACReceptionDisable(heth);
1516
1517	/* Flush Transmit FIFO */
1518	ETH_FlushTransmitFIFO(heth);
1519
1520	/* Disable transmit state machine of the MAC for transmission on the MII */
1521	ETH_MACTransmissionDisable(heth);
1522
1523	/* Set the ETH state*/
1524	heth->State = HAL_ETH_STATE_READY;
1525
1526	/* Process Unlocked */
1527	__HAL_UNLOCK(heth);
1528
1529	/* Return function status */
1530	return HAL_OK;
1531	}
1532
1533	/**
1534	* @brief Set ETH MAC Configuration.
1535	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1536	* the configuration information for ETHERNET module
1537	* @param macconf MAC Configuration structure
1538	* @retval HAL status
1539	*/
1540	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf)
1541	{
1542	uint32_t tmpreg1 = 0U;
1543
1544	/* Process Locked */
1545	__HAL_LOCK(heth);
1546
1547	/* Set the ETH peripheral state to BUSY */
1548	heth->State= HAL_ETH_STATE_BUSY;
1549
1550	assert_param(IS_ETH_SPEED(heth->Init.Speed));
1551	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
1552
1553	if (macconf != NULL)
1554	{
1555	/* Check the parameters */
1556	assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
1557	assert_param(IS_ETH_JABBER(macconf->Jabber));
1558	assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
1559	assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
1560	assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
1561	assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
1562	assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
1563	assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
1564	assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
1565	assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
1566	assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
1567	assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
1568	assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
1569	assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
1570	assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
1571	assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
1572	assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
1573	assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
1574	assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
1575	assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
1576	assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
1577	assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
1578	assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
1579	assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
1580	assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
1581	assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
1582	assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
1583
1584	/------------------------ ETHERNET MACCR Configuration --------------------/
1585	/* Get the ETHERNET MACCR value */
1586	tmpreg1 = (heth->Instance)->MACCR;
1587	/* Clear WD, PCE, PS, TE and RE bits */
1588	tmpreg1 &= ETH_MACCR_CLEAR_MASK;
1589
1590	tmpreg1 \|= (uint32_t)(macconf->Watchdog \|
1591	macconf->Jabber \|
1592	macconf->InterFrameGap \|
1593	macconf->CarrierSense \|
1594	(heth->Init).Speed \|
1595	macconf->ReceiveOwn \|
1596	macconf->LoopbackMode \|
1597	(heth->Init).DuplexMode \|
1598	macconf->ChecksumOffload \|
1599	macconf->RetryTransmission \|
1600	macconf->AutomaticPadCRCStrip \|
1601	macconf->BackOffLimit \|
1602	macconf->DeferralCheck);
1603
1604	/* Write to ETHERNET MACCR */
1605	(heth->Instance)->MACCR = (uint32_t)tmpreg1;
1606
1607	/* Wait until the write operation will be taken into account :
1608	at least four TX_CLK/RX_CLK clock cycles */
1609	tmpreg1 = (heth->Instance)->MACCR;
1610	HAL_Delay(ETH_REG_WRITE_DELAY);
1611	(heth->Instance)->MACCR = tmpreg1;
1612
1613	/----------------------- ETHERNET MACFFR Configuration --------------------/
1614	/* Write to ETHERNET MACFFR */
1615	(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll \|
1616	macconf->SourceAddrFilter \|
1617	macconf->PassControlFrames \|
1618	macconf->BroadcastFramesReception \|
1619	macconf->DestinationAddrFilter \|
1620	macconf->PromiscuousMode \|
1621	macconf->MulticastFramesFilter \|
1622	macconf->UnicastFramesFilter);
1623
1624	/* Wait until the write operation will be taken into account :
1625	at least four TX_CLK/RX_CLK clock cycles */
1626	tmpreg1 = (heth->Instance)->MACFFR;
1627	HAL_Delay(ETH_REG_WRITE_DELAY);
1628	(heth->Instance)->MACFFR = tmpreg1;
1629
1630	/--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------/
1631	/* Write to ETHERNET MACHTHR */
1632	(heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
1633
1634	/* Write to ETHERNET MACHTLR */
1635	(heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
1636	/----------------------- ETHERNET MACFCR Configuration --------------------/
1637
1638	/* Get the ETHERNET MACFCR value */
1639	tmpreg1 = (heth->Instance)->MACFCR;
1640	/* Clear xx bits */
1641	tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
1642
1643	tmpreg1 \|= (uint32_t)((macconf->PauseTime << 16U) \|
1644	macconf->ZeroQuantaPause \|
1645	macconf->PauseLowThreshold \|
1646	macconf->UnicastPauseFrameDetect \|
1647	macconf->ReceiveFlowControl \|
1648	macconf->TransmitFlowControl);
1649
1650	/* Write to ETHERNET MACFCR */
1651	(heth->Instance)->MACFCR = (uint32_t)tmpreg1;
1652
1653	/* Wait until the write operation will be taken into account :
1654	at least four TX_CLK/RX_CLK clock cycles */
1655	tmpreg1 = (heth->Instance)->MACFCR;
1656	HAL_Delay(ETH_REG_WRITE_DELAY);
1657	(heth->Instance)->MACFCR = tmpreg1;
1658
1659	/----------------------- ETHERNET MACVLANTR Configuration -----------------/
1660	(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison \|
1661	macconf->VLANTagIdentifier);
1662
1663	/* Wait until the write operation will be taken into account :
1664	at least four TX_CLK/RX_CLK clock cycles */
1665	tmpreg1 = (heth->Instance)->MACVLANTR;
1666	HAL_Delay(ETH_REG_WRITE_DELAY);
1667	(heth->Instance)->MACVLANTR = tmpreg1;
1668	}
1669	else /* macconf == NULL : here we just configure Speed and Duplex mode */
1670	{
1671	/------------------------ ETHERNET MACCR Configuration --------------------/
1672	/* Get the ETHERNET MACCR value */
1673	tmpreg1 = (heth->Instance)->MACCR;
1674
1675	/* Clear FES and DM bits */
1676	tmpreg1 &= ~(0x00004800U);
1677
1678	tmpreg1 \|= (uint32_t)(heth->Init.Speed \| heth->Init.DuplexMode);
1679
1680	/* Write to ETHERNET MACCR */
1681	(heth->Instance)->MACCR = (uint32_t)tmpreg1;
1682
1683	/* Wait until the write operation will be taken into account:
1684	at least four TX_CLK/RX_CLK clock cycles */
1685	tmpreg1 = (heth->Instance)->MACCR;
1686	HAL_Delay(ETH_REG_WRITE_DELAY);
1687	(heth->Instance)->MACCR = tmpreg1;
1688	}
1689
1690	/* Set the ETH state to Ready */
1691	heth->State= HAL_ETH_STATE_READY;
1692
1693	/* Process Unlocked */
1694	__HAL_UNLOCK(heth);
1695
1696	/* Return function status */
1697	return HAL_OK;
1698	}
1699
1700	/**
1701	* @brief Sets ETH DMA Configuration.
1702	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1703	* the configuration information for ETHERNET module
1704	* @param dmaconf DMA Configuration structure
1705	* @retval HAL status
1706	*/
1707	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf)
1708	{
1709	uint32_t tmpreg1 = 0U;
1710
1711	/* Process Locked */
1712	__HAL_LOCK(heth);
1713
1714	/* Set the ETH peripheral state to BUSY */
1715	heth->State= HAL_ETH_STATE_BUSY;
1716
1717	/* Check parameters */
1718	assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
1719	assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
1720	assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
1721	assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
1722	assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
1723	assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
1724	assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
1725	assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
1726	assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
1727	assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
1728	assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
1729	assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
1730	assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
1731	assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
1732	assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
1733	assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
1734
1735	/----------------------- ETHERNET DMAOMR Configuration --------------------/
1736	/* Get the ETHERNET DMAOMR value */
1737	tmpreg1 = (heth->Instance)->DMAOMR;
1738	/* Clear xx bits */
1739	tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
1740
1741	tmpreg1 \|= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame \|
1742	dmaconf->ReceiveStoreForward \|
1743	dmaconf->FlushReceivedFrame \|
1744	dmaconf->TransmitStoreForward \|
1745	dmaconf->TransmitThresholdControl \|
1746	dmaconf->ForwardErrorFrames \|
1747	dmaconf->ForwardUndersizedGoodFrames \|
1748	dmaconf->ReceiveThresholdControl \|
1749	dmaconf->SecondFrameOperate);
1750
1751	/* Write to ETHERNET DMAOMR */
1752	(heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
1753
1754	/* Wait until the write operation will be taken into account:
1755	at least four TX_CLK/RX_CLK clock cycles */
1756	tmpreg1 = (heth->Instance)->DMAOMR;
1757	HAL_Delay(ETH_REG_WRITE_DELAY);
1758	(heth->Instance)->DMAOMR = tmpreg1;
1759
1760	/----------------------- ETHERNET DMABMR Configuration --------------------/
1761	(heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats \|
1762	dmaconf->FixedBurst \|
1763	dmaconf->RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
1764	dmaconf->TxDMABurstLength \|
1765	dmaconf->EnhancedDescriptorFormat \|
1766	(dmaconf->DescriptorSkipLength << 2U) \|
1767	dmaconf->DMAArbitration \|
1768	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
1769
1770	/* Wait until the write operation will be taken into account:
1771	at least four TX_CLK/RX_CLK clock cycles */
1772	tmpreg1 = (heth->Instance)->DMABMR;
1773	HAL_Delay(ETH_REG_WRITE_DELAY);
1774	(heth->Instance)->DMABMR = tmpreg1;
1775
1776	/* Set the ETH state to Ready */
1777	heth->State= HAL_ETH_STATE_READY;
1778
1779	/* Process Unlocked */
1780	__HAL_UNLOCK(heth);
1781
1782	/* Return function status */
1783	return HAL_OK;
1784	}
1785
1786	/**
1787	* @}
1788	*/
1789
1790	/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
1791	* @brief Peripheral State functions
1792	*
1793	@verbatim
1794	===============================================================================
1795	##### Peripheral State functions #####
1796	===============================================================================
1797	[..]
1798	This subsection permits to get in run-time the status of the peripheral
1799	and the data flow.
1800	(+) Get the ETH handle state:
1801	HAL_ETH_GetState();
1802
1803
1804	@endverbatim
1805	* @{
1806	*/
1807
1808	/**
1809	* @brief Return the ETH HAL state
1810	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1811	* the configuration information for ETHERNET module
1812	* @retval HAL state
1813	*/
1814	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
1815	{
1816	/* Return ETH state */
1817	return heth->State;
1818	}
1819
1820	/**
1821	* @}
1822	*/
1823
1824	/**
1825	* @}
1826	*/
1827
1828	/** @addtogroup ETH_Private_Functions
1829	* @{
1830	*/
1831
1832	/**
1833	* @brief Configures Ethernet MAC and DMA with default parameters.
1834	* @param heth pointer to a ETH_HandleTypeDef structure that contains
1835	* the configuration information for ETHERNET module
1836	* @param err Ethernet Init error
1837	* @retval HAL status
1838	*/
1839	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
1840	{
1841	ETH_MACInitTypeDef macinit;
1842	ETH_DMAInitTypeDef dmainit;
1843	uint32_t tmpreg1 = 0U;
1844
1845	if (err != ETH_SUCCESS) /* Auto-negotiation failed */
1846	{
1847	/* Set Ethernet duplex mode to Full-duplex */
1848	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
1849
1850	/* Set Ethernet speed to 100M */
1851	(heth->Init).Speed = ETH_SPEED_100M;
1852	}
1853
1854	/* Ethernet MAC default initialization **************************************/
1855	macinit.Watchdog = ETH_WATCHDOG_ENABLE;
1856	macinit.Jabber = ETH_JABBER_ENABLE;
1857	macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
1858	macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
1859	macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
1860	macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
1861	if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
1862	{
1863	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
1864	}
1865	else
1866	{
1867	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
1868	}
1869	macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
1870	macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
1871	macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
1872	macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
1873	macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
1874	macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
1875	macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
1876	macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
1877	macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
1878	macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
1879	macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
1880	macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
1881	macinit.HashTableHigh = 0x0U;
1882	macinit.HashTableLow = 0x0U;
1883	macinit.PauseTime = 0x0U;
1884	macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
1885	macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
1886	macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
1887	macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
1888	macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
1889	macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
1890	macinit.VLANTagIdentifier = 0x0U;
1891
1892	/------------------------ ETHERNET MACCR Configuration --------------------/
1893	/* Get the ETHERNET MACCR value */
1894	tmpreg1 = (heth->Instance)->MACCR;
1895	/* Clear WD, PCE, PS, TE and RE bits */
1896	tmpreg1 &= ETH_MACCR_CLEAR_MASK;
1897	/* Set the WD bit according to ETH Watchdog value */
1898	/* Set the JD: bit according to ETH Jabber value */
1899	/* Set the IFG bit according to ETH InterFrameGap value */
1900	/* Set the DCRS bit according to ETH CarrierSense value */
1901	/* Set the FES bit according to ETH Speed value */
1902	/* Set the DO bit according to ETH ReceiveOwn value */
1903	/* Set the LM bit according to ETH LoopbackMode value */
1904	/* Set the DM bit according to ETH Mode value */
1905	/* Set the IPCO bit according to ETH ChecksumOffload value */
1906	/* Set the DR bit according to ETH RetryTransmission value */
1907	/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
1908	/* Set the BL bit according to ETH BackOffLimit value */
1909	/* Set the DC bit according to ETH DeferralCheck value */
1910	tmpreg1 \|= (uint32_t)(macinit.Watchdog \|
1911	macinit.Jabber \|
1912	macinit.InterFrameGap \|
1913	macinit.CarrierSense \|
1914	(heth->Init).Speed \|
1915	macinit.ReceiveOwn \|
1916	macinit.LoopbackMode \|
1917	(heth->Init).DuplexMode \|
1918	macinit.ChecksumOffload \|
1919	macinit.RetryTransmission \|
1920	macinit.AutomaticPadCRCStrip \|
1921	macinit.BackOffLimit \|
1922	macinit.DeferralCheck);
1923
1924	/* Write to ETHERNET MACCR */
1925	(heth->Instance)->MACCR = (uint32_t)tmpreg1;
1926
1927	/* Wait until the write operation will be taken into account:
1928	at least four TX_CLK/RX_CLK clock cycles */
1929	tmpreg1 = (heth->Instance)->MACCR;
1930	HAL_Delay(ETH_REG_WRITE_DELAY);
1931	(heth->Instance)->MACCR = tmpreg1;
1932
1933	/----------------------- ETHERNET MACFFR Configuration --------------------/
1934	/* Set the RA bit according to ETH ReceiveAll value */
1935	/* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
1936	/* Set the PCF bit according to ETH PassControlFrames value */
1937	/* Set the DBF bit according to ETH BroadcastFramesReception value */
1938	/* Set the DAIF bit according to ETH DestinationAddrFilter value */
1939	/* Set the PR bit according to ETH PromiscuousMode value */
1940	/* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
1941	/* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
1942	/* Write to ETHERNET MACFFR */
1943	(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll \|
1944	macinit.SourceAddrFilter \|
1945	macinit.PassControlFrames \|
1946	macinit.BroadcastFramesReception \|
1947	macinit.DestinationAddrFilter \|
1948	macinit.PromiscuousMode \|
1949	macinit.MulticastFramesFilter \|
1950	macinit.UnicastFramesFilter);
1951
1952	/* Wait until the write operation will be taken into account:
1953	at least four TX_CLK/RX_CLK clock cycles */
1954	tmpreg1 = (heth->Instance)->MACFFR;
1955	HAL_Delay(ETH_REG_WRITE_DELAY);
1956	(heth->Instance)->MACFFR = tmpreg1;
1957
1958	/--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------/
1959	/* Write to ETHERNET MACHTHR */
1960	(heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
1961
1962	/* Write to ETHERNET MACHTLR */
1963	(heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
1964	/----------------------- ETHERNET MACFCR Configuration -------------------/
1965
1966	/* Get the ETHERNET MACFCR value */
1967	tmpreg1 = (heth->Instance)->MACFCR;
1968	/* Clear xx bits */
1969	tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
1970
1971	/* Set the PT bit according to ETH PauseTime value */
1972	/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
1973	/* Set the PLT bit according to ETH PauseLowThreshold value */
1974	/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
1975	/* Set the RFE bit according to ETH ReceiveFlowControl value */
1976	/* Set the TFE bit according to ETH TransmitFlowControl value */
1977	tmpreg1 \|= (uint32_t)((macinit.PauseTime << 16U) \|
1978	macinit.ZeroQuantaPause \|
1979	macinit.PauseLowThreshold \|
1980	macinit.UnicastPauseFrameDetect \|
1981	macinit.ReceiveFlowControl \|
1982	macinit.TransmitFlowControl);
1983
1984	/* Write to ETHERNET MACFCR */
1985	(heth->Instance)->MACFCR = (uint32_t)tmpreg1;
1986
1987	/* Wait until the write operation will be taken into account:
1988	at least four TX_CLK/RX_CLK clock cycles */
1989	tmpreg1 = (heth->Instance)->MACFCR;
1990	HAL_Delay(ETH_REG_WRITE_DELAY);
1991	(heth->Instance)->MACFCR = tmpreg1;
1992
1993	/----------------------- ETHERNET MACVLANTR Configuration ----------------/
1994	/* Set the ETV bit according to ETH VLANTagComparison value */
1995	/* Set the VL bit according to ETH VLANTagIdentifier value */
1996	(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison \|
1997	macinit.VLANTagIdentifier);
1998
1999	/* Wait until the write operation will be taken into account:
2000	at least four TX_CLK/RX_CLK clock cycles */
2001	tmpreg1 = (heth->Instance)->MACVLANTR;
2002	HAL_Delay(ETH_REG_WRITE_DELAY);
2003	(heth->Instance)->MACVLANTR = tmpreg1;
2004
2005	/* Ethernet DMA default initialization ************************************/
2006	dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
2007	dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
2008	dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
2009	dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
2010	dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
2011	dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
2012	dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
2013	dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
2014	dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
2015	dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
2016	dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
2017	dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
2018	dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
2019	dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
2020	dmainit.DescriptorSkipLength = 0x0U;
2021	dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
2022
2023	/* Get the ETHERNET DMAOMR value */
2024	tmpreg1 = (heth->Instance)->DMAOMR;
2025	/* Clear xx bits */
2026	tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
2027
2028	/* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
2029	/* Set the RSF bit according to ETH ReceiveStoreForward value */
2030	/* Set the DFF bit according to ETH FlushReceivedFrame value */
2031	/* Set the TSF bit according to ETH TransmitStoreForward value */
2032	/* Set the TTC bit according to ETH TransmitThresholdControl value */
2033	/* Set the FEF bit according to ETH ForwardErrorFrames value */
2034	/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
2035	/* Set the RTC bit according to ETH ReceiveThresholdControl value */
2036	/* Set the OSF bit according to ETH SecondFrameOperate value */
2037	tmpreg1 \|= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame \|
2038	dmainit.ReceiveStoreForward \|
2039	dmainit.FlushReceivedFrame \|
2040	dmainit.TransmitStoreForward \|
2041	dmainit.TransmitThresholdControl \|
2042	dmainit.ForwardErrorFrames \|
2043	dmainit.ForwardUndersizedGoodFrames \|
2044	dmainit.ReceiveThresholdControl \|
2045	dmainit.SecondFrameOperate);
2046
2047	/* Write to ETHERNET DMAOMR */
2048	(heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
2049
2050	/* Wait until the write operation will be taken into account:
2051	at least four TX_CLK/RX_CLK clock cycles */
2052	tmpreg1 = (heth->Instance)->DMAOMR;
2053	HAL_Delay(ETH_REG_WRITE_DELAY);
2054	(heth->Instance)->DMAOMR = tmpreg1;
2055
2056	/----------------------- ETHERNET DMABMR Configuration ------------------/
2057	/* Set the AAL bit according to ETH AddressAlignedBeats value */
2058	/* Set the FB bit according to ETH FixedBurst value */
2059	/* Set the RPBL and 4PBL bits according to ETH RxDMABurstLength value /
2060	/* Set the PBL and 4PBL bits according to ETH TxDMABurstLength value /
2061	/* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
2062	/* Set the DSL bit according to ETH DesciptorSkipLength value */
2063	/* Set the PR and DA bits according to ETH DMAArbitration value */
2064	(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats \|
2065	dmainit.FixedBurst \|
2066	dmainit.RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
2067	dmainit.TxDMABurstLength \|
2068	dmainit.EnhancedDescriptorFormat \|
2069	(dmainit.DescriptorSkipLength << 2U) \|
2070	dmainit.DMAArbitration \|
2071	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
2072
2073	/* Wait until the write operation will be taken into account:
2074	at least four TX_CLK/RX_CLK clock cycles */
2075	tmpreg1 = (heth->Instance)->DMABMR;
2076	HAL_Delay(ETH_REG_WRITE_DELAY);
2077	(heth->Instance)->DMABMR = tmpreg1;
2078
2079	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
2080	{
2081	/* Enable the Ethernet Rx Interrupt */
2082	__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS \| ETH_DMA_IT_R);
2083	}
2084
2085	/* Initialize MAC address in ethernet MAC */
2086	ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
2087	}
2088
2089	/**
2090	* @brief Configures the selected MAC address.
2091	* @param heth pointer to a ETH_HandleTypeDef structure that contains
2092	* the configuration information for ETHERNET module
2093	* @param MacAddr The MAC address to configure
2094	* This parameter can be one of the following values:
2095	* @arg ETH_MAC_Address0: MAC Address0
2096	* @arg ETH_MAC_Address1: MAC Address1
2097	* @arg ETH_MAC_Address2: MAC Address2
2098	* @arg ETH_MAC_Address3: MAC Address3
2099	* @param Addr Pointer to MAC address buffer data (6 bytes)
2100	* @retval HAL status
2101	*/
2102	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr)
2103	{
2104	uint32_t tmpreg1;
2105
2106	/* Prevent unused argument(s) compilation warning */
2107	UNUSED(heth);
2108
2109	/* Check the parameters */
2110	assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
2111
2112	/* Calculate the selected MAC address high register */
2113	tmpreg1 = ((uint32_t)Addr[5U] << 8U) \| (uint32_t)Addr[4U];
2114	/* Load the selected MAC address high register */
2115	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
2116	/* Calculate the selected MAC address low register */
2117	tmpreg1 = ((uint32_t)Addr[3U] << 24U) \| ((uint32_t)Addr[2U] << 16U) \| ((uint32_t)Addr[1U] << 8U) \| Addr[0U];
2118
2119	/* Load the selected MAC address low register */
2120	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
2121	}
2122
2123	/**
2124	* @brief Enables the MAC transmission.
2125	* @param heth pointer to a ETH_HandleTypeDef structure that contains
2126	* the configuration information for ETHERNET module
2127	* @retval None
2128	*/
2129	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
2130	{
2131	__IO uint32_t tmpreg1 = 0U;
2132
2133	/* Enable the MAC transmission */
2134	(heth->Instance)->MACCR \|= ETH_MACCR_TE;
2135
2136	/* Wait until the write operation will be taken into account:
2137	at least four TX_CLK/RX_CLK clock cycles */
2138	tmpreg1 = (heth->Instance)->MACCR;
2139	ETH_Delay(ETH_REG_WRITE_DELAY);
2140	(heth->Instance)->MACCR = tmpreg1;
2141	}
2142
2143	/**
2144	* @brief Disables the MAC transmission.
2145	* @param heth pointer to a ETH_HandleTypeDef structure that contains
2146	* the configuration information for ETHERNET module
2147	* @retval None
2148	*/
2149	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
2150	{
2151	__IO uint32_t tmpreg1 = 0U;
2152
2153	/* Disable the MAC transmission */
2154	(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
2155
2156	/* Wait until the write operation will be taken into account:
2157	at least four TX_CLK/RX_CLK clock cycles */
2158	tmpreg1 = (heth->Instance)->MACCR;
2159	ETH_Delay(ETH_REG_WRITE_DELAY);
2160	(heth->Instance)->MACCR = tmpreg1;
2161	}
2162
2163	/**
2164	* @brief Enables the MAC reception.
2165	* @param heth pointer to a ETH_HandleTypeDef structure that contains
2166	* the configuration information for ETHERNET module
2167	* @retval None
2168	*/
2169	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
2170	{
2171	__IO uint32_t tmpreg1 = 0U;
2172
2173	/* Enable the MAC reception */
2174	(heth->Instance)->MACCR \|= ETH_MACCR_RE;
2175
2176	/* Wait until the write operation will be taken into account:
2177	at least four TX_CLK/RX_CLK clock cycles */
2178	tmpreg1 = (heth->Instance)->MACCR;
2179	ETH_Delay(ETH_REG_WRITE_DELAY);
2180	(heth->Instance)->MACCR = tmpreg1;
2181	}
2182
2183	/**
2184	* @brief Disables the MAC reception.
2185	* @param heth pointer to a ETH_HandleTypeDef structure that contains
2186	* the configuration information for ETHERNET module
2187	* @retval None
2188	*/
2189	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
2190	{
2191	__IO uint32_t tmpreg1 = 0U;
2192
2193	/* Disable the MAC reception */
2194	(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
2195
2196	/* Wait until the write operation will be taken into account:
2197	at least four TX_CLK/RX_CLK clock cycles */
2198	tmpreg1 = (heth->Instance)->MACCR;
2199	ETH_Delay(ETH_REG_WRITE_DELAY);
2200	(heth->Instance)->MACCR = tmpreg1;
2201	}
2202
2203	/**
2204	* @brief Enables the DMA transmission.
2205	* @param heth pointer to a ETH_HandleTypeDef structure that contains
2206	* the configuration information for ETHERNET module
2207	* @retval None
2208	*/
2209	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
2210	{
2211	/* Enable the DMA transmission */
2212	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_ST;
2213	}
2214
2215	/**
2216	* @brief Disables the DMA transmission.
2217	* @param heth pointer to a ETH_HandleTypeDef structure that contains
2218	* the configuration information for ETHERNET module
2219	* @retval None
2220	*/
2221	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
2222	{
2223	/* Disable the DMA transmission */
2224	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
2225	}
2226
2227	/**
2228	* @brief Enables the DMA reception.
2229	* @param heth pointer to a ETH_HandleTypeDef structure that contains
2230	* the configuration information for ETHERNET module
2231	* @retval None
2232	*/
2233	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
2234	{
2235	/* Enable the DMA reception */
2236	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_SR;
2237	}
2238
2239	/**
2240	* @brief Disables the DMA reception.
2241	* @param heth pointer to a ETH_HandleTypeDef structure that contains
2242	* the configuration information for ETHERNET module
2243	* @retval None
2244	*/
2245	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
2246	{
2247	/* Disable the DMA reception */
2248	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
2249	}
2250
2251	/**
2252	* @brief Clears the ETHERNET transmit FIFO.
2253	* @param heth pointer to a ETH_HandleTypeDef structure that contains
2254	* the configuration information for ETHERNET module
2255	* @retval None
2256	*/
2257	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
2258	{
2259	__IO uint32_t tmpreg1 = 0U;
2260
2261	/* Set the Flush Transmit FIFO bit */
2262	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_FTF;
2263
2264	/* Wait until the write operation will be taken into account:
2265	at least four TX_CLK/RX_CLK clock cycles */
2266	tmpreg1 = (heth->Instance)->DMAOMR;
2267	ETH_Delay(ETH_REG_WRITE_DELAY);
2268	(heth->Instance)->DMAOMR = tmpreg1;
2269	}
2270
2271	/**
2272	* @brief This function provides delay (in milliseconds) based on CPU cycles method.
2273	* @param mdelay specifies the delay time length, in milliseconds.
2274	* @retval None
2275	*/
2276	static void ETH_Delay(uint32_t mdelay)
2277	{
2278	__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
2279	do
2280	{
2281	__NOP();
2282	}
2283	while (Delay --);
2284	}
2285
2286	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
2287	static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
2288	{
2289	/* Init the ETH Callback settings */
2290	heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */
2291	heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */
2292	heth->DMAErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak DMAErrorCallback */
2293	}
2294	#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
2295
2296	/**
2297	* @}
2298	*/
2299
2300	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\|\
2301	STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
2302	#endif /* HAL_ETH_MODULE_ENABLED */
2303	/**
2304	* @}
2305	*/
2306
2307	/**
2308	* @}
2309	*/
2310
2311	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c

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