source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c

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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
15 * All rights reserved.</center></h2>
16 *
17 * This software component is licensed by ST under BSD 3-Clause license,
18 * the "License"; You may not use this file except in compliance with the
19 * License. You may obtain a copy of the License at:
20 * opensource.org/licenses/BSD-3-Clause
21 *
22 ******************************************************************************
23 */
24
25/* Includes ------------------------------------------------------------------*/
26#include "stm32f4xx_hal.h"
27
28/** @addtogroup STM32F4xx_HAL_Driver
29 * @{
30 */
31
32/** @defgroup PWR PWR
33 * @brief PWR HAL module driver
34 * @{
35 */
36
37#ifdef HAL_PWR_MODULE_ENABLED
38
39/* Private typedef -----------------------------------------------------------*/
40/* Private define ------------------------------------------------------------*/
41/** @addtogroup PWR_Private_Constants
42 * @{
43 */
44
45/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
46 * @{
47 */
48#define PVD_MODE_IT 0x00010000U
49#define PVD_MODE_EVT 0x00020000U
50#define PVD_RISING_EDGE 0x00000001U
51#define PVD_FALLING_EDGE 0x00000002U
52/**
53 * @}
54 */
55
56/**
57 * @}
58 */
59/* Private macro -------------------------------------------------------------*/
60/* Private variables ---------------------------------------------------------*/
61/* Private function prototypes -----------------------------------------------*/
62/* Private functions ---------------------------------------------------------*/
63
64/** @defgroup PWR_Exported_Functions PWR Exported Functions
65 * @{
66 */
67
68/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
69 * @brief Initialization and de-initialization functions
70 *
71@verbatim
72 ===============================================================================
73 ##### Initialization and de-initialization functions #####
74 ===============================================================================
75 [..]
76 After reset, the backup domain (RTC registers, RTC backup data
77 registers and backup SRAM) is protected against possible unwanted
78 write accesses.
79 To enable access to the RTC Domain and RTC registers, proceed as follows:
80 (+) Enable the Power Controller (PWR) APB1 interface clock using the
81 __HAL_RCC_PWR_CLK_ENABLE() macro.
82 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
83
84@endverbatim
85 * @{
86 */
87
88/**
89 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
90 * @retval None
91 */
92void HAL_PWR_DeInit(void)
93{
94 __HAL_RCC_PWR_FORCE_RESET();
95 __HAL_RCC_PWR_RELEASE_RESET();
96}
97
98/**
99 * @brief Enables access to the backup domain (RTC registers, RTC
100 * backup data registers and backup SRAM).
101 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
102 * Backup Domain Access should be kept enabled.
103 * @note The following sequence is required to bypass the delay between
104 * DBP bit programming and the effective enabling of the backup domain.
105 * Please check the Errata Sheet for more details under "Possible delay
106 * in backup domain protection disabling/enabling after programming the
107 * DBP bit" section.
108 * @retval None
109 */
110void HAL_PWR_EnableBkUpAccess(void)
111{
112 __IO uint32_t dummyread;
113 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
114 dummyread = PWR->CR;
115 UNUSED(dummyread);
116}
117
118/**
119 * @brief Disables access to the backup domain (RTC registers, RTC
120 * backup data registers and backup SRAM).
121 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
122 * Backup Domain Access should be kept enabled.
123 * @note The following sequence is required to bypass the delay between
124 * DBP bit programming and the effective disabling of the backup domain.
125 * Please check the Errata Sheet for more details under "Possible delay
126 * in backup domain protection disabling/enabling after programming the
127 * DBP bit" section.
128 * @retval None
129 */
130void HAL_PWR_DisableBkUpAccess(void)
131{
132 __IO uint32_t dummyread;
133 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
134 dummyread = PWR->CR;
135 UNUSED(dummyread);
136}
137
138/**
139 * @}
140 */
141
142/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
143 * @brief Low Power modes configuration functions
144 *
145@verbatim
146
147 ===============================================================================
148 ##### Peripheral Control functions #####
149 ===============================================================================
150
151 *** PVD configuration ***
152 =========================
153 [..]
154 (+) The PVD is used to monitor the VDD power supply by comparing it to a
155 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
156 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
157 than the PVD threshold. This event is internally connected to the EXTI
158 line16 and can generate an interrupt if enabled. This is done through
159 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
160 (+) The PVD is stopped in Standby mode.
161
162 *** Wake-up pin configuration ***
163 ================================
164 [..]
165 (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
166 forced in input pull-down configuration and is active on rising edges.
167 (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
168 (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
169 (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
170
171 *** Low Power modes configuration ***
172 =====================================
173 [..]
174 The devices feature 3 low-power modes:
175 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
176 (+) Stop mode: all clocks are stopped, regulator running, regulator
177 in low power mode
178 (+) Standby mode: 1.2V domain powered off.
179
180 *** Sleep mode ***
181 ==================
182 [..]
183 (+) Entry:
184 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
185 functions with
186 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
187 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
188
189 -@@- The Regulator parameter is not used for the STM32F4 family
190 and is kept as parameter just to maintain compatibility with the
191 lower power families (STM32L).
192 (+) Exit:
193 Any peripheral interrupt acknowledged by the nested vectored interrupt
194 controller (NVIC) can wake up the device from Sleep mode.
195
196 *** Stop mode ***
197 =================
198 [..]
199 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
200 and the HSE RC oscillators are disabled. Internal SRAM and register contents
201 are preserved.
202 The voltage regulator can be configured either in normal or low-power mode.
203 To minimize the consumption In Stop mode, FLASH can be powered off before
204 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
205 It can be switched on again by software after exiting the Stop mode using
206 the HAL_PWREx_DisableFlashPowerDown() function.
207
208 (+) Entry:
209 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
210 function with:
211 (++) Main regulator ON.
212 (++) Low Power regulator ON.
213 (+) Exit:
214 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
215
216 *** Standby mode ***
217 ====================
218 [..]
219 (+)
220 The Standby mode allows to achieve the lowest power consumption. It is based
221 on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
222 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
223 the HSE oscillator are also switched off. SRAM and register contents are lost
224 except for the RTC registers, RTC backup registers, backup SRAM and Standby
225 circuitry.
226
227 The voltage regulator is OFF.
228
229 (++) Entry:
230 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
231 (++) Exit:
232 (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
233 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
234
235 *** Auto-wake-up (AWU) from low-power mode ***
236 =============================================
237 [..]
238
239 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
240 Wake-up event, a tamper event or a time-stamp event, without depending on
241 an external interrupt (Auto-wake-up mode).
242
243 (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
244
245 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
246 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
247
248 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
249 is necessary to configure the RTC to detect the tamper or time stamp event using the
250 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
251
252 (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
253 configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
254
255@endverbatim
256 * @{
257 */
258
259/**
260 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
261 * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
262 * information for the PVD.
263 * @note Refer to the electrical characteristics of your device datasheet for
264 * more details about the voltage threshold corresponding to each
265 * detection level.
266 * @retval None
267 */
268void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
269{
270 /* Check the parameters */
271 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
272 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
273
274 /* Set PLS[7:5] bits according to PVDLevel value */
275 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
276
277 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
278 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
279 __HAL_PWR_PVD_EXTI_DISABLE_IT();
280 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
281 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
282
283 /* Configure interrupt mode */
284 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
285 {
286 __HAL_PWR_PVD_EXTI_ENABLE_IT();
287 }
288
289 /* Configure event mode */
290 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
291 {
292 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
293 }
294
295 /* Configure the edge */
296 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
297 {
298 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
299 }
300
301 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
302 {
303 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
304 }
305}
306
307/**
308 * @brief Enables the Power Voltage Detector(PVD).
309 * @retval None
310 */
311void HAL_PWR_EnablePVD(void)
312{
313 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
314}
315
316/**
317 * @brief Disables the Power Voltage Detector(PVD).
318 * @retval None
319 */
320void HAL_PWR_DisablePVD(void)
321{
322 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
323}
324
325/**
326 * @brief Enables the Wake-up PINx functionality.
327 * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
328 * This parameter can be one of the following values:
329 * @arg PWR_WAKEUP_PIN1
330 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
331 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
332 * @retval None
333 */
334void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
335{
336 /* Check the parameter */
337 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
338
339 /* Enable the wake up pin */
340 SET_BIT(PWR->CSR, WakeUpPinx);
341}
342
343/**
344 * @brief Disables the Wake-up PINx functionality.
345 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
346 * This parameter can be one of the following values:
347 * @arg PWR_WAKEUP_PIN1
348 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
349 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
350 * @retval None
351 */
352void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
353{
354 /* Check the parameter */
355 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
356
357 /* Disable the wake up pin */
358 CLEAR_BIT(PWR->CSR, WakeUpPinx);
359}
360
361/**
362 * @brief Enters Sleep mode.
363 *
364 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
365 *
366 * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
367 * systick interrupt when used as time base for Timeout
368 *
369 * @param Regulator Specifies the regulator state in SLEEP mode.
370 * This parameter can be one of the following values:
371 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
372 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
373 * @note This parameter is not used for the STM32F4 family and is kept as parameter
374 * just to maintain compatibility with the lower power families.
375 * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
376 * This parameter can be one of the following values:
377 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
378 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
379 * @retval None
380 */
381void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
382{
383 /* Check the parameters */
384 assert_param(IS_PWR_REGULATOR(Regulator));
385 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
386
387 /* Clear SLEEPDEEP bit of Cortex System Control Register */
388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
389
390 /* Select SLEEP mode entry -------------------------------------------------*/
391 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
392 {
393 /* Request Wait For Interrupt */
394 __WFI();
395 }
396 else
397 {
398 /* Request Wait For Event */
399 __SEV();
400 __WFE();
401 __WFE();
402 }
403}
404
405/**
406 * @brief Enters Stop mode.
407 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
408 * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
409 * the HSI RC oscillator is selected as system clock.
410 * @note When the voltage regulator operates in low power mode, an additional
411 * startup delay is incurred when waking up from Stop mode.
412 * By keeping the internal regulator ON during Stop mode, the consumption
413 * is higher although the startup time is reduced.
414 * @param Regulator Specifies the regulator state in Stop mode.
415 * This parameter can be one of the following values:
416 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
417 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
418 * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
419 * This parameter can be one of the following values:
420 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
421 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
422 * @retval None
423 */
424void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
425{
426 /* Check the parameters */
427 assert_param(IS_PWR_REGULATOR(Regulator));
428 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
429
430 /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
431 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
432
433 /* Set SLEEPDEEP bit of Cortex System Control Register */
434 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
435
436 /* Select Stop mode entry --------------------------------------------------*/
437 if(STOPEntry == PWR_STOPENTRY_WFI)
438 {
439 /* Request Wait For Interrupt */
440 __WFI();
441 }
442 else
443 {
444 /* Request Wait For Event */
445 __SEV();
446 __WFE();
447 __WFE();
448 }
449 /* Reset SLEEPDEEP bit of Cortex System Control Register */
450 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
451}
452
453/**
454 * @brief Enters Standby mode.
455 * @note In Standby mode, all I/O pins are high impedance except for:
456 * - Reset pad (still available)
457 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
458 * Alarm out, or RTC clock calibration out.
459 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
460 * - WKUP pin 1 (PA0) if enabled.
461 * @retval None
462 */
463void HAL_PWR_EnterSTANDBYMode(void)
464{
465 /* Select Standby mode */
466 SET_BIT(PWR->CR, PWR_CR_PDDS);
467
468 /* Set SLEEPDEEP bit of Cortex System Control Register */
469 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
470
471 /* This option is used to ensure that store operations are completed */
472#if defined ( __CC_ARM)
473 __force_stores();
474#endif
475 /* Request Wait For Interrupt */
476 __WFI();
477}
478
479/**
480 * @brief This function handles the PWR PVD interrupt request.
481 * @note This API should be called under the PVD_IRQHandler().
482 * @retval None
483 */
484void HAL_PWR_PVD_IRQHandler(void)
485{
486 /* Check PWR Exti flag */
487 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
488 {
489 /* PWR PVD interrupt user callback */
490 HAL_PWR_PVDCallback();
491
492 /* Clear PWR Exti pending bit */
493 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
494 }
495}
496
497/**
498 * @brief PWR PVD interrupt callback
499 * @retval None
500 */
501__weak void HAL_PWR_PVDCallback(void)
502{
503 /* NOTE : This function Should not be modified, when the callback is needed,
504 the HAL_PWR_PVDCallback could be implemented in the user file
505 */
506}
507
508/**
509 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
510 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
511 * re-enters SLEEP mode when an interruption handling is over.
512 * Setting this bit is useful when the processor is expected to run only on
513 * interruptions handling.
514 * @retval None
515 */
516void HAL_PWR_EnableSleepOnExit(void)
517{
518 /* Set SLEEPONEXIT bit of Cortex System Control Register */
519 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
520}
521
522/**
523 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
524 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
525 * re-enters SLEEP mode when an interruption handling is over.
526 * @retval None
527 */
528void HAL_PWR_DisableSleepOnExit(void)
529{
530 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
531 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
532}
533
534/**
535 * @brief Enables CORTEX M4 SEVONPEND bit.
536 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
537 * WFE to wake up when an interrupt moves from inactive to pended.
538 * @retval None
539 */
540void HAL_PWR_EnableSEVOnPend(void)
541{
542 /* Set SEVONPEND bit of Cortex System Control Register */
543 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
544}
545
546/**
547 * @brief Disables CORTEX M4 SEVONPEND bit.
548 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
549 * WFE to wake up when an interrupt moves from inactive to pended.
550 * @retval None
551 */
552void HAL_PWR_DisableSEVOnPend(void)
553{
554 /* Clear SEVONPEND bit of Cortex System Control Register */
555 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
556}
557
558/**
559 * @}
560 */
561
562/**
563 * @}
564 */
565
566#endif /* HAL_PWR_MODULE_ENABLED */
567/**
568 * @}
569 */
570
571/**
572 * @}
573 */
574
575/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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