source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c

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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 @verbatim
33 ==============================================================================
34 ##### TIMER Generic features #####
35 ==============================================================================
36 [..] The Timer features include:
37 (#) 16-bit up, down, up/down auto-reload counter.
38 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
39 counter clock frequency either by any factor between 1 and 65536.
40 (#) Up to 4 independent channels for:
41 (++) Input Capture
42 (++) Output Compare
43 (++) PWM generation (Edge and Center-aligned Mode)
44 (++) One-pulse mode output
45 (#) Synchronization circuit to control the timer with external signals and to interconnect
46 several timers together.
47 (#) Supports incremental encoder for positioning purposes
48
49 ##### How to use this driver #####
50 ==============================================================================
51 [..]
52 (#) Initialize the TIM low level resources by implementing the following functions
53 depending on the selected feature:
54 (++) Time Base : HAL_TIM_Base_MspInit()
55 (++) Input Capture : HAL_TIM_IC_MspInit()
56 (++) Output Compare : HAL_TIM_OC_MspInit()
57 (++) PWM generation : HAL_TIM_PWM_MspInit()
58 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
59 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60
61 (#) Initialize the TIM low level resources :
62 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
63 (##) TIM pins configuration
64 (+++) Enable the clock for the TIM GPIOs using the following function:
65 __HAL_RCC_GPIOx_CLK_ENABLE();
66 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67
68 (#) The external Clock can be configured, if needed (the default clock is the
69 internal clock from the APBx), using the following function:
70 HAL_TIM_ConfigClockSource, the clock configuration should be done before
71 any start function.
72
73 (#) Configure the TIM in the desired functioning mode using one of the
74 Initialization function of this driver:
75 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
76 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
77 Output Compare signal.
78 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 PWM signal.
80 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 external signal.
82 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 in One Pulse Mode.
84 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85
86 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
87 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
88 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
89 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
90 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
91 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
92 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93
94 (#) The DMA Burst is managed with the two following functions:
95 HAL_TIM_DMABurst_WriteStart()
96 HAL_TIM_DMABurst_ReadStart()
97
98 *** Callback registration ***
99 =============================================
100
101 [..]
102 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
103 allows the user to configure dynamically the driver callbacks.
104
105 [..]
106 Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
107 @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
108 the Callback ID and a pointer to the user callback function.
109
110 [..]
111 Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
112 weak function.
113 @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
114 and the Callback ID.
115
116 [..]
117 These functions allow to register/unregister following callbacks:
118 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
119 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
120 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
121 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
122 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
123 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
124 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
125 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
126 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
127 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
128 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
129 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
130 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
131 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
132 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
133 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
134 (+) TriggerCallback : TIM Trigger Callback.
135 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
136 (+) IC_CaptureCallback : TIM Input Capture Callback.
137 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
138 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
139 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
140 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
141 (+) ErrorCallback : TIM Error Callback.
142 (+) CommutationCallback : TIM Commutation Callback.
143 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
144 (+) BreakCallback : TIM Break Callback.
145
146 [..]
147By default, after the Init and when the state is HAL_TIM_STATE_RESET
148all interrupt callbacks are set to the corresponding weak functions:
149 examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
150
151 [..]
152 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
153 functionalities in the Init / DeInit only when these callbacks are null
154 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
155 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
156
157 [..]
158 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
159 Exception done MspInit / MspDeInit that can be registered / unregistered
160 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
161 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
162 In that case first register the MspInit/MspDeInit user callbacks
163 using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
164
165 [..]
166 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
167 not defined, the callback registration feature is not available and all callbacks
168 are set to the corresponding weak functions.
169
170 @endverbatim
171 ******************************************************************************
172 * @attention
173 *
174 * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
175 * All rights reserved.</center></h2>
176 *
177 * This software component is licensed by ST under BSD 3-Clause license,
178 * the "License"; You may not use this file except in compliance with the
179 * License. You may obtain a copy of the License at:
180 * opensource.org/licenses/BSD-3-Clause
181 *
182 ******************************************************************************
183 */
184
185/* Includes ------------------------------------------------------------------*/
186#include "stm32f4xx_hal.h"
187
188/** @addtogroup STM32F4xx_HAL_Driver
189 * @{
190 */
191
192/** @defgroup TIM TIM
193 * @brief TIM HAL module driver
194 * @{
195 */
196
197#ifdef HAL_TIM_MODULE_ENABLED
198
199/* Private typedef -----------------------------------------------------------*/
200/* Private define ------------------------------------------------------------*/
201/* Private macros ------------------------------------------------------------*/
202/* Private variables ---------------------------------------------------------*/
203/* Private function prototypes -----------------------------------------------*/
204/** @addtogroup TIM_Private_Functions
205 * @{
206 */
207static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
208static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
209static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
210static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
211static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
212 uint32_t TIM_ICFilter);
213static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
214static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
215 uint32_t TIM_ICFilter);
216static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
217 uint32_t TIM_ICFilter);
218static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
219static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
220static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
221static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
222static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
223static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
224static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
225 TIM_SlaveConfigTypeDef *sSlaveConfig);
226/**
227 * @}
228 */
229/* Exported functions --------------------------------------------------------*/
230
231/** @defgroup TIM_Exported_Functions TIM Exported Functions
232 * @{
233 */
234
235/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
236 * @brief Time Base functions
237 *
238@verbatim
239 ==============================================================================
240 ##### Time Base functions #####
241 ==============================================================================
242 [..]
243 This section provides functions allowing to:
244 (+) Initialize and configure the TIM base.
245 (+) De-initialize the TIM base.
246 (+) Start the Time Base.
247 (+) Stop the Time Base.
248 (+) Start the Time Base and enable interrupt.
249 (+) Stop the Time Base and disable interrupt.
250 (+) Start the Time Base and enable DMA transfer.
251 (+) Stop the Time Base and disable DMA transfer.
252
253@endverbatim
254 * @{
255 */
256/**
257 * @brief Initializes the TIM Time base Unit according to the specified
258 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
259 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
260 * requires a timer reset to avoid unexpected direction
261 * due to DIR bit readonly in center aligned mode.
262 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
263 * @param htim TIM Base handle
264 * @retval HAL status
265 */
266HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
267{
268 /* Check the TIM handle allocation */
269 if (htim == NULL)
270 {
271 return HAL_ERROR;
272 }
273
274 /* Check the parameters */
275 assert_param(IS_TIM_INSTANCE(htim->Instance));
276 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
277 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
278 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
279
280 if (htim->State == HAL_TIM_STATE_RESET)
281 {
282 /* Allocate lock resource and initialize it */
283 htim->Lock = HAL_UNLOCKED;
284
285#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
286 /* Reset interrupt callbacks to legacy weak callbacks */
287 TIM_ResetCallback(htim);
288
289 if (htim->Base_MspInitCallback == NULL)
290 {
291 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
292 }
293 /* Init the low level hardware : GPIO, CLOCK, NVIC */
294 htim->Base_MspInitCallback(htim);
295#else
296 /* Init the low level hardware : GPIO, CLOCK, NVIC */
297 HAL_TIM_Base_MspInit(htim);
298#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
299 }
300
301 /* Set the TIM state */
302 htim->State = HAL_TIM_STATE_BUSY;
303
304 /* Set the Time Base configuration */
305 TIM_Base_SetConfig(htim->Instance, &htim->Init);
306
307 /* Initialize the DMA burst operation state */
308 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
309
310 /* Initialize the TIM channels state */
311 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
312 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
313
314 /* Initialize the TIM state*/
315 htim->State = HAL_TIM_STATE_READY;
316
317 return HAL_OK;
318}
319
320/**
321 * @brief DeInitializes the TIM Base peripheral
322 * @param htim TIM Base handle
323 * @retval HAL status
324 */
325HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
326{
327 /* Check the parameters */
328 assert_param(IS_TIM_INSTANCE(htim->Instance));
329
330 htim->State = HAL_TIM_STATE_BUSY;
331
332 /* Disable the TIM Peripheral Clock */
333 __HAL_TIM_DISABLE(htim);
334
335#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
336 if (htim->Base_MspDeInitCallback == NULL)
337 {
338 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
339 }
340 /* DeInit the low level hardware */
341 htim->Base_MspDeInitCallback(htim);
342#else
343 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
344 HAL_TIM_Base_MspDeInit(htim);
345#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
346
347 /* Change the DMA burst operation state */
348 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
349
350 /* Change the TIM channels state */
351 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
352 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
353
354 /* Change TIM state */
355 htim->State = HAL_TIM_STATE_RESET;
356
357 /* Release Lock */
358 __HAL_UNLOCK(htim);
359
360 return HAL_OK;
361}
362
363/**
364 * @brief Initializes the TIM Base MSP.
365 * @param htim TIM Base handle
366 * @retval None
367 */
368__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
369{
370 /* Prevent unused argument(s) compilation warning */
371 UNUSED(htim);
372
373 /* NOTE : This function should not be modified, when the callback is needed,
374 the HAL_TIM_Base_MspInit could be implemented in the user file
375 */
376}
377
378/**
379 * @brief DeInitializes TIM Base MSP.
380 * @param htim TIM Base handle
381 * @retval None
382 */
383__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
384{
385 /* Prevent unused argument(s) compilation warning */
386 UNUSED(htim);
387
388 /* NOTE : This function should not be modified, when the callback is needed,
389 the HAL_TIM_Base_MspDeInit could be implemented in the user file
390 */
391}
392
393
394/**
395 * @brief Starts the TIM Base generation.
396 * @param htim TIM Base handle
397 * @retval HAL status
398 */
399HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
400{
401 uint32_t tmpsmcr;
402
403 /* Check the parameters */
404 assert_param(IS_TIM_INSTANCE(htim->Instance));
405
406 /* Check the TIM state */
407 if (htim->State != HAL_TIM_STATE_READY)
408 {
409 return HAL_ERROR;
410 }
411
412 /* Set the TIM state */
413 htim->State = HAL_TIM_STATE_BUSY;
414
415 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
416 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
417 {
418 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
419 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
420 {
421 __HAL_TIM_ENABLE(htim);
422 }
423 }
424 else
425 {
426 __HAL_TIM_ENABLE(htim);
427 }
428
429 /* Return function status */
430 return HAL_OK;
431}
432
433/**
434 * @brief Stops the TIM Base generation.
435 * @param htim TIM Base handle
436 * @retval HAL status
437 */
438HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
439{
440 /* Check the parameters */
441 assert_param(IS_TIM_INSTANCE(htim->Instance));
442
443 /* Disable the Peripheral */
444 __HAL_TIM_DISABLE(htim);
445
446 /* Set the TIM state */
447 htim->State = HAL_TIM_STATE_READY;
448
449 /* Return function status */
450 return HAL_OK;
451}
452
453/**
454 * @brief Starts the TIM Base generation in interrupt mode.
455 * @param htim TIM Base handle
456 * @retval HAL status
457 */
458HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
459{
460 uint32_t tmpsmcr;
461
462 /* Check the parameters */
463 assert_param(IS_TIM_INSTANCE(htim->Instance));
464
465 /* Check the TIM state */
466 if (htim->State != HAL_TIM_STATE_READY)
467 {
468 return HAL_ERROR;
469 }
470
471 /* Set the TIM state */
472 htim->State = HAL_TIM_STATE_BUSY;
473
474 /* Enable the TIM Update interrupt */
475 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
476
477 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
478 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
479 {
480 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
481 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
482 {
483 __HAL_TIM_ENABLE(htim);
484 }
485 }
486 else
487 {
488 __HAL_TIM_ENABLE(htim);
489 }
490
491 /* Return function status */
492 return HAL_OK;
493}
494
495/**
496 * @brief Stops the TIM Base generation in interrupt mode.
497 * @param htim TIM Base handle
498 * @retval HAL status
499 */
500HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
501{
502 /* Check the parameters */
503 assert_param(IS_TIM_INSTANCE(htim->Instance));
504
505 /* Disable the TIM Update interrupt */
506 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
507
508 /* Disable the Peripheral */
509 __HAL_TIM_DISABLE(htim);
510
511 /* Set the TIM state */
512 htim->State = HAL_TIM_STATE_READY;
513
514 /* Return function status */
515 return HAL_OK;
516}
517
518/**
519 * @brief Starts the TIM Base generation in DMA mode.
520 * @param htim TIM Base handle
521 * @param pData The source Buffer address.
522 * @param Length The length of data to be transferred from memory to peripheral.
523 * @retval HAL status
524 */
525HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
526{
527 uint32_t tmpsmcr;
528
529 /* Check the parameters */
530 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
531
532 /* Set the TIM state */
533 if (htim->State == HAL_TIM_STATE_BUSY)
534 {
535 return HAL_BUSY;
536 }
537 else if (htim->State == HAL_TIM_STATE_READY)
538 {
539 if ((pData == NULL) && (Length > 0U))
540 {
541 return HAL_ERROR;
542 }
543 else
544 {
545 htim->State = HAL_TIM_STATE_BUSY;
546 }
547 }
548 else
549 {
550 return HAL_ERROR;
551 }
552
553 /* Set the DMA Period elapsed callbacks */
554 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
555 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
556
557 /* Set the DMA error callback */
558 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
559
560 /* Enable the DMA stream */
561 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
562 {
563 /* Return error status */
564 return HAL_ERROR;
565 }
566
567 /* Enable the TIM Update DMA request */
568 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
569
570 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
571 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
572 {
573 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
574 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
575 {
576 __HAL_TIM_ENABLE(htim);
577 }
578 }
579 else
580 {
581 __HAL_TIM_ENABLE(htim);
582 }
583
584 /* Return function status */
585 return HAL_OK;
586}
587
588/**
589 * @brief Stops the TIM Base generation in DMA mode.
590 * @param htim TIM Base handle
591 * @retval HAL status
592 */
593HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
594{
595 /* Check the parameters */
596 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
597
598 /* Disable the TIM Update DMA request */
599 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
600
601 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
602
603 /* Disable the Peripheral */
604 __HAL_TIM_DISABLE(htim);
605
606 /* Set the TIM state */
607 htim->State = HAL_TIM_STATE_READY;
608
609 /* Return function status */
610 return HAL_OK;
611}
612
613/**
614 * @}
615 */
616
617/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
618 * @brief TIM Output Compare functions
619 *
620@verbatim
621 ==============================================================================
622 ##### TIM Output Compare functions #####
623 ==============================================================================
624 [..]
625 This section provides functions allowing to:
626 (+) Initialize and configure the TIM Output Compare.
627 (+) De-initialize the TIM Output Compare.
628 (+) Start the TIM Output Compare.
629 (+) Stop the TIM Output Compare.
630 (+) Start the TIM Output Compare and enable interrupt.
631 (+) Stop the TIM Output Compare and disable interrupt.
632 (+) Start the TIM Output Compare and enable DMA transfer.
633 (+) Stop the TIM Output Compare and disable DMA transfer.
634
635@endverbatim
636 * @{
637 */
638/**
639 * @brief Initializes the TIM Output Compare according to the specified
640 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
641 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
642 * requires a timer reset to avoid unexpected direction
643 * due to DIR bit readonly in center aligned mode.
644 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
645 * @param htim TIM Output Compare handle
646 * @retval HAL status
647 */
648HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
649{
650 /* Check the TIM handle allocation */
651 if (htim == NULL)
652 {
653 return HAL_ERROR;
654 }
655
656 /* Check the parameters */
657 assert_param(IS_TIM_INSTANCE(htim->Instance));
658 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
659 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
660 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
661
662 if (htim->State == HAL_TIM_STATE_RESET)
663 {
664 /* Allocate lock resource and initialize it */
665 htim->Lock = HAL_UNLOCKED;
666
667#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
668 /* Reset interrupt callbacks to legacy weak callbacks */
669 TIM_ResetCallback(htim);
670
671 if (htim->OC_MspInitCallback == NULL)
672 {
673 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
674 }
675 /* Init the low level hardware : GPIO, CLOCK, NVIC */
676 htim->OC_MspInitCallback(htim);
677#else
678 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
679 HAL_TIM_OC_MspInit(htim);
680#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
681 }
682
683 /* Set the TIM state */
684 htim->State = HAL_TIM_STATE_BUSY;
685
686 /* Init the base time for the Output Compare */
687 TIM_Base_SetConfig(htim->Instance, &htim->Init);
688
689 /* Initialize the DMA burst operation state */
690 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
691
692 /* Initialize the TIM channels state */
693 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
694 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
695
696 /* Initialize the TIM state*/
697 htim->State = HAL_TIM_STATE_READY;
698
699 return HAL_OK;
700}
701
702/**
703 * @brief DeInitializes the TIM peripheral
704 * @param htim TIM Output Compare handle
705 * @retval HAL status
706 */
707HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
708{
709 /* Check the parameters */
710 assert_param(IS_TIM_INSTANCE(htim->Instance));
711
712 htim->State = HAL_TIM_STATE_BUSY;
713
714 /* Disable the TIM Peripheral Clock */
715 __HAL_TIM_DISABLE(htim);
716
717#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
718 if (htim->OC_MspDeInitCallback == NULL)
719 {
720 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
721 }
722 /* DeInit the low level hardware */
723 htim->OC_MspDeInitCallback(htim);
724#else
725 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
726 HAL_TIM_OC_MspDeInit(htim);
727#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
728
729 /* Change the DMA burst operation state */
730 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
731
732 /* Change the TIM channels state */
733 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
734 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
735
736 /* Change TIM state */
737 htim->State = HAL_TIM_STATE_RESET;
738
739 /* Release Lock */
740 __HAL_UNLOCK(htim);
741
742 return HAL_OK;
743}
744
745/**
746 * @brief Initializes the TIM Output Compare MSP.
747 * @param htim TIM Output Compare handle
748 * @retval None
749 */
750__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
751{
752 /* Prevent unused argument(s) compilation warning */
753 UNUSED(htim);
754
755 /* NOTE : This function should not be modified, when the callback is needed,
756 the HAL_TIM_OC_MspInit could be implemented in the user file
757 */
758}
759
760/**
761 * @brief DeInitializes TIM Output Compare MSP.
762 * @param htim TIM Output Compare handle
763 * @retval None
764 */
765__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
766{
767 /* Prevent unused argument(s) compilation warning */
768 UNUSED(htim);
769
770 /* NOTE : This function should not be modified, when the callback is needed,
771 the HAL_TIM_OC_MspDeInit could be implemented in the user file
772 */
773}
774
775/**
776 * @brief Starts the TIM Output Compare signal generation.
777 * @param htim TIM Output Compare handle
778 * @param Channel TIM Channel to be enabled
779 * This parameter can be one of the following values:
780 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
781 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
782 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
783 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
784 * @retval HAL status
785 */
786HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
787{
788 uint32_t tmpsmcr;
789
790 /* Check the parameters */
791 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
792
793 /* Check the TIM channel state */
794 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
795 {
796 return HAL_ERROR;
797 }
798
799 /* Set the TIM channel state */
800 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
801
802 /* Enable the Output compare channel */
803 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
804
805 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
806 {
807 /* Enable the main output */
808 __HAL_TIM_MOE_ENABLE(htim);
809 }
810
811 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
812 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
813 {
814 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
815 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
816 {
817 __HAL_TIM_ENABLE(htim);
818 }
819 }
820 else
821 {
822 __HAL_TIM_ENABLE(htim);
823 }
824
825 /* Return function status */
826 return HAL_OK;
827}
828
829/**
830 * @brief Stops the TIM Output Compare signal generation.
831 * @param htim TIM Output Compare handle
832 * @param Channel TIM Channel to be disabled
833 * This parameter can be one of the following values:
834 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
835 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
836 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
837 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
838 * @retval HAL status
839 */
840HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
841{
842 /* Check the parameters */
843 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
844
845 /* Disable the Output compare channel */
846 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
847
848 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
849 {
850 /* Disable the Main Output */
851 __HAL_TIM_MOE_DISABLE(htim);
852 }
853
854 /* Disable the Peripheral */
855 __HAL_TIM_DISABLE(htim);
856
857 /* Set the TIM channel state */
858 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
859
860 /* Return function status */
861 return HAL_OK;
862}
863
864/**
865 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
866 * @param htim TIM Output Compare handle
867 * @param Channel TIM Channel to be enabled
868 * This parameter can be one of the following values:
869 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
870 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
871 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
872 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
873 * @retval HAL status
874 */
875HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
876{
877 uint32_t tmpsmcr;
878
879 /* Check the parameters */
880 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
881
882 /* Check the TIM channel state */
883 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
884 {
885 return HAL_ERROR;
886 }
887
888 /* Set the TIM channel state */
889 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
890
891 switch (Channel)
892 {
893 case TIM_CHANNEL_1:
894 {
895 /* Enable the TIM Capture/Compare 1 interrupt */
896 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
897 break;
898 }
899
900 case TIM_CHANNEL_2:
901 {
902 /* Enable the TIM Capture/Compare 2 interrupt */
903 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
904 break;
905 }
906
907 case TIM_CHANNEL_3:
908 {
909 /* Enable the TIM Capture/Compare 3 interrupt */
910 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
911 break;
912 }
913
914 case TIM_CHANNEL_4:
915 {
916 /* Enable the TIM Capture/Compare 4 interrupt */
917 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
918 break;
919 }
920
921 default:
922 break;
923 }
924
925 /* Enable the Output compare channel */
926 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
927
928 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
929 {
930 /* Enable the main output */
931 __HAL_TIM_MOE_ENABLE(htim);
932 }
933
934 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
935 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
936 {
937 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
938 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
939 {
940 __HAL_TIM_ENABLE(htim);
941 }
942 }
943 else
944 {
945 __HAL_TIM_ENABLE(htim);
946 }
947
948 /* Return function status */
949 return HAL_OK;
950}
951
952/**
953 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
954 * @param htim TIM Output Compare handle
955 * @param Channel TIM Channel to be disabled
956 * This parameter can be one of the following values:
957 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
958 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
959 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
960 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
961 * @retval HAL status
962 */
963HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
964{
965 /* Check the parameters */
966 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
967
968 switch (Channel)
969 {
970 case TIM_CHANNEL_1:
971 {
972 /* Disable the TIM Capture/Compare 1 interrupt */
973 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
974 break;
975 }
976
977 case TIM_CHANNEL_2:
978 {
979 /* Disable the TIM Capture/Compare 2 interrupt */
980 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
981 break;
982 }
983
984 case TIM_CHANNEL_3:
985 {
986 /* Disable the TIM Capture/Compare 3 interrupt */
987 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
988 break;
989 }
990
991 case TIM_CHANNEL_4:
992 {
993 /* Disable the TIM Capture/Compare 4 interrupt */
994 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
995 break;
996 }
997
998 default:
999 break;
1000 }
1001
1002 /* Disable the Output compare channel */
1003 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1004
1005 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1006 {
1007 /* Disable the Main Output */
1008 __HAL_TIM_MOE_DISABLE(htim);
1009 }
1010
1011 /* Disable the Peripheral */
1012 __HAL_TIM_DISABLE(htim);
1013
1014 /* Set the TIM channel state */
1015 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1016
1017 /* Return function status */
1018 return HAL_OK;
1019}
1020
1021/**
1022 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1023 * @param htim TIM Output Compare handle
1024 * @param Channel TIM Channel to be enabled
1025 * This parameter can be one of the following values:
1026 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1027 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1028 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1029 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1030 * @param pData The source Buffer address.
1031 * @param Length The length of data to be transferred from memory to TIM peripheral
1032 * @retval HAL status
1033 */
1034HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1035{
1036 uint32_t tmpsmcr;
1037
1038 /* Check the parameters */
1039 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1040
1041 /* Set the TIM channel state */
1042 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1043 {
1044 return HAL_BUSY;
1045 }
1046 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1047 {
1048 if ((pData == NULL) && (Length > 0U))
1049 {
1050 return HAL_ERROR;
1051 }
1052 else
1053 {
1054 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1055 }
1056 }
1057 else
1058 {
1059 return HAL_ERROR;
1060 }
1061
1062 switch (Channel)
1063 {
1064 case TIM_CHANNEL_1:
1065 {
1066 /* Set the DMA compare callbacks */
1067 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1068 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1069
1070 /* Set the DMA error callback */
1071 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1072
1073 /* Enable the DMA stream */
1074 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1075 {
1076 /* Return error status */
1077 return HAL_ERROR;
1078 }
1079
1080 /* Enable the TIM Capture/Compare 1 DMA request */
1081 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1082 break;
1083 }
1084
1085 case TIM_CHANNEL_2:
1086 {
1087 /* Set the DMA compare callbacks */
1088 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1089 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1090
1091 /* Set the DMA error callback */
1092 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1093
1094 /* Enable the DMA stream */
1095 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1096 {
1097 /* Return error status */
1098 return HAL_ERROR;
1099 }
1100
1101 /* Enable the TIM Capture/Compare 2 DMA request */
1102 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1103 break;
1104 }
1105
1106 case TIM_CHANNEL_3:
1107 {
1108 /* Set the DMA compare callbacks */
1109 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1110 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1111
1112 /* Set the DMA error callback */
1113 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1114
1115 /* Enable the DMA stream */
1116 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1117 {
1118 /* Return error status */
1119 return HAL_ERROR;
1120 }
1121 /* Enable the TIM Capture/Compare 3 DMA request */
1122 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1123 break;
1124 }
1125
1126 case TIM_CHANNEL_4:
1127 {
1128 /* Set the DMA compare callbacks */
1129 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1130 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1131
1132 /* Set the DMA error callback */
1133 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1134
1135 /* Enable the DMA stream */
1136 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1137 {
1138 /* Return error status */
1139 return HAL_ERROR;
1140 }
1141 /* Enable the TIM Capture/Compare 4 DMA request */
1142 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1143 break;
1144 }
1145
1146 default:
1147 break;
1148 }
1149
1150 /* Enable the Output compare channel */
1151 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1152
1153 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1154 {
1155 /* Enable the main output */
1156 __HAL_TIM_MOE_ENABLE(htim);
1157 }
1158
1159 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1160 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1161 {
1162 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1163 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1164 {
1165 __HAL_TIM_ENABLE(htim);
1166 }
1167 }
1168 else
1169 {
1170 __HAL_TIM_ENABLE(htim);
1171 }
1172
1173 /* Return function status */
1174 return HAL_OK;
1175}
1176
1177/**
1178 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1179 * @param htim TIM Output Compare handle
1180 * @param Channel TIM Channel to be disabled
1181 * This parameter can be one of the following values:
1182 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1183 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1184 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1185 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1186 * @retval HAL status
1187 */
1188HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1189{
1190 /* Check the parameters */
1191 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1192
1193 switch (Channel)
1194 {
1195 case TIM_CHANNEL_1:
1196 {
1197 /* Disable the TIM Capture/Compare 1 DMA request */
1198 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1199 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1200 break;
1201 }
1202
1203 case TIM_CHANNEL_2:
1204 {
1205 /* Disable the TIM Capture/Compare 2 DMA request */
1206 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1207 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1208 break;
1209 }
1210
1211 case TIM_CHANNEL_3:
1212 {
1213 /* Disable the TIM Capture/Compare 3 DMA request */
1214 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1215 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1216 break;
1217 }
1218
1219 case TIM_CHANNEL_4:
1220 {
1221 /* Disable the TIM Capture/Compare 4 interrupt */
1222 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1223 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1224 break;
1225 }
1226
1227 default:
1228 break;
1229 }
1230
1231 /* Disable the Output compare channel */
1232 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1233
1234 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1235 {
1236 /* Disable the Main Output */
1237 __HAL_TIM_MOE_DISABLE(htim);
1238 }
1239
1240 /* Disable the Peripheral */
1241 __HAL_TIM_DISABLE(htim);
1242
1243 /* Set the TIM channel state */
1244 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1245
1246 /* Return function status */
1247 return HAL_OK;
1248}
1249
1250/**
1251 * @}
1252 */
1253
1254/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1255 * @brief TIM PWM functions
1256 *
1257@verbatim
1258 ==============================================================================
1259 ##### TIM PWM functions #####
1260 ==============================================================================
1261 [..]
1262 This section provides functions allowing to:
1263 (+) Initialize and configure the TIM PWM.
1264 (+) De-initialize the TIM PWM.
1265 (+) Start the TIM PWM.
1266 (+) Stop the TIM PWM.
1267 (+) Start the TIM PWM and enable interrupt.
1268 (+) Stop the TIM PWM and disable interrupt.
1269 (+) Start the TIM PWM and enable DMA transfer.
1270 (+) Stop the TIM PWM and disable DMA transfer.
1271
1272@endverbatim
1273 * @{
1274 */
1275/**
1276 * @brief Initializes the TIM PWM Time Base according to the specified
1277 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1278 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1279 * requires a timer reset to avoid unexpected direction
1280 * due to DIR bit readonly in center aligned mode.
1281 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1282 * @param htim TIM PWM handle
1283 * @retval HAL status
1284 */
1285HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1286{
1287 /* Check the TIM handle allocation */
1288 if (htim == NULL)
1289 {
1290 return HAL_ERROR;
1291 }
1292
1293 /* Check the parameters */
1294 assert_param(IS_TIM_INSTANCE(htim->Instance));
1295 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1296 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1297 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1298
1299 if (htim->State == HAL_TIM_STATE_RESET)
1300 {
1301 /* Allocate lock resource and initialize it */
1302 htim->Lock = HAL_UNLOCKED;
1303
1304#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1305 /* Reset interrupt callbacks to legacy weak callbacks */
1306 TIM_ResetCallback(htim);
1307
1308 if (htim->PWM_MspInitCallback == NULL)
1309 {
1310 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1311 }
1312 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1313 htim->PWM_MspInitCallback(htim);
1314#else
1315 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1316 HAL_TIM_PWM_MspInit(htim);
1317#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1318 }
1319
1320 /* Set the TIM state */
1321 htim->State = HAL_TIM_STATE_BUSY;
1322
1323 /* Init the base time for the PWM */
1324 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1325
1326 /* Initialize the DMA burst operation state */
1327 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1328
1329 /* Initialize the TIM channels state */
1330 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1331 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1332
1333 /* Initialize the TIM state*/
1334 htim->State = HAL_TIM_STATE_READY;
1335
1336 return HAL_OK;
1337}
1338
1339/**
1340 * @brief DeInitializes the TIM peripheral
1341 * @param htim TIM PWM handle
1342 * @retval HAL status
1343 */
1344HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1345{
1346 /* Check the parameters */
1347 assert_param(IS_TIM_INSTANCE(htim->Instance));
1348
1349 htim->State = HAL_TIM_STATE_BUSY;
1350
1351 /* Disable the TIM Peripheral Clock */
1352 __HAL_TIM_DISABLE(htim);
1353
1354#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1355 if (htim->PWM_MspDeInitCallback == NULL)
1356 {
1357 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1358 }
1359 /* DeInit the low level hardware */
1360 htim->PWM_MspDeInitCallback(htim);
1361#else
1362 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1363 HAL_TIM_PWM_MspDeInit(htim);
1364#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1365
1366 /* Change the DMA burst operation state */
1367 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1368
1369 /* Change the TIM channels state */
1370 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1371 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1372
1373 /* Change TIM state */
1374 htim->State = HAL_TIM_STATE_RESET;
1375
1376 /* Release Lock */
1377 __HAL_UNLOCK(htim);
1378
1379 return HAL_OK;
1380}
1381
1382/**
1383 * @brief Initializes the TIM PWM MSP.
1384 * @param htim TIM PWM handle
1385 * @retval None
1386 */
1387__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1388{
1389 /* Prevent unused argument(s) compilation warning */
1390 UNUSED(htim);
1391
1392 /* NOTE : This function should not be modified, when the callback is needed,
1393 the HAL_TIM_PWM_MspInit could be implemented in the user file
1394 */
1395}
1396
1397/**
1398 * @brief DeInitializes TIM PWM MSP.
1399 * @param htim TIM PWM handle
1400 * @retval None
1401 */
1402__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1403{
1404 /* Prevent unused argument(s) compilation warning */
1405 UNUSED(htim);
1406
1407 /* NOTE : This function should not be modified, when the callback is needed,
1408 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1409 */
1410}
1411
1412/**
1413 * @brief Starts the PWM signal generation.
1414 * @param htim TIM handle
1415 * @param Channel TIM Channels to be enabled
1416 * This parameter can be one of the following values:
1417 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1418 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1419 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1420 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1421 * @retval HAL status
1422 */
1423HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1424{
1425 uint32_t tmpsmcr;
1426
1427 /* Check the parameters */
1428 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1429
1430 /* Check the TIM channel state */
1431 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1432 {
1433 return HAL_ERROR;
1434 }
1435
1436 /* Set the TIM channel state */
1437 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1438
1439 /* Enable the Capture compare channel */
1440 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1441
1442 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1443 {
1444 /* Enable the main output */
1445 __HAL_TIM_MOE_ENABLE(htim);
1446 }
1447
1448 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1449 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1450 {
1451 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1452 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1453 {
1454 __HAL_TIM_ENABLE(htim);
1455 }
1456 }
1457 else
1458 {
1459 __HAL_TIM_ENABLE(htim);
1460 }
1461
1462 /* Return function status */
1463 return HAL_OK;
1464}
1465
1466/**
1467 * @brief Stops the PWM signal generation.
1468 * @param htim TIM PWM handle
1469 * @param Channel TIM Channels to be disabled
1470 * This parameter can be one of the following values:
1471 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1472 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1473 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1474 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1475 * @retval HAL status
1476 */
1477HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1478{
1479 /* Check the parameters */
1480 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1481
1482 /* Disable the Capture compare channel */
1483 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1484
1485 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1486 {
1487 /* Disable the Main Output */
1488 __HAL_TIM_MOE_DISABLE(htim);
1489 }
1490
1491 /* Disable the Peripheral */
1492 __HAL_TIM_DISABLE(htim);
1493
1494 /* Set the TIM channel state */
1495 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1496
1497 /* Return function status */
1498 return HAL_OK;
1499}
1500
1501/**
1502 * @brief Starts the PWM signal generation in interrupt mode.
1503 * @param htim TIM PWM handle
1504 * @param Channel TIM Channel to be enabled
1505 * This parameter can be one of the following values:
1506 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1507 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1508 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1509 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1510 * @retval HAL status
1511 */
1512HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1513{
1514 uint32_t tmpsmcr;
1515 /* Check the parameters */
1516 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1517
1518 /* Check the TIM channel state */
1519 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1520 {
1521 return HAL_ERROR;
1522 }
1523
1524 /* Set the TIM channel state */
1525 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1526
1527 switch (Channel)
1528 {
1529 case TIM_CHANNEL_1:
1530 {
1531 /* Enable the TIM Capture/Compare 1 interrupt */
1532 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1533 break;
1534 }
1535
1536 case TIM_CHANNEL_2:
1537 {
1538 /* Enable the TIM Capture/Compare 2 interrupt */
1539 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1540 break;
1541 }
1542
1543 case TIM_CHANNEL_3:
1544 {
1545 /* Enable the TIM Capture/Compare 3 interrupt */
1546 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1547 break;
1548 }
1549
1550 case TIM_CHANNEL_4:
1551 {
1552 /* Enable the TIM Capture/Compare 4 interrupt */
1553 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1554 break;
1555 }
1556
1557 default:
1558 break;
1559 }
1560
1561 /* Enable the Capture compare channel */
1562 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1563
1564 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1565 {
1566 /* Enable the main output */
1567 __HAL_TIM_MOE_ENABLE(htim);
1568 }
1569
1570 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1571 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1572 {
1573 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1574 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1575 {
1576 __HAL_TIM_ENABLE(htim);
1577 }
1578 }
1579 else
1580 {
1581 __HAL_TIM_ENABLE(htim);
1582 }
1583
1584 /* Return function status */
1585 return HAL_OK;
1586}
1587
1588/**
1589 * @brief Stops the PWM signal generation in interrupt mode.
1590 * @param htim TIM PWM handle
1591 * @param Channel TIM Channels to be disabled
1592 * This parameter can be one of the following values:
1593 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1594 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1595 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1596 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1597 * @retval HAL status
1598 */
1599HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1600{
1601 /* Check the parameters */
1602 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1603
1604 switch (Channel)
1605 {
1606 case TIM_CHANNEL_1:
1607 {
1608 /* Disable the TIM Capture/Compare 1 interrupt */
1609 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1610 break;
1611 }
1612
1613 case TIM_CHANNEL_2:
1614 {
1615 /* Disable the TIM Capture/Compare 2 interrupt */
1616 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1617 break;
1618 }
1619
1620 case TIM_CHANNEL_3:
1621 {
1622 /* Disable the TIM Capture/Compare 3 interrupt */
1623 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1624 break;
1625 }
1626
1627 case TIM_CHANNEL_4:
1628 {
1629 /* Disable the TIM Capture/Compare 4 interrupt */
1630 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1631 break;
1632 }
1633
1634 default:
1635 break;
1636 }
1637
1638 /* Disable the Capture compare channel */
1639 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1640
1641 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1642 {
1643 /* Disable the Main Output */
1644 __HAL_TIM_MOE_DISABLE(htim);
1645 }
1646
1647 /* Disable the Peripheral */
1648 __HAL_TIM_DISABLE(htim);
1649
1650 /* Set the TIM channel state */
1651 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1652
1653 /* Return function status */
1654 return HAL_OK;
1655}
1656
1657/**
1658 * @brief Starts the TIM PWM signal generation in DMA mode.
1659 * @param htim TIM PWM handle
1660 * @param Channel TIM Channels to be enabled
1661 * This parameter can be one of the following values:
1662 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1663 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1664 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1665 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1666 * @param pData The source Buffer address.
1667 * @param Length The length of data to be transferred from memory to TIM peripheral
1668 * @retval HAL status
1669 */
1670HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1671{
1672 uint32_t tmpsmcr;
1673
1674 /* Check the parameters */
1675 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1676
1677 /* Set the TIM channel state */
1678 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1679 {
1680 return HAL_BUSY;
1681 }
1682 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1683 {
1684 if ((pData == NULL) && (Length > 0U))
1685 {
1686 return HAL_ERROR;
1687 }
1688 else
1689 {
1690 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1691 }
1692 }
1693 else
1694 {
1695 return HAL_ERROR;
1696 }
1697
1698 switch (Channel)
1699 {
1700 case TIM_CHANNEL_1:
1701 {
1702 /* Set the DMA compare callbacks */
1703 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1704 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1705
1706 /* Set the DMA error callback */
1707 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1708
1709 /* Enable the DMA stream */
1710 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1711 {
1712 /* Return error status */
1713 return HAL_ERROR;
1714 }
1715
1716 /* Enable the TIM Capture/Compare 1 DMA request */
1717 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1718 break;
1719 }
1720
1721 case TIM_CHANNEL_2:
1722 {
1723 /* Set the DMA compare callbacks */
1724 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1725 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1726
1727 /* Set the DMA error callback */
1728 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1729
1730 /* Enable the DMA stream */
1731 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1732 {
1733 /* Return error status */
1734 return HAL_ERROR;
1735 }
1736 /* Enable the TIM Capture/Compare 2 DMA request */
1737 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1738 break;
1739 }
1740
1741 case TIM_CHANNEL_3:
1742 {
1743 /* Set the DMA compare callbacks */
1744 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1745 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1746
1747 /* Set the DMA error callback */
1748 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1749
1750 /* Enable the DMA stream */
1751 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1752 {
1753 /* Return error status */
1754 return HAL_ERROR;
1755 }
1756 /* Enable the TIM Output Capture/Compare 3 request */
1757 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1758 break;
1759 }
1760
1761 case TIM_CHANNEL_4:
1762 {
1763 /* Set the DMA compare callbacks */
1764 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1765 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1766
1767 /* Set the DMA error callback */
1768 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1769
1770 /* Enable the DMA stream */
1771 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1772 {
1773 /* Return error status */
1774 return HAL_ERROR;
1775 }
1776 /* Enable the TIM Capture/Compare 4 DMA request */
1777 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1778 break;
1779 }
1780
1781 default:
1782 break;
1783 }
1784
1785 /* Enable the Capture compare channel */
1786 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1787
1788 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1789 {
1790 /* Enable the main output */
1791 __HAL_TIM_MOE_ENABLE(htim);
1792 }
1793
1794 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1795 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1796 {
1797 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1798 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1799 {
1800 __HAL_TIM_ENABLE(htim);
1801 }
1802 }
1803 else
1804 {
1805 __HAL_TIM_ENABLE(htim);
1806 }
1807
1808 /* Return function status */
1809 return HAL_OK;
1810}
1811
1812/**
1813 * @brief Stops the TIM PWM signal generation in DMA mode.
1814 * @param htim TIM PWM handle
1815 * @param Channel TIM Channels to be disabled
1816 * This parameter can be one of the following values:
1817 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1818 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1819 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1820 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1821 * @retval HAL status
1822 */
1823HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1824{
1825 /* Check the parameters */
1826 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1827
1828 switch (Channel)
1829 {
1830 case TIM_CHANNEL_1:
1831 {
1832 /* Disable the TIM Capture/Compare 1 DMA request */
1833 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1834 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1835 break;
1836 }
1837
1838 case TIM_CHANNEL_2:
1839 {
1840 /* Disable the TIM Capture/Compare 2 DMA request */
1841 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1842 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1843 break;
1844 }
1845
1846 case TIM_CHANNEL_3:
1847 {
1848 /* Disable the TIM Capture/Compare 3 DMA request */
1849 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1850 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1851 break;
1852 }
1853
1854 case TIM_CHANNEL_4:
1855 {
1856 /* Disable the TIM Capture/Compare 4 interrupt */
1857 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1858 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1859 break;
1860 }
1861
1862 default:
1863 break;
1864 }
1865
1866 /* Disable the Capture compare channel */
1867 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1868
1869 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1870 {
1871 /* Disable the Main Output */
1872 __HAL_TIM_MOE_DISABLE(htim);
1873 }
1874
1875 /* Disable the Peripheral */
1876 __HAL_TIM_DISABLE(htim);
1877
1878 /* Set the TIM channel state */
1879 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1880
1881 /* Return function status */
1882 return HAL_OK;
1883}
1884
1885/**
1886 * @}
1887 */
1888
1889/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1890 * @brief TIM Input Capture functions
1891 *
1892@verbatim
1893 ==============================================================================
1894 ##### TIM Input Capture functions #####
1895 ==============================================================================
1896 [..]
1897 This section provides functions allowing to:
1898 (+) Initialize and configure the TIM Input Capture.
1899 (+) De-initialize the TIM Input Capture.
1900 (+) Start the TIM Input Capture.
1901 (+) Stop the TIM Input Capture.
1902 (+) Start the TIM Input Capture and enable interrupt.
1903 (+) Stop the TIM Input Capture and disable interrupt.
1904 (+) Start the TIM Input Capture and enable DMA transfer.
1905 (+) Stop the TIM Input Capture and disable DMA transfer.
1906
1907@endverbatim
1908 * @{
1909 */
1910/**
1911 * @brief Initializes the TIM Input Capture Time base according to the specified
1912 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1913 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1914 * requires a timer reset to avoid unexpected direction
1915 * due to DIR bit readonly in center aligned mode.
1916 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1917 * @param htim TIM Input Capture handle
1918 * @retval HAL status
1919 */
1920HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1921{
1922 /* Check the TIM handle allocation */
1923 if (htim == NULL)
1924 {
1925 return HAL_ERROR;
1926 }
1927
1928 /* Check the parameters */
1929 assert_param(IS_TIM_INSTANCE(htim->Instance));
1930 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1931 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1932 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1933
1934 if (htim->State == HAL_TIM_STATE_RESET)
1935 {
1936 /* Allocate lock resource and initialize it */
1937 htim->Lock = HAL_UNLOCKED;
1938
1939#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1940 /* Reset interrupt callbacks to legacy weak callbacks */
1941 TIM_ResetCallback(htim);
1942
1943 if (htim->IC_MspInitCallback == NULL)
1944 {
1945 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
1946 }
1947 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1948 htim->IC_MspInitCallback(htim);
1949#else
1950 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1951 HAL_TIM_IC_MspInit(htim);
1952#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1953 }
1954
1955 /* Set the TIM state */
1956 htim->State = HAL_TIM_STATE_BUSY;
1957
1958 /* Init the base time for the input capture */
1959 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1960
1961 /* Initialize the DMA burst operation state */
1962 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1963
1964 /* Initialize the TIM channels state */
1965 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1966 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1967
1968 /* Initialize the TIM state*/
1969 htim->State = HAL_TIM_STATE_READY;
1970
1971 return HAL_OK;
1972}
1973
1974/**
1975 * @brief DeInitializes the TIM peripheral
1976 * @param htim TIM Input Capture handle
1977 * @retval HAL status
1978 */
1979HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1980{
1981 /* Check the parameters */
1982 assert_param(IS_TIM_INSTANCE(htim->Instance));
1983
1984 htim->State = HAL_TIM_STATE_BUSY;
1985
1986 /* Disable the TIM Peripheral Clock */
1987 __HAL_TIM_DISABLE(htim);
1988
1989#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1990 if (htim->IC_MspDeInitCallback == NULL)
1991 {
1992 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
1993 }
1994 /* DeInit the low level hardware */
1995 htim->IC_MspDeInitCallback(htim);
1996#else
1997 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1998 HAL_TIM_IC_MspDeInit(htim);
1999#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2000
2001 /* Change the DMA burst operation state */
2002 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2003
2004 /* Change the TIM channels state */
2005 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2006 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2007
2008 /* Change TIM state */
2009 htim->State = HAL_TIM_STATE_RESET;
2010
2011 /* Release Lock */
2012 __HAL_UNLOCK(htim);
2013
2014 return HAL_OK;
2015}
2016
2017/**
2018 * @brief Initializes the TIM Input Capture MSP.
2019 * @param htim TIM Input Capture handle
2020 * @retval None
2021 */
2022__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2023{
2024 /* Prevent unused argument(s) compilation warning */
2025 UNUSED(htim);
2026
2027 /* NOTE : This function should not be modified, when the callback is needed,
2028 the HAL_TIM_IC_MspInit could be implemented in the user file
2029 */
2030}
2031
2032/**
2033 * @brief DeInitializes TIM Input Capture MSP.
2034 * @param htim TIM handle
2035 * @retval None
2036 */
2037__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2038{
2039 /* Prevent unused argument(s) compilation warning */
2040 UNUSED(htim);
2041
2042 /* NOTE : This function should not be modified, when the callback is needed,
2043 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2044 */
2045}
2046
2047/**
2048 * @brief Starts the TIM Input Capture measurement.
2049 * @param htim TIM Input Capture handle
2050 * @param Channel TIM Channels to be enabled
2051 * This parameter can be one of the following values:
2052 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2053 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2054 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2055 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2056 * @retval HAL status
2057 */
2058HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2059{
2060 uint32_t tmpsmcr;
2061 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2062 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2063
2064 /* Check the parameters */
2065 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2066
2067 /* Check the TIM channel state */
2068 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2069 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2070 {
2071 return HAL_ERROR;
2072 }
2073
2074 /* Set the TIM channel state */
2075 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2076 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2077
2078 /* Enable the Input Capture channel */
2079 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2080
2081 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2082 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2083 {
2084 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2085 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2086 {
2087 __HAL_TIM_ENABLE(htim);
2088 }
2089 }
2090 else
2091 {
2092 __HAL_TIM_ENABLE(htim);
2093 }
2094
2095 /* Return function status */
2096 return HAL_OK;
2097}
2098
2099/**
2100 * @brief Stops the TIM Input Capture measurement.
2101 * @param htim TIM Input Capture handle
2102 * @param Channel TIM Channels to be disabled
2103 * This parameter can be one of the following values:
2104 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2105 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2106 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2107 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2108 * @retval HAL status
2109 */
2110HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2111{
2112 /* Check the parameters */
2113 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2114
2115 /* Disable the Input Capture channel */
2116 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2117
2118 /* Disable the Peripheral */
2119 __HAL_TIM_DISABLE(htim);
2120
2121 /* Set the TIM channel state */
2122 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2123 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2124
2125 /* Return function status */
2126 return HAL_OK;
2127}
2128
2129/**
2130 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2131 * @param htim TIM Input Capture handle
2132 * @param Channel TIM Channels to be enabled
2133 * This parameter can be one of the following values:
2134 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2135 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2136 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2137 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2138 * @retval HAL status
2139 */
2140HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2141{
2142 uint32_t tmpsmcr;
2143 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2144 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2145
2146 /* Check the parameters */
2147 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2148
2149 /* Check the TIM channel state */
2150 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2151 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2152 {
2153 return HAL_ERROR;
2154 }
2155
2156 /* Set the TIM channel state */
2157 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2158 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2159
2160 switch (Channel)
2161 {
2162 case TIM_CHANNEL_1:
2163 {
2164 /* Enable the TIM Capture/Compare 1 interrupt */
2165 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2166 break;
2167 }
2168
2169 case TIM_CHANNEL_2:
2170 {
2171 /* Enable the TIM Capture/Compare 2 interrupt */
2172 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2173 break;
2174 }
2175
2176 case TIM_CHANNEL_3:
2177 {
2178 /* Enable the TIM Capture/Compare 3 interrupt */
2179 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2180 break;
2181 }
2182
2183 case TIM_CHANNEL_4:
2184 {
2185 /* Enable the TIM Capture/Compare 4 interrupt */
2186 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2187 break;
2188 }
2189
2190 default:
2191 break;
2192 }
2193 /* Enable the Input Capture channel */
2194 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2195
2196 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2197 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2198 {
2199 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2200 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2201 {
2202 __HAL_TIM_ENABLE(htim);
2203 }
2204 }
2205 else
2206 {
2207 __HAL_TIM_ENABLE(htim);
2208 }
2209
2210 /* Return function status */
2211 return HAL_OK;
2212}
2213
2214/**
2215 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2216 * @param htim TIM Input Capture handle
2217 * @param Channel TIM Channels to be disabled
2218 * This parameter can be one of the following values:
2219 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2220 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2221 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2222 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2223 * @retval HAL status
2224 */
2225HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2226{
2227 /* Check the parameters */
2228 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2229
2230 switch (Channel)
2231 {
2232 case TIM_CHANNEL_1:
2233 {
2234 /* Disable the TIM Capture/Compare 1 interrupt */
2235 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2236 break;
2237 }
2238
2239 case TIM_CHANNEL_2:
2240 {
2241 /* Disable the TIM Capture/Compare 2 interrupt */
2242 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2243 break;
2244 }
2245
2246 case TIM_CHANNEL_3:
2247 {
2248 /* Disable the TIM Capture/Compare 3 interrupt */
2249 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2250 break;
2251 }
2252
2253 case TIM_CHANNEL_4:
2254 {
2255 /* Disable the TIM Capture/Compare 4 interrupt */
2256 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2257 break;
2258 }
2259
2260 default:
2261 break;
2262 }
2263
2264 /* Disable the Input Capture channel */
2265 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2266
2267 /* Disable the Peripheral */
2268 __HAL_TIM_DISABLE(htim);
2269
2270 /* Set the TIM channel state */
2271 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2272 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2273
2274 /* Return function status */
2275 return HAL_OK;
2276}
2277
2278/**
2279 * @brief Starts the TIM Input Capture measurement in DMA mode.
2280 * @param htim TIM Input Capture handle
2281 * @param Channel TIM Channels to be enabled
2282 * This parameter can be one of the following values:
2283 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2284 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2285 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2286 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2287 * @param pData The destination Buffer address.
2288 * @param Length The length of data to be transferred from TIM peripheral to memory.
2289 * @retval HAL status
2290 */
2291HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2292{
2293 uint32_t tmpsmcr;
2294 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2295 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2296
2297 /* Check the parameters */
2298 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2299 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2300
2301 /* Set the TIM channel state */
2302 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2303 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2304 {
2305 return HAL_BUSY;
2306 }
2307 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2308 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2309 {
2310 if ((pData == NULL) && (Length > 0U))
2311 {
2312 return HAL_ERROR;
2313 }
2314 else
2315 {
2316 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2317 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2318 }
2319 }
2320 else
2321 {
2322 return HAL_ERROR;
2323 }
2324
2325 switch (Channel)
2326 {
2327 case TIM_CHANNEL_1:
2328 {
2329 /* Set the DMA capture callbacks */
2330 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2331 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2332
2333 /* Set the DMA error callback */
2334 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2335
2336 /* Enable the DMA stream */
2337 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2338 {
2339 /* Return error status */
2340 return HAL_ERROR;
2341 }
2342 /* Enable the TIM Capture/Compare 1 DMA request */
2343 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2344 break;
2345 }
2346
2347 case TIM_CHANNEL_2:
2348 {
2349 /* Set the DMA capture callbacks */
2350 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2351 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2352
2353 /* Set the DMA error callback */
2354 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2355
2356 /* Enable the DMA stream */
2357 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2358 {
2359 /* Return error status */
2360 return HAL_ERROR;
2361 }
2362 /* Enable the TIM Capture/Compare 2 DMA request */
2363 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2364 break;
2365 }
2366
2367 case TIM_CHANNEL_3:
2368 {
2369 /* Set the DMA capture callbacks */
2370 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2371 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2372
2373 /* Set the DMA error callback */
2374 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2375
2376 /* Enable the DMA stream */
2377 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
2378 {
2379 /* Return error status */
2380 return HAL_ERROR;
2381 }
2382 /* Enable the TIM Capture/Compare 3 DMA request */
2383 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2384 break;
2385 }
2386
2387 case TIM_CHANNEL_4:
2388 {
2389 /* Set the DMA capture callbacks */
2390 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2391 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2392
2393 /* Set the DMA error callback */
2394 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2395
2396 /* Enable the DMA stream */
2397 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
2398 {
2399 /* Return error status */
2400 return HAL_ERROR;
2401 }
2402 /* Enable the TIM Capture/Compare 4 DMA request */
2403 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2404 break;
2405 }
2406
2407 default:
2408 break;
2409 }
2410
2411 /* Enable the Input Capture channel */
2412 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2413
2414 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2415 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2416 {
2417 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2418 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2419 {
2420 __HAL_TIM_ENABLE(htim);
2421 }
2422 }
2423 else
2424 {
2425 __HAL_TIM_ENABLE(htim);
2426 }
2427
2428 /* Return function status */
2429 return HAL_OK;
2430}
2431
2432/**
2433 * @brief Stops the TIM Input Capture measurement in DMA mode.
2434 * @param htim TIM Input Capture handle
2435 * @param Channel TIM Channels to be disabled
2436 * This parameter can be one of the following values:
2437 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2438 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2439 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2440 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2441 * @retval HAL status
2442 */
2443HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2444{
2445 /* Check the parameters */
2446 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2447 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2448
2449 /* Disable the Input Capture channel */
2450 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2451
2452 switch (Channel)
2453 {
2454 case TIM_CHANNEL_1:
2455 {
2456 /* Disable the TIM Capture/Compare 1 DMA request */
2457 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2458 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2459 break;
2460 }
2461
2462 case TIM_CHANNEL_2:
2463 {
2464 /* Disable the TIM Capture/Compare 2 DMA request */
2465 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2466 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2467 break;
2468 }
2469
2470 case TIM_CHANNEL_3:
2471 {
2472 /* Disable the TIM Capture/Compare 3 DMA request */
2473 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2474 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2475 break;
2476 }
2477
2478 case TIM_CHANNEL_4:
2479 {
2480 /* Disable the TIM Capture/Compare 4 DMA request */
2481 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2482 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2483 break;
2484 }
2485
2486 default:
2487 break;
2488 }
2489
2490 /* Disable the Peripheral */
2491 __HAL_TIM_DISABLE(htim);
2492
2493 /* Set the TIM channel state */
2494 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2495 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2496
2497 /* Return function status */
2498 return HAL_OK;
2499}
2500/**
2501 * @}
2502 */
2503
2504/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2505 * @brief TIM One Pulse functions
2506 *
2507@verbatim
2508 ==============================================================================
2509 ##### TIM One Pulse functions #####
2510 ==============================================================================
2511 [..]
2512 This section provides functions allowing to:
2513 (+) Initialize and configure the TIM One Pulse.
2514 (+) De-initialize the TIM One Pulse.
2515 (+) Start the TIM One Pulse.
2516 (+) Stop the TIM One Pulse.
2517 (+) Start the TIM One Pulse and enable interrupt.
2518 (+) Stop the TIM One Pulse and disable interrupt.
2519 (+) Start the TIM One Pulse and enable DMA transfer.
2520 (+) Stop the TIM One Pulse and disable DMA transfer.
2521
2522@endverbatim
2523 * @{
2524 */
2525/**
2526 * @brief Initializes the TIM One Pulse Time Base according to the specified
2527 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2528 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2529 * requires a timer reset to avoid unexpected direction
2530 * due to DIR bit readonly in center aligned mode.
2531 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2532 * @note When the timer instance is initialized in One Pulse mode, timer
2533 * channels 1 and channel 2 are reserved and cannot be used for other
2534 * purpose.
2535 * @param htim TIM One Pulse handle
2536 * @param OnePulseMode Select the One pulse mode.
2537 * This parameter can be one of the following values:
2538 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2539 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2540 * @retval HAL status
2541 */
2542HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2543{
2544 /* Check the TIM handle allocation */
2545 if (htim == NULL)
2546 {
2547 return HAL_ERROR;
2548 }
2549
2550 /* Check the parameters */
2551 assert_param(IS_TIM_INSTANCE(htim->Instance));
2552 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2553 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2554 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2555 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2556
2557 if (htim->State == HAL_TIM_STATE_RESET)
2558 {
2559 /* Allocate lock resource and initialize it */
2560 htim->Lock = HAL_UNLOCKED;
2561
2562#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2563 /* Reset interrupt callbacks to legacy weak callbacks */
2564 TIM_ResetCallback(htim);
2565
2566 if (htim->OnePulse_MspInitCallback == NULL)
2567 {
2568 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2569 }
2570 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2571 htim->OnePulse_MspInitCallback(htim);
2572#else
2573 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2574 HAL_TIM_OnePulse_MspInit(htim);
2575#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2576 }
2577
2578 /* Set the TIM state */
2579 htim->State = HAL_TIM_STATE_BUSY;
2580
2581 /* Configure the Time base in the One Pulse Mode */
2582 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2583
2584 /* Reset the OPM Bit */
2585 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2586
2587 /* Configure the OPM Mode */
2588 htim->Instance->CR1 |= OnePulseMode;
2589
2590 /* Initialize the DMA burst operation state */
2591 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2592
2593 /* Initialize the TIM channels state */
2594 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2595 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2596 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2597 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2598
2599 /* Initialize the TIM state*/
2600 htim->State = HAL_TIM_STATE_READY;
2601
2602 return HAL_OK;
2603}
2604
2605/**
2606 * @brief DeInitializes the TIM One Pulse
2607 * @param htim TIM One Pulse handle
2608 * @retval HAL status
2609 */
2610HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2611{
2612 /* Check the parameters */
2613 assert_param(IS_TIM_INSTANCE(htim->Instance));
2614
2615 htim->State = HAL_TIM_STATE_BUSY;
2616
2617 /* Disable the TIM Peripheral Clock */
2618 __HAL_TIM_DISABLE(htim);
2619
2620#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2621 if (htim->OnePulse_MspDeInitCallback == NULL)
2622 {
2623 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2624 }
2625 /* DeInit the low level hardware */
2626 htim->OnePulse_MspDeInitCallback(htim);
2627#else
2628 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2629 HAL_TIM_OnePulse_MspDeInit(htim);
2630#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2631
2632 /* Change the DMA burst operation state */
2633 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2634
2635 /* Set the TIM channel state */
2636 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2637 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2638 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2639 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2640
2641 /* Change TIM state */
2642 htim->State = HAL_TIM_STATE_RESET;
2643
2644 /* Release Lock */
2645 __HAL_UNLOCK(htim);
2646
2647 return HAL_OK;
2648}
2649
2650/**
2651 * @brief Initializes the TIM One Pulse MSP.
2652 * @param htim TIM One Pulse handle
2653 * @retval None
2654 */
2655__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2656{
2657 /* Prevent unused argument(s) compilation warning */
2658 UNUSED(htim);
2659
2660 /* NOTE : This function should not be modified, when the callback is needed,
2661 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2662 */
2663}
2664
2665/**
2666 * @brief DeInitializes TIM One Pulse MSP.
2667 * @param htim TIM One Pulse handle
2668 * @retval None
2669 */
2670__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2671{
2672 /* Prevent unused argument(s) compilation warning */
2673 UNUSED(htim);
2674
2675 /* NOTE : This function should not be modified, when the callback is needed,
2676 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2677 */
2678}
2679
2680/**
2681 * @brief Starts the TIM One Pulse signal generation.
2682 * @note Though OutputChannel parameter is deprecated and ignored by the function
2683 * it has been kept to avoid HAL_TIM API compatibility break.
2684 * @note The pulse output channel is determined when calling
2685 * @ref HAL_TIM_OnePulse_ConfigChannel().
2686 * @param htim TIM One Pulse handle
2687 * @param OutputChannel See note above
2688 * @retval HAL status
2689 */
2690HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2691{
2692 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2693 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2694 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2695 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2696
2697 /* Prevent unused argument(s) compilation warning */
2698 UNUSED(OutputChannel);
2699
2700 /* Check the TIM channels state */
2701 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2702 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2703 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2704 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2705 {
2706 return HAL_ERROR;
2707 }
2708
2709 /* Set the TIM channels state */
2710 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2711 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2712 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2713 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2714
2715 /* Enable the Capture compare and the Input Capture channels
2716 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2717 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2718 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2719 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2720
2721 No need to enable the counter, it's enabled automatically by hardware
2722 (the counter starts in response to a stimulus and generate a pulse */
2723
2724 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2725 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2726
2727 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2728 {
2729 /* Enable the main output */
2730 __HAL_TIM_MOE_ENABLE(htim);
2731 }
2732
2733 /* Return function status */
2734 return HAL_OK;
2735}
2736
2737/**
2738 * @brief Stops the TIM One Pulse signal generation.
2739 * @note Though OutputChannel parameter is deprecated and ignored by the function
2740 * it has been kept to avoid HAL_TIM API compatibility break.
2741 * @note The pulse output channel is determined when calling
2742 * @ref HAL_TIM_OnePulse_ConfigChannel().
2743 * @param htim TIM One Pulse handle
2744 * @param OutputChannel See note above
2745 * @retval HAL status
2746 */
2747HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2748{
2749 /* Prevent unused argument(s) compilation warning */
2750 UNUSED(OutputChannel);
2751
2752 /* Disable the Capture compare and the Input Capture channels
2753 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2754 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2755 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2756 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2757
2758 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2759 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2760
2761 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2762 {
2763 /* Disable the Main Output */
2764 __HAL_TIM_MOE_DISABLE(htim);
2765 }
2766
2767 /* Disable the Peripheral */
2768 __HAL_TIM_DISABLE(htim);
2769
2770 /* Set the TIM channels state */
2771 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2772 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2773 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2774 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2775
2776 /* Return function status */
2777 return HAL_OK;
2778}
2779
2780/**
2781 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2782 * @note Though OutputChannel parameter is deprecated and ignored by the function
2783 * it has been kept to avoid HAL_TIM API compatibility break.
2784 * @note The pulse output channel is determined when calling
2785 * @ref HAL_TIM_OnePulse_ConfigChannel().
2786 * @param htim TIM One Pulse handle
2787 * @param OutputChannel See note above
2788 * @retval HAL status
2789 */
2790HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2791{
2792 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2793 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2794 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2795 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2796
2797 /* Prevent unused argument(s) compilation warning */
2798 UNUSED(OutputChannel);
2799
2800 /* Check the TIM channels state */
2801 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2802 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2803 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2804 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2805 {
2806 return HAL_ERROR;
2807 }
2808
2809 /* Set the TIM channels state */
2810 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2811 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2812 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2813 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2814
2815 /* Enable the Capture compare and the Input Capture channels
2816 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2817 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2818 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2819 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2820
2821 No need to enable the counter, it's enabled automatically by hardware
2822 (the counter starts in response to a stimulus and generate a pulse */
2823
2824 /* Enable the TIM Capture/Compare 1 interrupt */
2825 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2826
2827 /* Enable the TIM Capture/Compare 2 interrupt */
2828 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2829
2830 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2831 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2832
2833 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2834 {
2835 /* Enable the main output */
2836 __HAL_TIM_MOE_ENABLE(htim);
2837 }
2838
2839 /* Return function status */
2840 return HAL_OK;
2841}
2842
2843/**
2844 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2845 * @note Though OutputChannel parameter is deprecated and ignored by the function
2846 * it has been kept to avoid HAL_TIM API compatibility break.
2847 * @note The pulse output channel is determined when calling
2848 * @ref HAL_TIM_OnePulse_ConfigChannel().
2849 * @param htim TIM One Pulse handle
2850 * @param OutputChannel See note above
2851 * @retval HAL status
2852 */
2853HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2854{
2855 /* Prevent unused argument(s) compilation warning */
2856 UNUSED(OutputChannel);
2857
2858 /* Disable the TIM Capture/Compare 1 interrupt */
2859 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2860
2861 /* Disable the TIM Capture/Compare 2 interrupt */
2862 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2863
2864 /* Disable the Capture compare and the Input Capture channels
2865 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2866 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2867 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2868 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2869 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2870 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2871
2872 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2873 {
2874 /* Disable the Main Output */
2875 __HAL_TIM_MOE_DISABLE(htim);
2876 }
2877
2878 /* Disable the Peripheral */
2879 __HAL_TIM_DISABLE(htim);
2880
2881 /* Set the TIM channels state */
2882 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2883 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2884 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2885 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2886
2887 /* Return function status */
2888 return HAL_OK;
2889}
2890
2891/**
2892 * @}
2893 */
2894
2895/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2896 * @brief TIM Encoder functions
2897 *
2898@verbatim
2899 ==============================================================================
2900 ##### TIM Encoder functions #####
2901 ==============================================================================
2902 [..]
2903 This section provides functions allowing to:
2904 (+) Initialize and configure the TIM Encoder.
2905 (+) De-initialize the TIM Encoder.
2906 (+) Start the TIM Encoder.
2907 (+) Stop the TIM Encoder.
2908 (+) Start the TIM Encoder and enable interrupt.
2909 (+) Stop the TIM Encoder and disable interrupt.
2910 (+) Start the TIM Encoder and enable DMA transfer.
2911 (+) Stop the TIM Encoder and disable DMA transfer.
2912
2913@endverbatim
2914 * @{
2915 */
2916/**
2917 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
2918 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2919 * requires a timer reset to avoid unexpected direction
2920 * due to DIR bit readonly in center aligned mode.
2921 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
2922 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
2923 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
2924 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
2925 * @note When the timer instance is initialized in Encoder mode, timer
2926 * channels 1 and channel 2 are reserved and cannot be used for other
2927 * purpose.
2928 * @param htim TIM Encoder Interface handle
2929 * @param sConfig TIM Encoder Interface configuration structure
2930 * @retval HAL status
2931 */
2932HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
2933{
2934 uint32_t tmpsmcr;
2935 uint32_t tmpccmr1;
2936 uint32_t tmpccer;
2937
2938 /* Check the TIM handle allocation */
2939 if (htim == NULL)
2940 {
2941 return HAL_ERROR;
2942 }
2943
2944 /* Check the parameters */
2945 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2946 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2947 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2948 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2949 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2950 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2951 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2952 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
2953 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
2954 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2955 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2956 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2957 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2958
2959 if (htim->State == HAL_TIM_STATE_RESET)
2960 {
2961 /* Allocate lock resource and initialize it */
2962 htim->Lock = HAL_UNLOCKED;
2963
2964#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2965 /* Reset interrupt callbacks to legacy weak callbacks */
2966 TIM_ResetCallback(htim);
2967
2968 if (htim->Encoder_MspInitCallback == NULL)
2969 {
2970 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
2971 }
2972 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2973 htim->Encoder_MspInitCallback(htim);
2974#else
2975 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2976 HAL_TIM_Encoder_MspInit(htim);
2977#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2978 }
2979
2980 /* Set the TIM state */
2981 htim->State = HAL_TIM_STATE_BUSY;
2982
2983 /* Reset the SMS and ECE bits */
2984 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
2985
2986 /* Configure the Time base in the Encoder Mode */
2987 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2988
2989 /* Get the TIMx SMCR register value */
2990 tmpsmcr = htim->Instance->SMCR;
2991
2992 /* Get the TIMx CCMR1 register value */
2993 tmpccmr1 = htim->Instance->CCMR1;
2994
2995 /* Get the TIMx CCER register value */
2996 tmpccer = htim->Instance->CCER;
2997
2998 /* Set the encoder Mode */
2999 tmpsmcr |= sConfig->EncoderMode;
3000
3001 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3002 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3003 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3004
3005 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3006 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3007 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3008 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3009 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3010
3011 /* Set the TI1 and the TI2 Polarities */
3012 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3013 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3014 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3015
3016 /* Write to TIMx SMCR */
3017 htim->Instance->SMCR = tmpsmcr;
3018
3019 /* Write to TIMx CCMR1 */
3020 htim->Instance->CCMR1 = tmpccmr1;
3021
3022 /* Write to TIMx CCER */
3023 htim->Instance->CCER = tmpccer;
3024
3025 /* Initialize the DMA burst operation state */
3026 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3027
3028 /* Set the TIM channels state */
3029 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3030 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3031 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3032 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3033
3034 /* Initialize the TIM state*/
3035 htim->State = HAL_TIM_STATE_READY;
3036
3037 return HAL_OK;
3038}
3039
3040
3041/**
3042 * @brief DeInitializes the TIM Encoder interface
3043 * @param htim TIM Encoder Interface handle
3044 * @retval HAL status
3045 */
3046HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3047{
3048 /* Check the parameters */
3049 assert_param(IS_TIM_INSTANCE(htim->Instance));
3050
3051 htim->State = HAL_TIM_STATE_BUSY;
3052
3053 /* Disable the TIM Peripheral Clock */
3054 __HAL_TIM_DISABLE(htim);
3055
3056#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3057 if (htim->Encoder_MspDeInitCallback == NULL)
3058 {
3059 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3060 }
3061 /* DeInit the low level hardware */
3062 htim->Encoder_MspDeInitCallback(htim);
3063#else
3064 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3065 HAL_TIM_Encoder_MspDeInit(htim);
3066#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3067
3068 /* Change the DMA burst operation state */
3069 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3070
3071 /* Set the TIM channels state */
3072 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3073 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3074 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3075 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3076
3077 /* Change TIM state */
3078 htim->State = HAL_TIM_STATE_RESET;
3079
3080 /* Release Lock */
3081 __HAL_UNLOCK(htim);
3082
3083 return HAL_OK;
3084}
3085
3086/**
3087 * @brief Initializes the TIM Encoder Interface MSP.
3088 * @param htim TIM Encoder Interface handle
3089 * @retval None
3090 */
3091__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3092{
3093 /* Prevent unused argument(s) compilation warning */
3094 UNUSED(htim);
3095
3096 /* NOTE : This function should not be modified, when the callback is needed,
3097 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3098 */
3099}
3100
3101/**
3102 * @brief DeInitializes TIM Encoder Interface MSP.
3103 * @param htim TIM Encoder Interface handle
3104 * @retval None
3105 */
3106__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3107{
3108 /* Prevent unused argument(s) compilation warning */
3109 UNUSED(htim);
3110
3111 /* NOTE : This function should not be modified, when the callback is needed,
3112 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3113 */
3114}
3115
3116/**
3117 * @brief Starts the TIM Encoder Interface.
3118 * @param htim TIM Encoder Interface handle
3119 * @param Channel TIM Channels to be enabled
3120 * This parameter can be one of the following values:
3121 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3122 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3123 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3124 * @retval HAL status
3125 */
3126HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3127{
3128 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3129 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3130 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3131 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3132
3133 /* Check the parameters */
3134 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3135
3136 /* Set the TIM channel(s) state */
3137 if (Channel == TIM_CHANNEL_1)
3138 {
3139 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3140 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3141 {
3142 return HAL_ERROR;
3143 }
3144 else
3145 {
3146 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3147 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3148 }
3149 }
3150 else if (Channel == TIM_CHANNEL_2)
3151 {
3152 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3153 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3154 {
3155 return HAL_ERROR;
3156 }
3157 else
3158 {
3159 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3160 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3161 }
3162 }
3163 else
3164 {
3165 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3166 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3167 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3168 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3169 {
3170 return HAL_ERROR;
3171 }
3172 else
3173 {
3174 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3175 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3176 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3177 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3178 }
3179 }
3180
3181 /* Enable the encoder interface channels */
3182 switch (Channel)
3183 {
3184 case TIM_CHANNEL_1:
3185 {
3186 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3187 break;
3188 }
3189
3190 case TIM_CHANNEL_2:
3191 {
3192 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3193 break;
3194 }
3195
3196 default :
3197 {
3198 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3199 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3200 break;
3201 }
3202 }
3203 /* Enable the Peripheral */
3204 __HAL_TIM_ENABLE(htim);
3205
3206 /* Return function status */
3207 return HAL_OK;
3208}
3209
3210/**
3211 * @brief Stops the TIM Encoder Interface.
3212 * @param htim TIM Encoder Interface handle
3213 * @param Channel TIM Channels to be disabled
3214 * This parameter can be one of the following values:
3215 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3216 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3217 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3218 * @retval HAL status
3219 */
3220HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3221{
3222 /* Check the parameters */
3223 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3224
3225 /* Disable the Input Capture channels 1 and 2
3226 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3227 switch (Channel)
3228 {
3229 case TIM_CHANNEL_1:
3230 {
3231 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3232 break;
3233 }
3234
3235 case TIM_CHANNEL_2:
3236 {
3237 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3238 break;
3239 }
3240
3241 default :
3242 {
3243 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3244 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3245 break;
3246 }
3247 }
3248
3249 /* Disable the Peripheral */
3250 __HAL_TIM_DISABLE(htim);
3251
3252 /* Set the TIM channel(s) state */
3253 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3254 {
3255 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3256 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3257 }
3258 else
3259 {
3260 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3261 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3262 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3263 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3264 }
3265
3266 /* Return function status */
3267 return HAL_OK;
3268}
3269
3270/**
3271 * @brief Starts the TIM Encoder Interface in interrupt mode.
3272 * @param htim TIM Encoder Interface handle
3273 * @param Channel TIM Channels to be enabled
3274 * This parameter can be one of the following values:
3275 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3276 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3277 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3278 * @retval HAL status
3279 */
3280HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3281{
3282 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3283 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3284 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3285 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3286
3287 /* Check the parameters */
3288 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3289
3290 /* Set the TIM channel(s) state */
3291 if (Channel == TIM_CHANNEL_1)
3292 {
3293 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3294 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3295 {
3296 return HAL_ERROR;
3297 }
3298 else
3299 {
3300 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3301 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3302 }
3303 }
3304 else if (Channel == TIM_CHANNEL_2)
3305 {
3306 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3307 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3308 {
3309 return HAL_ERROR;
3310 }
3311 else
3312 {
3313 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3314 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3315 }
3316 }
3317 else
3318 {
3319 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3320 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3321 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3322 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3323 {
3324 return HAL_ERROR;
3325 }
3326 else
3327 {
3328 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3329 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3330 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3331 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3332 }
3333 }
3334
3335 /* Enable the encoder interface channels */
3336 /* Enable the capture compare Interrupts 1 and/or 2 */
3337 switch (Channel)
3338 {
3339 case TIM_CHANNEL_1:
3340 {
3341 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3342 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3343 break;
3344 }
3345
3346 case TIM_CHANNEL_2:
3347 {
3348 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3349 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3350 break;
3351 }
3352
3353 default :
3354 {
3355 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3356 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3357 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3358 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3359 break;
3360 }
3361 }
3362
3363 /* Enable the Peripheral */
3364 __HAL_TIM_ENABLE(htim);
3365
3366 /* Return function status */
3367 return HAL_OK;
3368}
3369
3370/**
3371 * @brief Stops the TIM Encoder Interface in interrupt mode.
3372 * @param htim TIM Encoder Interface handle
3373 * @param Channel TIM Channels to be disabled
3374 * This parameter can be one of the following values:
3375 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3376 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3377 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3378 * @retval HAL status
3379 */
3380HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3381{
3382 /* Check the parameters */
3383 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3384
3385 /* Disable the Input Capture channels 1 and 2
3386 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3387 if (Channel == TIM_CHANNEL_1)
3388 {
3389 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3390
3391 /* Disable the capture compare Interrupts 1 */
3392 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3393 }
3394 else if (Channel == TIM_CHANNEL_2)
3395 {
3396 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3397
3398 /* Disable the capture compare Interrupts 2 */
3399 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3400 }
3401 else
3402 {
3403 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3404 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3405
3406 /* Disable the capture compare Interrupts 1 and 2 */
3407 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3408 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3409 }
3410
3411 /* Disable the Peripheral */
3412 __HAL_TIM_DISABLE(htim);
3413
3414 /* Set the TIM channel(s) state */
3415 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3416 {
3417 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3418 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3419 }
3420 else
3421 {
3422 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3423 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3424 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3425 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3426 }
3427
3428 /* Return function status */
3429 return HAL_OK;
3430}
3431
3432/**
3433 * @brief Starts the TIM Encoder Interface in DMA mode.
3434 * @param htim TIM Encoder Interface handle
3435 * @param Channel TIM Channels to be enabled
3436 * This parameter can be one of the following values:
3437 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3438 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3439 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3440 * @param pData1 The destination Buffer address for IC1.
3441 * @param pData2 The destination Buffer address for IC2.
3442 * @param Length The length of data to be transferred from TIM peripheral to memory.
3443 * @retval HAL status
3444 */
3445HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3446 uint32_t *pData2, uint16_t Length)
3447{
3448 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3449 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3450 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3451 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3452
3453 /* Check the parameters */
3454 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3455
3456 /* Set the TIM channel(s) state */
3457 if (Channel == TIM_CHANNEL_1)
3458 {
3459 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3460 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3461 {
3462 return HAL_BUSY;
3463 }
3464 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3465 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3466 {
3467 if ((pData1 == NULL) && (Length > 0U))
3468 {
3469 return HAL_ERROR;
3470 }
3471 else
3472 {
3473 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3474 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3475 }
3476 }
3477 else
3478 {
3479 return HAL_ERROR;
3480 }
3481 }
3482 else if (Channel == TIM_CHANNEL_2)
3483 {
3484 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3485 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3486 {
3487 return HAL_BUSY;
3488 }
3489 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3490 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3491 {
3492 if ((pData2 == NULL) && (Length > 0U))
3493 {
3494 return HAL_ERROR;
3495 }
3496 else
3497 {
3498 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3499 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3500 }
3501 }
3502 else
3503 {
3504 return HAL_ERROR;
3505 }
3506 }
3507 else
3508 {
3509 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3510 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3511 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3512 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3513 {
3514 return HAL_BUSY;
3515 }
3516 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3517 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3518 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3519 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3520 {
3521 if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
3522 {
3523 return HAL_ERROR;
3524 }
3525 else
3526 {
3527 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3528 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3529 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3530 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3531 }
3532 }
3533 else
3534 {
3535 return HAL_ERROR;
3536 }
3537 }
3538
3539 switch (Channel)
3540 {
3541 case TIM_CHANNEL_1:
3542 {
3543 /* Set the DMA capture callbacks */
3544 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3545 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3546
3547 /* Set the DMA error callback */
3548 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3549
3550 /* Enable the DMA stream */
3551 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3552 {
3553 /* Return error status */
3554 return HAL_ERROR;
3555 }
3556 /* Enable the TIM Input Capture DMA request */
3557 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3558
3559 /* Enable the Peripheral */
3560 __HAL_TIM_ENABLE(htim);
3561
3562 /* Enable the Capture compare channel */
3563 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3564 break;
3565 }
3566
3567 case TIM_CHANNEL_2:
3568 {
3569 /* Set the DMA capture callbacks */
3570 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3571 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3572
3573 /* Set the DMA error callback */
3574 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3575 /* Enable the DMA stream */
3576 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3577 {
3578 /* Return error status */
3579 return HAL_ERROR;
3580 }
3581 /* Enable the TIM Input Capture DMA request */
3582 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3583
3584 /* Enable the Peripheral */
3585 __HAL_TIM_ENABLE(htim);
3586
3587 /* Enable the Capture compare channel */
3588 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3589 break;
3590 }
3591
3592 case TIM_CHANNEL_ALL:
3593 {
3594 /* Set the DMA capture callbacks */
3595 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3596 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3597
3598 /* Set the DMA error callback */
3599 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3600
3601 /* Enable the DMA stream */
3602 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3603 {
3604 /* Return error status */
3605 return HAL_ERROR;
3606 }
3607
3608 /* Set the DMA capture callbacks */
3609 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3610 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3611
3612 /* Set the DMA error callback */
3613 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3614
3615 /* Enable the DMA stream */
3616 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3617 {
3618 /* Return error status */
3619 return HAL_ERROR;
3620 }
3621 /* Enable the Peripheral */
3622 __HAL_TIM_ENABLE(htim);
3623
3624 /* Enable the Capture compare channel */
3625 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3626 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3627
3628 /* Enable the TIM Input Capture DMA request */
3629 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3630 /* Enable the TIM Input Capture DMA request */
3631 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3632 break;
3633 }
3634
3635 default:
3636 break;
3637 }
3638
3639 /* Return function status */
3640 return HAL_OK;
3641}
3642
3643/**
3644 * @brief Stops the TIM Encoder Interface in DMA mode.
3645 * @param htim TIM Encoder Interface handle
3646 * @param Channel TIM Channels to be enabled
3647 * This parameter can be one of the following values:
3648 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3649 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3650 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3651 * @retval HAL status
3652 */
3653HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3654{
3655 /* Check the parameters */
3656 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3657
3658 /* Disable the Input Capture channels 1 and 2
3659 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3660 if (Channel == TIM_CHANNEL_1)
3661 {
3662 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3663
3664 /* Disable the capture compare DMA Request 1 */
3665 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3666 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3667 }
3668 else if (Channel == TIM_CHANNEL_2)
3669 {
3670 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3671
3672 /* Disable the capture compare DMA Request 2 */
3673 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3674 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3675 }
3676 else
3677 {
3678 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3679 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3680
3681 /* Disable the capture compare DMA Request 1 and 2 */
3682 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3683 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3684 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3685 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3686 }
3687
3688 /* Disable the Peripheral */
3689 __HAL_TIM_DISABLE(htim);
3690
3691 /* Set the TIM channel(s) state */
3692 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3693 {
3694 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3695 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3696 }
3697 else
3698 {
3699 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3700 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3701 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3702 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3703 }
3704
3705 /* Return function status */
3706 return HAL_OK;
3707}
3708
3709/**
3710 * @}
3711 */
3712/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3713 * @brief TIM IRQ handler management
3714 *
3715@verbatim
3716 ==============================================================================
3717 ##### IRQ handler management #####
3718 ==============================================================================
3719 [..]
3720 This section provides Timer IRQ handler function.
3721
3722@endverbatim
3723 * @{
3724 */
3725/**
3726 * @brief This function handles TIM interrupts requests.
3727 * @param htim TIM handle
3728 * @retval None
3729 */
3730void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3731{
3732 /* Capture compare 1 event */
3733 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3734 {
3735 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3736 {
3737 {
3738 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3739 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3740
3741 /* Input capture event */
3742 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3743 {
3744#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3745 htim->IC_CaptureCallback(htim);
3746#else
3747 HAL_TIM_IC_CaptureCallback(htim);
3748#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3749 }
3750 /* Output compare event */
3751 else
3752 {
3753#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3754 htim->OC_DelayElapsedCallback(htim);
3755 htim->PWM_PulseFinishedCallback(htim);
3756#else
3757 HAL_TIM_OC_DelayElapsedCallback(htim);
3758 HAL_TIM_PWM_PulseFinishedCallback(htim);
3759#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3760 }
3761 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3762 }
3763 }
3764 }
3765 /* Capture compare 2 event */
3766 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3767 {
3768 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3769 {
3770 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3771 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3772 /* Input capture event */
3773 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3774 {
3775#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3776 htim->IC_CaptureCallback(htim);
3777#else
3778 HAL_TIM_IC_CaptureCallback(htim);
3779#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3780 }
3781 /* Output compare event */
3782 else
3783 {
3784#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3785 htim->OC_DelayElapsedCallback(htim);
3786 htim->PWM_PulseFinishedCallback(htim);
3787#else
3788 HAL_TIM_OC_DelayElapsedCallback(htim);
3789 HAL_TIM_PWM_PulseFinishedCallback(htim);
3790#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3791 }
3792 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3793 }
3794 }
3795 /* Capture compare 3 event */
3796 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3797 {
3798 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3799 {
3800 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3801 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3802 /* Input capture event */
3803 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3804 {
3805#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3806 htim->IC_CaptureCallback(htim);
3807#else
3808 HAL_TIM_IC_CaptureCallback(htim);
3809#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3810 }
3811 /* Output compare event */
3812 else
3813 {
3814#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3815 htim->OC_DelayElapsedCallback(htim);
3816 htim->PWM_PulseFinishedCallback(htim);
3817#else
3818 HAL_TIM_OC_DelayElapsedCallback(htim);
3819 HAL_TIM_PWM_PulseFinishedCallback(htim);
3820#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3821 }
3822 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3823 }
3824 }
3825 /* Capture compare 4 event */
3826 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3827 {
3828 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3829 {
3830 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3831 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3832 /* Input capture event */
3833 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3834 {
3835#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3836 htim->IC_CaptureCallback(htim);
3837#else
3838 HAL_TIM_IC_CaptureCallback(htim);
3839#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3840 }
3841 /* Output compare event */
3842 else
3843 {
3844#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3845 htim->OC_DelayElapsedCallback(htim);
3846 htim->PWM_PulseFinishedCallback(htim);
3847#else
3848 HAL_TIM_OC_DelayElapsedCallback(htim);
3849 HAL_TIM_PWM_PulseFinishedCallback(htim);
3850#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3851 }
3852 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3853 }
3854 }
3855 /* TIM Update event */
3856 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3857 {
3858 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3859 {
3860 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3861#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3862 htim->PeriodElapsedCallback(htim);
3863#else
3864 HAL_TIM_PeriodElapsedCallback(htim);
3865#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3866 }
3867 }
3868 /* TIM Break input event */
3869 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3870 {
3871 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3872 {
3873 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3874#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3875 htim->BreakCallback(htim);
3876#else
3877 HAL_TIMEx_BreakCallback(htim);
3878#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3879 }
3880 }
3881 /* TIM Trigger detection event */
3882 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3883 {
3884 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3885 {
3886 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3887#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3888 htim->TriggerCallback(htim);
3889#else
3890 HAL_TIM_TriggerCallback(htim);
3891#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3892 }
3893 }
3894 /* TIM commutation event */
3895 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
3896 {
3897 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
3898 {
3899 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
3900#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3901 htim->CommutationCallback(htim);
3902#else
3903 HAL_TIMEx_CommutCallback(htim);
3904#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3905 }
3906 }
3907}
3908
3909/**
3910 * @}
3911 */
3912
3913/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
3914 * @brief TIM Peripheral Control functions
3915 *
3916@verbatim
3917 ==============================================================================
3918 ##### Peripheral Control functions #####
3919 ==============================================================================
3920 [..]
3921 This section provides functions allowing to:
3922 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3923 (+) Configure External Clock source.
3924 (+) Configure Complementary channels, break features and dead time.
3925 (+) Configure Master and the Slave synchronization.
3926 (+) Configure the DMA Burst Mode.
3927
3928@endverbatim
3929 * @{
3930 */
3931
3932/**
3933 * @brief Initializes the TIM Output Compare Channels according to the specified
3934 * parameters in the TIM_OC_InitTypeDef.
3935 * @param htim TIM Output Compare handle
3936 * @param sConfig TIM Output Compare configuration structure
3937 * @param Channel TIM Channels to configure
3938 * This parameter can be one of the following values:
3939 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3940 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3941 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3942 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3943 * @retval HAL status
3944 */
3945HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
3946 TIM_OC_InitTypeDef *sConfig,
3947 uint32_t Channel)
3948{
3949 /* Check the parameters */
3950 assert_param(IS_TIM_CHANNELS(Channel));
3951 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
3952 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3953
3954 /* Process Locked */
3955 __HAL_LOCK(htim);
3956
3957 switch (Channel)
3958 {
3959 case TIM_CHANNEL_1:
3960 {
3961 /* Check the parameters */
3962 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3963
3964 /* Configure the TIM Channel 1 in Output Compare */
3965 TIM_OC1_SetConfig(htim->Instance, sConfig);
3966 break;
3967 }
3968
3969 case TIM_CHANNEL_2:
3970 {
3971 /* Check the parameters */
3972 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3973
3974 /* Configure the TIM Channel 2 in Output Compare */
3975 TIM_OC2_SetConfig(htim->Instance, sConfig);
3976 break;
3977 }
3978
3979 case TIM_CHANNEL_3:
3980 {
3981 /* Check the parameters */
3982 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3983
3984 /* Configure the TIM Channel 3 in Output Compare */
3985 TIM_OC3_SetConfig(htim->Instance, sConfig);
3986 break;
3987 }
3988
3989 case TIM_CHANNEL_4:
3990 {
3991 /* Check the parameters */
3992 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3993
3994 /* Configure the TIM Channel 4 in Output Compare */
3995 TIM_OC4_SetConfig(htim->Instance, sConfig);
3996 break;
3997 }
3998
3999 default:
4000 break;
4001 }
4002
4003 __HAL_UNLOCK(htim);
4004
4005 return HAL_OK;
4006}
4007
4008/**
4009 * @brief Initializes the TIM Input Capture Channels according to the specified
4010 * parameters in the TIM_IC_InitTypeDef.
4011 * @param htim TIM IC handle
4012 * @param sConfig TIM Input Capture configuration structure
4013 * @param Channel TIM Channel to configure
4014 * This parameter can be one of the following values:
4015 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4016 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4017 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4018 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4019 * @retval HAL status
4020 */
4021HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4022{
4023 /* Check the parameters */
4024 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4025 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4026 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4027 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4028 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4029
4030 /* Process Locked */
4031 __HAL_LOCK(htim);
4032
4033 if (Channel == TIM_CHANNEL_1)
4034 {
4035 /* TI1 Configuration */
4036 TIM_TI1_SetConfig(htim->Instance,
4037 sConfig->ICPolarity,
4038 sConfig->ICSelection,
4039 sConfig->ICFilter);
4040
4041 /* Reset the IC1PSC Bits */
4042 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4043
4044 /* Set the IC1PSC value */
4045 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4046 }
4047 else if (Channel == TIM_CHANNEL_2)
4048 {
4049 /* TI2 Configuration */
4050 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4051
4052 TIM_TI2_SetConfig(htim->Instance,
4053 sConfig->ICPolarity,
4054 sConfig->ICSelection,
4055 sConfig->ICFilter);
4056
4057 /* Reset the IC2PSC Bits */
4058 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4059
4060 /* Set the IC2PSC value */
4061 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4062 }
4063 else if (Channel == TIM_CHANNEL_3)
4064 {
4065 /* TI3 Configuration */
4066 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4067
4068 TIM_TI3_SetConfig(htim->Instance,
4069 sConfig->ICPolarity,
4070 sConfig->ICSelection,
4071 sConfig->ICFilter);
4072
4073 /* Reset the IC3PSC Bits */
4074 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4075
4076 /* Set the IC3PSC value */
4077 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4078 }
4079 else
4080 {
4081 /* TI4 Configuration */
4082 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4083
4084 TIM_TI4_SetConfig(htim->Instance,
4085 sConfig->ICPolarity,
4086 sConfig->ICSelection,
4087 sConfig->ICFilter);
4088
4089 /* Reset the IC4PSC Bits */
4090 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4091
4092 /* Set the IC4PSC value */
4093 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4094 }
4095
4096 __HAL_UNLOCK(htim);
4097
4098 return HAL_OK;
4099}
4100
4101/**
4102 * @brief Initializes the TIM PWM channels according to the specified
4103 * parameters in the TIM_OC_InitTypeDef.
4104 * @param htim TIM PWM handle
4105 * @param sConfig TIM PWM configuration structure
4106 * @param Channel TIM Channels to be configured
4107 * This parameter can be one of the following values:
4108 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4109 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4110 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4111 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4112 * @retval HAL status
4113 */
4114HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4115 TIM_OC_InitTypeDef *sConfig,
4116 uint32_t Channel)
4117{
4118 /* Check the parameters */
4119 assert_param(IS_TIM_CHANNELS(Channel));
4120 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4121 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4122 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4123
4124 /* Process Locked */
4125 __HAL_LOCK(htim);
4126
4127 switch (Channel)
4128 {
4129 case TIM_CHANNEL_1:
4130 {
4131 /* Check the parameters */
4132 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4133
4134 /* Configure the Channel 1 in PWM mode */
4135 TIM_OC1_SetConfig(htim->Instance, sConfig);
4136
4137 /* Set the Preload enable bit for channel1 */
4138 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4139
4140 /* Configure the Output Fast mode */
4141 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4142 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4143 break;
4144 }
4145
4146 case TIM_CHANNEL_2:
4147 {
4148 /* Check the parameters */
4149 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4150
4151 /* Configure the Channel 2 in PWM mode */
4152 TIM_OC2_SetConfig(htim->Instance, sConfig);
4153
4154 /* Set the Preload enable bit for channel2 */
4155 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4156
4157 /* Configure the Output Fast mode */
4158 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4159 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4160 break;
4161 }
4162
4163 case TIM_CHANNEL_3:
4164 {
4165 /* Check the parameters */
4166 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4167
4168 /* Configure the Channel 3 in PWM mode */
4169 TIM_OC3_SetConfig(htim->Instance, sConfig);
4170
4171 /* Set the Preload enable bit for channel3 */
4172 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4173
4174 /* Configure the Output Fast mode */
4175 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4176 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4177 break;
4178 }
4179
4180 case TIM_CHANNEL_4:
4181 {
4182 /* Check the parameters */
4183 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4184
4185 /* Configure the Channel 4 in PWM mode */
4186 TIM_OC4_SetConfig(htim->Instance, sConfig);
4187
4188 /* Set the Preload enable bit for channel4 */
4189 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4190
4191 /* Configure the Output Fast mode */
4192 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4193 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4194 break;
4195 }
4196
4197 default:
4198 break;
4199 }
4200
4201 __HAL_UNLOCK(htim);
4202
4203 return HAL_OK;
4204}
4205
4206/**
4207 * @brief Initializes the TIM One Pulse Channels according to the specified
4208 * parameters in the TIM_OnePulse_InitTypeDef.
4209 * @param htim TIM One Pulse handle
4210 * @param sConfig TIM One Pulse configuration structure
4211 * @param OutputChannel TIM output channel to configure
4212 * This parameter can be one of the following values:
4213 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4214 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4215 * @param InputChannel TIM input Channel to configure
4216 * This parameter can be one of the following values:
4217 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4218 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4219 * @note To output a waveform with a minimum delay user can enable the fast
4220 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4221 * output is forced in response to the edge detection on TIx input,
4222 * without taking in account the comparison.
4223 * @retval HAL status
4224 */
4225HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4226 uint32_t OutputChannel, uint32_t InputChannel)
4227{
4228 TIM_OC_InitTypeDef temp1;
4229
4230 /* Check the parameters */
4231 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4232 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4233
4234 if (OutputChannel != InputChannel)
4235 {
4236 /* Process Locked */
4237 __HAL_LOCK(htim);
4238
4239 htim->State = HAL_TIM_STATE_BUSY;
4240
4241 /* Extract the Output compare configuration from sConfig structure */
4242 temp1.OCMode = sConfig->OCMode;
4243 temp1.Pulse = sConfig->Pulse;
4244 temp1.OCPolarity = sConfig->OCPolarity;
4245 temp1.OCNPolarity = sConfig->OCNPolarity;
4246 temp1.OCIdleState = sConfig->OCIdleState;
4247 temp1.OCNIdleState = sConfig->OCNIdleState;
4248
4249 switch (OutputChannel)
4250 {
4251 case TIM_CHANNEL_1:
4252 {
4253 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4254
4255 TIM_OC1_SetConfig(htim->Instance, &temp1);
4256 break;
4257 }
4258 case TIM_CHANNEL_2:
4259 {
4260 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4261
4262 TIM_OC2_SetConfig(htim->Instance, &temp1);
4263 break;
4264 }
4265 default:
4266 break;
4267 }
4268
4269 switch (InputChannel)
4270 {
4271 case TIM_CHANNEL_1:
4272 {
4273 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4274
4275 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4276 sConfig->ICSelection, sConfig->ICFilter);
4277
4278 /* Reset the IC1PSC Bits */
4279 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4280
4281 /* Select the Trigger source */
4282 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4283 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4284
4285 /* Select the Slave Mode */
4286 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4287 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4288 break;
4289 }
4290 case TIM_CHANNEL_2:
4291 {
4292 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4293
4294 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4295 sConfig->ICSelection, sConfig->ICFilter);
4296
4297 /* Reset the IC2PSC Bits */
4298 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4299
4300 /* Select the Trigger source */
4301 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4302 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4303
4304 /* Select the Slave Mode */
4305 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4306 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4307 break;
4308 }
4309
4310 default:
4311 break;
4312 }
4313
4314 htim->State = HAL_TIM_STATE_READY;
4315
4316 __HAL_UNLOCK(htim);
4317
4318 return HAL_OK;
4319 }
4320 else
4321 {
4322 return HAL_ERROR;
4323 }
4324}
4325
4326/**
4327 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4328 * @param htim TIM handle
4329 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4330 * This parameter can be one of the following values:
4331 * @arg TIM_DMABASE_CR1
4332 * @arg TIM_DMABASE_CR2
4333 * @arg TIM_DMABASE_SMCR
4334 * @arg TIM_DMABASE_DIER
4335 * @arg TIM_DMABASE_SR
4336 * @arg TIM_DMABASE_EGR
4337 * @arg TIM_DMABASE_CCMR1
4338 * @arg TIM_DMABASE_CCMR2
4339 * @arg TIM_DMABASE_CCER
4340 * @arg TIM_DMABASE_CNT
4341 * @arg TIM_DMABASE_PSC
4342 * @arg TIM_DMABASE_ARR
4343 * @arg TIM_DMABASE_RCR
4344 * @arg TIM_DMABASE_CCR1
4345 * @arg TIM_DMABASE_CCR2
4346 * @arg TIM_DMABASE_CCR3
4347 * @arg TIM_DMABASE_CCR4
4348 * @arg TIM_DMABASE_BDTR
4349 * @param BurstRequestSrc TIM DMA Request sources
4350 * This parameter can be one of the following values:
4351 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4352 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4353 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4354 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4355 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4356 * @arg TIM_DMA_COM: TIM Commutation DMA source
4357 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4358 * @param BurstBuffer The Buffer address.
4359 * @param BurstLength DMA Burst length. This parameter can be one value
4360 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4361 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4362 * @retval HAL status
4363 */
4364HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4365 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4366{
4367 return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4368 ((BurstLength) >> 8U) + 1U);
4369}
4370
4371/**
4372 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4373 * @param htim TIM handle
4374 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4375 * This parameter can be one of the following values:
4376 * @arg TIM_DMABASE_CR1
4377 * @arg TIM_DMABASE_CR2
4378 * @arg TIM_DMABASE_SMCR
4379 * @arg TIM_DMABASE_DIER
4380 * @arg TIM_DMABASE_SR
4381 * @arg TIM_DMABASE_EGR
4382 * @arg TIM_DMABASE_CCMR1
4383 * @arg TIM_DMABASE_CCMR2
4384 * @arg TIM_DMABASE_CCER
4385 * @arg TIM_DMABASE_CNT
4386 * @arg TIM_DMABASE_PSC
4387 * @arg TIM_DMABASE_ARR
4388 * @arg TIM_DMABASE_RCR
4389 * @arg TIM_DMABASE_CCR1
4390 * @arg TIM_DMABASE_CCR2
4391 * @arg TIM_DMABASE_CCR3
4392 * @arg TIM_DMABASE_CCR4
4393 * @arg TIM_DMABASE_BDTR
4394 * @param BurstRequestSrc TIM DMA Request sources
4395 * This parameter can be one of the following values:
4396 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4397 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4398 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4399 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4400 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4401 * @arg TIM_DMA_COM: TIM Commutation DMA source
4402 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4403 * @param BurstBuffer The Buffer address.
4404 * @param BurstLength DMA Burst length. This parameter can be one value
4405 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4406 * @param DataLength Data length. This parameter can be one value
4407 * between 1 and 0xFFFF.
4408 * @retval HAL status
4409 */
4410HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4411 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4412 uint32_t BurstLength, uint32_t DataLength)
4413{
4414 /* Check the parameters */
4415 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4416 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4417 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4418 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4419 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4420
4421 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4422 {
4423 return HAL_BUSY;
4424 }
4425 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4426 {
4427 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4428 {
4429 return HAL_ERROR;
4430 }
4431 else
4432 {
4433 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4434 }
4435 }
4436 else
4437 {
4438 /* nothing to do */
4439 }
4440 switch (BurstRequestSrc)
4441 {
4442 case TIM_DMA_UPDATE:
4443 {
4444 /* Set the DMA Period elapsed callbacks */
4445 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4446 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4447
4448 /* Set the DMA error callback */
4449 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4450
4451 /* Enable the DMA stream */
4452 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4453 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4454 {
4455 /* Return error status */
4456 return HAL_ERROR;
4457 }
4458 break;
4459 }
4460 case TIM_DMA_CC1:
4461 {
4462 /* Set the DMA compare callbacks */
4463 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4464 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4465
4466 /* Set the DMA error callback */
4467 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4468
4469 /* Enable the DMA stream */
4470 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4471 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4472 {
4473 /* Return error status */
4474 return HAL_ERROR;
4475 }
4476 break;
4477 }
4478 case TIM_DMA_CC2:
4479 {
4480 /* Set the DMA compare callbacks */
4481 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4482 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4483
4484 /* Set the DMA error callback */
4485 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4486
4487 /* Enable the DMA stream */
4488 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4489 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4490 {
4491 /* Return error status */
4492 return HAL_ERROR;
4493 }
4494 break;
4495 }
4496 case TIM_DMA_CC3:
4497 {
4498 /* Set the DMA compare callbacks */
4499 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4500 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4501
4502 /* Set the DMA error callback */
4503 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4504
4505 /* Enable the DMA stream */
4506 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4507 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4508 {
4509 /* Return error status */
4510 return HAL_ERROR;
4511 }
4512 break;
4513 }
4514 case TIM_DMA_CC4:
4515 {
4516 /* Set the DMA compare callbacks */
4517 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4518 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4519
4520 /* Set the DMA error callback */
4521 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4522
4523 /* Enable the DMA stream */
4524 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4525 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4526 {
4527 /* Return error status */
4528 return HAL_ERROR;
4529 }
4530 break;
4531 }
4532 case TIM_DMA_COM:
4533 {
4534 /* Set the DMA commutation callbacks */
4535 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4536 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4537
4538 /* Set the DMA error callback */
4539 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4540
4541 /* Enable the DMA stream */
4542 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4543 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4544 {
4545 /* Return error status */
4546 return HAL_ERROR;
4547 }
4548 break;
4549 }
4550 case TIM_DMA_TRIGGER:
4551 {
4552 /* Set the DMA trigger callbacks */
4553 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4554 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4555
4556 /* Set the DMA error callback */
4557 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4558
4559 /* Enable the DMA stream */
4560 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4561 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4562 {
4563 /* Return error status */
4564 return HAL_ERROR;
4565 }
4566 break;
4567 }
4568 default:
4569 break;
4570 }
4571
4572 /* Configure the DMA Burst Mode */
4573 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4574 /* Enable the TIM DMA Request */
4575 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4576
4577 /* Return function status */
4578 return HAL_OK;
4579}
4580
4581/**
4582 * @brief Stops the TIM DMA Burst mode
4583 * @param htim TIM handle
4584 * @param BurstRequestSrc TIM DMA Request sources to disable
4585 * @retval HAL status
4586 */
4587HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4588{
4589 /* Check the parameters */
4590 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4591
4592 /* Abort the DMA transfer (at least disable the DMA stream) */
4593 switch (BurstRequestSrc)
4594 {
4595 case TIM_DMA_UPDATE:
4596 {
4597 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4598 break;
4599 }
4600 case TIM_DMA_CC1:
4601 {
4602 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4603 break;
4604 }
4605 case TIM_DMA_CC2:
4606 {
4607 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4608 break;
4609 }
4610 case TIM_DMA_CC3:
4611 {
4612 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4613 break;
4614 }
4615 case TIM_DMA_CC4:
4616 {
4617 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4618 break;
4619 }
4620 case TIM_DMA_COM:
4621 {
4622 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4623 break;
4624 }
4625 case TIM_DMA_TRIGGER:
4626 {
4627 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4628 break;
4629 }
4630 default:
4631 break;
4632 }
4633
4634 /* Disable the TIM Update DMA request */
4635 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4636
4637 /* Change the DMA burst operation state */
4638 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4639
4640 /* Return function status */
4641 return HAL_OK;
4642}
4643
4644/**
4645 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4646 * @param htim TIM handle
4647 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4648 * This parameter can be one of the following values:
4649 * @arg TIM_DMABASE_CR1
4650 * @arg TIM_DMABASE_CR2
4651 * @arg TIM_DMABASE_SMCR
4652 * @arg TIM_DMABASE_DIER
4653 * @arg TIM_DMABASE_SR
4654 * @arg TIM_DMABASE_EGR
4655 * @arg TIM_DMABASE_CCMR1
4656 * @arg TIM_DMABASE_CCMR2
4657 * @arg TIM_DMABASE_CCER
4658 * @arg TIM_DMABASE_CNT
4659 * @arg TIM_DMABASE_PSC
4660 * @arg TIM_DMABASE_ARR
4661 * @arg TIM_DMABASE_RCR
4662 * @arg TIM_DMABASE_CCR1
4663 * @arg TIM_DMABASE_CCR2
4664 * @arg TIM_DMABASE_CCR3
4665 * @arg TIM_DMABASE_CCR4
4666 * @arg TIM_DMABASE_BDTR
4667 * @param BurstRequestSrc TIM DMA Request sources
4668 * This parameter can be one of the following values:
4669 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4670 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4671 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4672 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4673 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4674 * @arg TIM_DMA_COM: TIM Commutation DMA source
4675 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4676 * @param BurstBuffer The Buffer address.
4677 * @param BurstLength DMA Burst length. This parameter can be one value
4678 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4679 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4680 * @retval HAL status
4681 */
4682HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4683 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4684{
4685 return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4686 ((BurstLength) >> 8U) + 1U);
4687}
4688
4689/**
4690 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4691 * @param htim TIM handle
4692 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4693 * This parameter can be one of the following values:
4694 * @arg TIM_DMABASE_CR1
4695 * @arg TIM_DMABASE_CR2
4696 * @arg TIM_DMABASE_SMCR
4697 * @arg TIM_DMABASE_DIER
4698 * @arg TIM_DMABASE_SR
4699 * @arg TIM_DMABASE_EGR
4700 * @arg TIM_DMABASE_CCMR1
4701 * @arg TIM_DMABASE_CCMR2
4702 * @arg TIM_DMABASE_CCER
4703 * @arg TIM_DMABASE_CNT
4704 * @arg TIM_DMABASE_PSC
4705 * @arg TIM_DMABASE_ARR
4706 * @arg TIM_DMABASE_RCR
4707 * @arg TIM_DMABASE_CCR1
4708 * @arg TIM_DMABASE_CCR2
4709 * @arg TIM_DMABASE_CCR3
4710 * @arg TIM_DMABASE_CCR4
4711 * @arg TIM_DMABASE_BDTR
4712 * @param BurstRequestSrc TIM DMA Request sources
4713 * This parameter can be one of the following values:
4714 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4715 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4716 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4717 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4718 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4719 * @arg TIM_DMA_COM: TIM Commutation DMA source
4720 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4721 * @param BurstBuffer The Buffer address.
4722 * @param BurstLength DMA Burst length. This parameter can be one value
4723 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4724 * @param DataLength Data length. This parameter can be one value
4725 * between 1 and 0xFFFF.
4726 * @retval HAL status
4727 */
4728HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4729 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4730 uint32_t BurstLength, uint32_t DataLength)
4731{
4732 /* Check the parameters */
4733 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4734 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4735 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4736 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4737 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4738
4739 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4740 {
4741 return HAL_BUSY;
4742 }
4743 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4744 {
4745 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4746 {
4747 return HAL_ERROR;
4748 }
4749 else
4750 {
4751 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4752 }
4753 }
4754 else
4755 {
4756 /* nothing to do */
4757 }
4758 switch (BurstRequestSrc)
4759 {
4760 case TIM_DMA_UPDATE:
4761 {
4762 /* Set the DMA Period elapsed callbacks */
4763 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4764 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4765
4766 /* Set the DMA error callback */
4767 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4768
4769 /* Enable the DMA stream */
4770 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4771 DataLength) != HAL_OK)
4772 {
4773 /* Return error status */
4774 return HAL_ERROR;
4775 }
4776 break;
4777 }
4778 case TIM_DMA_CC1:
4779 {
4780 /* Set the DMA capture callbacks */
4781 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4782 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4783
4784 /* Set the DMA error callback */
4785 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4786
4787 /* Enable the DMA stream */
4788 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4789 DataLength) != HAL_OK)
4790 {
4791 /* Return error status */
4792 return HAL_ERROR;
4793 }
4794 break;
4795 }
4796 case TIM_DMA_CC2:
4797 {
4798 /* Set the DMA capture callbacks */
4799 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4800 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4801
4802 /* Set the DMA error callback */
4803 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4804
4805 /* Enable the DMA stream */
4806 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4807 DataLength) != HAL_OK)
4808 {
4809 /* Return error status */
4810 return HAL_ERROR;
4811 }
4812 break;
4813 }
4814 case TIM_DMA_CC3:
4815 {
4816 /* Set the DMA capture callbacks */
4817 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4818 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4819
4820 /* Set the DMA error callback */
4821 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4822
4823 /* Enable the DMA stream */
4824 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4825 DataLength) != HAL_OK)
4826 {
4827 /* Return error status */
4828 return HAL_ERROR;
4829 }
4830 break;
4831 }
4832 case TIM_DMA_CC4:
4833 {
4834 /* Set the DMA capture callbacks */
4835 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4836 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4837
4838 /* Set the DMA error callback */
4839 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4840
4841 /* Enable the DMA stream */
4842 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4843 DataLength) != HAL_OK)
4844 {
4845 /* Return error status */
4846 return HAL_ERROR;
4847 }
4848 break;
4849 }
4850 case TIM_DMA_COM:
4851 {
4852 /* Set the DMA commutation callbacks */
4853 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4854 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4855
4856 /* Set the DMA error callback */
4857 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4858
4859 /* Enable the DMA stream */
4860 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4861 DataLength) != HAL_OK)
4862 {
4863 /* Return error status */
4864 return HAL_ERROR;
4865 }
4866 break;
4867 }
4868 case TIM_DMA_TRIGGER:
4869 {
4870 /* Set the DMA trigger callbacks */
4871 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4872 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4873
4874 /* Set the DMA error callback */
4875 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4876
4877 /* Enable the DMA stream */
4878 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4879 DataLength) != HAL_OK)
4880 {
4881 /* Return error status */
4882 return HAL_ERROR;
4883 }
4884 break;
4885 }
4886 default:
4887 break;
4888 }
4889
4890 /* Configure the DMA Burst Mode */
4891 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4892
4893 /* Enable the TIM DMA Request */
4894 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4895
4896 /* Return function status */
4897 return HAL_OK;
4898}
4899
4900/**
4901 * @brief Stop the DMA burst reading
4902 * @param htim TIM handle
4903 * @param BurstRequestSrc TIM DMA Request sources to disable.
4904 * @retval HAL status
4905 */
4906HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4907{
4908 /* Check the parameters */
4909 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4910
4911 /* Abort the DMA transfer (at least disable the DMA stream) */
4912 switch (BurstRequestSrc)
4913 {
4914 case TIM_DMA_UPDATE:
4915 {
4916 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4917 break;
4918 }
4919 case TIM_DMA_CC1:
4920 {
4921 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4922 break;
4923 }
4924 case TIM_DMA_CC2:
4925 {
4926 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4927 break;
4928 }
4929 case TIM_DMA_CC3:
4930 {
4931 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4932 break;
4933 }
4934 case TIM_DMA_CC4:
4935 {
4936 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4937 break;
4938 }
4939 case TIM_DMA_COM:
4940 {
4941 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4942 break;
4943 }
4944 case TIM_DMA_TRIGGER:
4945 {
4946 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4947 break;
4948 }
4949 default:
4950 break;
4951 }
4952
4953 /* Disable the TIM Update DMA request */
4954 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4955
4956 /* Change the DMA burst operation state */
4957 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4958
4959 /* Return function status */
4960 return HAL_OK;
4961}
4962
4963/**
4964 * @brief Generate a software event
4965 * @param htim TIM handle
4966 * @param EventSource specifies the event source.
4967 * This parameter can be one of the following values:
4968 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
4969 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
4970 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
4971 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
4972 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
4973 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
4974 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
4975 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
4976 * @note Basic timers can only generate an update event.
4977 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
4978 * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
4979 * supporting a break input.
4980 * @retval HAL status
4981 */
4982
4983HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
4984{
4985 /* Check the parameters */
4986 assert_param(IS_TIM_INSTANCE(htim->Instance));
4987 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
4988
4989 /* Process Locked */
4990 __HAL_LOCK(htim);
4991
4992 /* Change the TIM state */
4993 htim->State = HAL_TIM_STATE_BUSY;
4994
4995 /* Set the event sources */
4996 htim->Instance->EGR = EventSource;
4997
4998 /* Change the TIM state */
4999 htim->State = HAL_TIM_STATE_READY;
5000
5001 __HAL_UNLOCK(htim);
5002
5003 /* Return function status */
5004 return HAL_OK;
5005}
5006
5007/**
5008 * @brief Configures the OCRef clear feature
5009 * @param htim TIM handle
5010 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5011 * contains the OCREF clear feature and parameters for the TIM peripheral.
5012 * @param Channel specifies the TIM Channel
5013 * This parameter can be one of the following values:
5014 * @arg TIM_CHANNEL_1: TIM Channel 1
5015 * @arg TIM_CHANNEL_2: TIM Channel 2
5016 * @arg TIM_CHANNEL_3: TIM Channel 3
5017 * @arg TIM_CHANNEL_4: TIM Channel 4
5018 * @retval HAL status
5019 */
5020HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5021 TIM_ClearInputConfigTypeDef *sClearInputConfig,
5022 uint32_t Channel)
5023{
5024 /* Check the parameters */
5025 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5026 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5027
5028 /* Process Locked */
5029 __HAL_LOCK(htim);
5030
5031 htim->State = HAL_TIM_STATE_BUSY;
5032
5033 switch (sClearInputConfig->ClearInputSource)
5034 {
5035 case TIM_CLEARINPUTSOURCE_NONE:
5036 {
5037 /* Clear the OCREF clear selection bit and the the ETR Bits */
5038 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5039 break;
5040 }
5041
5042 case TIM_CLEARINPUTSOURCE_ETR:
5043 {
5044 /* Check the parameters */
5045 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5046 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5047 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5048
5049 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5050 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5051 {
5052 htim->State = HAL_TIM_STATE_READY;
5053 __HAL_UNLOCK(htim);
5054 return HAL_ERROR;
5055 }
5056
5057 TIM_ETR_SetConfig(htim->Instance,
5058 sClearInputConfig->ClearInputPrescaler,
5059 sClearInputConfig->ClearInputPolarity,
5060 sClearInputConfig->ClearInputFilter);
5061 break;
5062 }
5063
5064 default:
5065 break;
5066 }
5067
5068 switch (Channel)
5069 {
5070 case TIM_CHANNEL_1:
5071 {
5072 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5073 {
5074 /* Enable the OCREF clear feature for Channel 1 */
5075 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5076 }
5077 else
5078 {
5079 /* Disable the OCREF clear feature for Channel 1 */
5080 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5081 }
5082 break;
5083 }
5084 case TIM_CHANNEL_2:
5085 {
5086 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5087 {
5088 /* Enable the OCREF clear feature for Channel 2 */
5089 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5090 }
5091 else
5092 {
5093 /* Disable the OCREF clear feature for Channel 2 */
5094 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5095 }
5096 break;
5097 }
5098 case TIM_CHANNEL_3:
5099 {
5100 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5101 {
5102 /* Enable the OCREF clear feature for Channel 3 */
5103 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5104 }
5105 else
5106 {
5107 /* Disable the OCREF clear feature for Channel 3 */
5108 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5109 }
5110 break;
5111 }
5112 case TIM_CHANNEL_4:
5113 {
5114 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5115 {
5116 /* Enable the OCREF clear feature for Channel 4 */
5117 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5118 }
5119 else
5120 {
5121 /* Disable the OCREF clear feature for Channel 4 */
5122 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5123 }
5124 break;
5125 }
5126 default:
5127 break;
5128 }
5129
5130 htim->State = HAL_TIM_STATE_READY;
5131
5132 __HAL_UNLOCK(htim);
5133
5134 return HAL_OK;
5135}
5136
5137/**
5138 * @brief Configures the clock source to be used
5139 * @param htim TIM handle
5140 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5141 * contains the clock source information for the TIM peripheral.
5142 * @retval HAL status
5143 */
5144HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
5145{
5146 uint32_t tmpsmcr;
5147
5148 /* Process Locked */
5149 __HAL_LOCK(htim);
5150
5151 htim->State = HAL_TIM_STATE_BUSY;
5152
5153 /* Check the parameters */
5154 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5155
5156 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5157 tmpsmcr = htim->Instance->SMCR;
5158 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5159 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5160 htim->Instance->SMCR = tmpsmcr;
5161
5162 switch (sClockSourceConfig->ClockSource)
5163 {
5164 case TIM_CLOCKSOURCE_INTERNAL:
5165 {
5166 assert_param(IS_TIM_INSTANCE(htim->Instance));
5167 break;
5168 }
5169
5170 case TIM_CLOCKSOURCE_ETRMODE1:
5171 {
5172 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5173 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5174
5175 /* Check ETR input conditioning related parameters */
5176 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5177 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5178 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5179
5180 /* Configure the ETR Clock source */
5181 TIM_ETR_SetConfig(htim->Instance,
5182 sClockSourceConfig->ClockPrescaler,
5183 sClockSourceConfig->ClockPolarity,
5184 sClockSourceConfig->ClockFilter);
5185
5186 /* Select the External clock mode1 and the ETRF trigger */
5187 tmpsmcr = htim->Instance->SMCR;
5188 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5189 /* Write to TIMx SMCR */
5190 htim->Instance->SMCR = tmpsmcr;
5191 break;
5192 }
5193
5194 case TIM_CLOCKSOURCE_ETRMODE2:
5195 {
5196 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5197 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5198
5199 /* Check ETR input conditioning related parameters */
5200 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5201 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5202 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5203
5204 /* Configure the ETR Clock source */
5205 TIM_ETR_SetConfig(htim->Instance,
5206 sClockSourceConfig->ClockPrescaler,
5207 sClockSourceConfig->ClockPolarity,
5208 sClockSourceConfig->ClockFilter);
5209 /* Enable the External clock mode2 */
5210 htim->Instance->SMCR |= TIM_SMCR_ECE;
5211 break;
5212 }
5213
5214 case TIM_CLOCKSOURCE_TI1:
5215 {
5216 /* Check whether or not the timer instance supports external clock mode 1 */
5217 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5218
5219 /* Check TI1 input conditioning related parameters */
5220 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5221 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5222
5223 TIM_TI1_ConfigInputStage(htim->Instance,
5224 sClockSourceConfig->ClockPolarity,
5225 sClockSourceConfig->ClockFilter);
5226 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5227 break;
5228 }
5229
5230 case TIM_CLOCKSOURCE_TI2:
5231 {
5232 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5233 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5234
5235 /* Check TI2 input conditioning related parameters */
5236 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5237 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5238
5239 TIM_TI2_ConfigInputStage(htim->Instance,
5240 sClockSourceConfig->ClockPolarity,
5241 sClockSourceConfig->ClockFilter);
5242 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5243 break;
5244 }
5245
5246 case TIM_CLOCKSOURCE_TI1ED:
5247 {
5248 /* Check whether or not the timer instance supports external clock mode 1 */
5249 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5250
5251 /* Check TI1 input conditioning related parameters */
5252 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5253 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5254
5255 TIM_TI1_ConfigInputStage(htim->Instance,
5256 sClockSourceConfig->ClockPolarity,
5257 sClockSourceConfig->ClockFilter);
5258 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5259 break;
5260 }
5261
5262 case TIM_CLOCKSOURCE_ITR0:
5263 case TIM_CLOCKSOURCE_ITR1:
5264 case TIM_CLOCKSOURCE_ITR2:
5265 case TIM_CLOCKSOURCE_ITR3:
5266 {
5267 /* Check whether or not the timer instance supports internal trigger input */
5268 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5269
5270 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5271 break;
5272 }
5273
5274 default:
5275 break;
5276 }
5277 htim->State = HAL_TIM_STATE_READY;
5278
5279 __HAL_UNLOCK(htim);
5280
5281 return HAL_OK;
5282}
5283
5284/**
5285 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5286 * or a XOR combination between CH1_input, CH2_input & CH3_input
5287 * @param htim TIM handle.
5288 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5289 * output of a XOR gate.
5290 * This parameter can be one of the following values:
5291 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5292 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5293 * pins are connected to the TI1 input (XOR combination)
5294 * @retval HAL status
5295 */
5296HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5297{
5298 uint32_t tmpcr2;
5299
5300 /* Check the parameters */
5301 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5302 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5303
5304 /* Get the TIMx CR2 register value */
5305 tmpcr2 = htim->Instance->CR2;
5306
5307 /* Reset the TI1 selection */
5308 tmpcr2 &= ~TIM_CR2_TI1S;
5309
5310 /* Set the TI1 selection */
5311 tmpcr2 |= TI1_Selection;
5312
5313 /* Write to TIMxCR2 */
5314 htim->Instance->CR2 = tmpcr2;
5315
5316 return HAL_OK;
5317}
5318
5319/**
5320 * @brief Configures the TIM in Slave mode
5321 * @param htim TIM handle.
5322 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5323 * contains the selected trigger (internal trigger input, filtered
5324 * timer input or external trigger input) and the Slave mode
5325 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5326 * @retval HAL status
5327 */
5328HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
5329{
5330 /* Check the parameters */
5331 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5332 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5333 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5334
5335 __HAL_LOCK(htim);
5336
5337 htim->State = HAL_TIM_STATE_BUSY;
5338
5339 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5340 {
5341 htim->State = HAL_TIM_STATE_READY;
5342 __HAL_UNLOCK(htim);
5343 return HAL_ERROR;
5344 }
5345
5346 /* Disable Trigger Interrupt */
5347 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5348
5349 /* Disable Trigger DMA request */
5350 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5351
5352 htim->State = HAL_TIM_STATE_READY;
5353
5354 __HAL_UNLOCK(htim);
5355
5356 return HAL_OK;
5357}
5358
5359/**
5360 * @brief Configures the TIM in Slave mode in interrupt mode
5361 * @param htim TIM handle.
5362 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5363 * contains the selected trigger (internal trigger input, filtered
5364 * timer input or external trigger input) and the Slave mode
5365 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5366 * @retval HAL status
5367 */
5368HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5369 TIM_SlaveConfigTypeDef *sSlaveConfig)
5370{
5371 /* Check the parameters */
5372 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5373 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5374 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5375
5376 __HAL_LOCK(htim);
5377
5378 htim->State = HAL_TIM_STATE_BUSY;
5379
5380 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5381 {
5382 htim->State = HAL_TIM_STATE_READY;
5383 __HAL_UNLOCK(htim);
5384 return HAL_ERROR;
5385 }
5386
5387 /* Enable Trigger Interrupt */
5388 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5389
5390 /* Disable Trigger DMA request */
5391 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5392
5393 htim->State = HAL_TIM_STATE_READY;
5394
5395 __HAL_UNLOCK(htim);
5396
5397 return HAL_OK;
5398}
5399
5400/**
5401 * @brief Read the captured value from Capture Compare unit
5402 * @param htim TIM handle.
5403 * @param Channel TIM Channels to be enabled
5404 * This parameter can be one of the following values:
5405 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5406 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5407 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5408 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5409 * @retval Captured value
5410 */
5411uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
5412{
5413 uint32_t tmpreg = 0U;
5414
5415 switch (Channel)
5416 {
5417 case TIM_CHANNEL_1:
5418 {
5419 /* Check the parameters */
5420 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5421
5422 /* Return the capture 1 value */
5423 tmpreg = htim->Instance->CCR1;
5424
5425 break;
5426 }
5427 case TIM_CHANNEL_2:
5428 {
5429 /* Check the parameters */
5430 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5431
5432 /* Return the capture 2 value */
5433 tmpreg = htim->Instance->CCR2;
5434
5435 break;
5436 }
5437
5438 case TIM_CHANNEL_3:
5439 {
5440 /* Check the parameters */
5441 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5442
5443 /* Return the capture 3 value */
5444 tmpreg = htim->Instance->CCR3;
5445
5446 break;
5447 }
5448
5449 case TIM_CHANNEL_4:
5450 {
5451 /* Check the parameters */
5452 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5453
5454 /* Return the capture 4 value */
5455 tmpreg = htim->Instance->CCR4;
5456
5457 break;
5458 }
5459
5460 default:
5461 break;
5462 }
5463
5464 return tmpreg;
5465}
5466
5467/**
5468 * @}
5469 */
5470
5471/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5472 * @brief TIM Callbacks functions
5473 *
5474@verbatim
5475 ==============================================================================
5476 ##### TIM Callbacks functions #####
5477 ==============================================================================
5478 [..]
5479 This section provides TIM callback functions:
5480 (+) TIM Period elapsed callback
5481 (+) TIM Output Compare callback
5482 (+) TIM Input capture callback
5483 (+) TIM Trigger callback
5484 (+) TIM Error callback
5485
5486@endverbatim
5487 * @{
5488 */
5489
5490/**
5491 * @brief Period elapsed callback in non-blocking mode
5492 * @param htim TIM handle
5493 * @retval None
5494 */
5495__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5496{
5497 /* Prevent unused argument(s) compilation warning */
5498 UNUSED(htim);
5499
5500 /* NOTE : This function should not be modified, when the callback is needed,
5501 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5502 */
5503}
5504
5505/**
5506 * @brief Period elapsed half complete callback in non-blocking mode
5507 * @param htim TIM handle
5508 * @retval None
5509 */
5510__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5511{
5512 /* Prevent unused argument(s) compilation warning */
5513 UNUSED(htim);
5514
5515 /* NOTE : This function should not be modified, when the callback is needed,
5516 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5517 */
5518}
5519
5520/**
5521 * @brief Output Compare callback in non-blocking mode
5522 * @param htim TIM OC handle
5523 * @retval None
5524 */
5525__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5526{
5527 /* Prevent unused argument(s) compilation warning */
5528 UNUSED(htim);
5529
5530 /* NOTE : This function should not be modified, when the callback is needed,
5531 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5532 */
5533}
5534
5535/**
5536 * @brief Input Capture callback in non-blocking mode
5537 * @param htim TIM IC handle
5538 * @retval None
5539 */
5540__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5541{
5542 /* Prevent unused argument(s) compilation warning */
5543 UNUSED(htim);
5544
5545 /* NOTE : This function should not be modified, when the callback is needed,
5546 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5547 */
5548}
5549
5550/**
5551 * @brief Input Capture half complete callback in non-blocking mode
5552 * @param htim TIM IC handle
5553 * @retval None
5554 */
5555__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5556{
5557 /* Prevent unused argument(s) compilation warning */
5558 UNUSED(htim);
5559
5560 /* NOTE : This function should not be modified, when the callback is needed,
5561 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5562 */
5563}
5564
5565/**
5566 * @brief PWM Pulse finished callback in non-blocking mode
5567 * @param htim TIM handle
5568 * @retval None
5569 */
5570__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5571{
5572 /* Prevent unused argument(s) compilation warning */
5573 UNUSED(htim);
5574
5575 /* NOTE : This function should not be modified, when the callback is needed,
5576 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5577 */
5578}
5579
5580/**
5581 * @brief PWM Pulse finished half complete callback in non-blocking mode
5582 * @param htim TIM handle
5583 * @retval None
5584 */
5585__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5586{
5587 /* Prevent unused argument(s) compilation warning */
5588 UNUSED(htim);
5589
5590 /* NOTE : This function should not be modified, when the callback is needed,
5591 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5592 */
5593}
5594
5595/**
5596 * @brief Hall Trigger detection callback in non-blocking mode
5597 * @param htim TIM handle
5598 * @retval None
5599 */
5600__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5601{
5602 /* Prevent unused argument(s) compilation warning */
5603 UNUSED(htim);
5604
5605 /* NOTE : This function should not be modified, when the callback is needed,
5606 the HAL_TIM_TriggerCallback could be implemented in the user file
5607 */
5608}
5609
5610/**
5611 * @brief Hall Trigger detection half complete callback in non-blocking mode
5612 * @param htim TIM handle
5613 * @retval None
5614 */
5615__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5616{
5617 /* Prevent unused argument(s) compilation warning */
5618 UNUSED(htim);
5619
5620 /* NOTE : This function should not be modified, when the callback is needed,
5621 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5622 */
5623}
5624
5625/**
5626 * @brief Timer error callback in non-blocking mode
5627 * @param htim TIM handle
5628 * @retval None
5629 */
5630__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5631{
5632 /* Prevent unused argument(s) compilation warning */
5633 UNUSED(htim);
5634
5635 /* NOTE : This function should not be modified, when the callback is needed,
5636 the HAL_TIM_ErrorCallback could be implemented in the user file
5637 */
5638}
5639
5640#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5641/**
5642 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5643 * @param htim tim handle
5644 * @param CallbackID ID of the callback to be registered
5645 * This parameter can be one of the following values:
5646 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5647 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5648 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5649 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5650 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5651 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5652 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5653 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5654 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5655 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5656 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5657 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5658 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5659 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5660 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5661 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5662 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5663 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5664 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5665 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5666 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5667 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5668 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5669 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5670 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5671 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5672 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5673 * @param pCallback pointer to the callback function
5674 * @retval status
5675 */
5676HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5677 pTIM_CallbackTypeDef pCallback)
5678{
5679 HAL_StatusTypeDef status = HAL_OK;
5680
5681 if (pCallback == NULL)
5682 {
5683 return HAL_ERROR;
5684 }
5685 /* Process locked */
5686 __HAL_LOCK(htim);
5687
5688 if (htim->State == HAL_TIM_STATE_READY)
5689 {
5690 switch (CallbackID)
5691 {
5692 case HAL_TIM_BASE_MSPINIT_CB_ID :
5693 htim->Base_MspInitCallback = pCallback;
5694 break;
5695
5696 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5697 htim->Base_MspDeInitCallback = pCallback;
5698 break;
5699
5700 case HAL_TIM_IC_MSPINIT_CB_ID :
5701 htim->IC_MspInitCallback = pCallback;
5702 break;
5703
5704 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5705 htim->IC_MspDeInitCallback = pCallback;
5706 break;
5707
5708 case HAL_TIM_OC_MSPINIT_CB_ID :
5709 htim->OC_MspInitCallback = pCallback;
5710 break;
5711
5712 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5713 htim->OC_MspDeInitCallback = pCallback;
5714 break;
5715
5716 case HAL_TIM_PWM_MSPINIT_CB_ID :
5717 htim->PWM_MspInitCallback = pCallback;
5718 break;
5719
5720 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5721 htim->PWM_MspDeInitCallback = pCallback;
5722 break;
5723
5724 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5725 htim->OnePulse_MspInitCallback = pCallback;
5726 break;
5727
5728 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5729 htim->OnePulse_MspDeInitCallback = pCallback;
5730 break;
5731
5732 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5733 htim->Encoder_MspInitCallback = pCallback;
5734 break;
5735
5736 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5737 htim->Encoder_MspDeInitCallback = pCallback;
5738 break;
5739
5740 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5741 htim->HallSensor_MspInitCallback = pCallback;
5742 break;
5743
5744 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5745 htim->HallSensor_MspDeInitCallback = pCallback;
5746 break;
5747
5748 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5749 htim->PeriodElapsedCallback = pCallback;
5750 break;
5751
5752 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5753 htim->PeriodElapsedHalfCpltCallback = pCallback;
5754 break;
5755
5756 case HAL_TIM_TRIGGER_CB_ID :
5757 htim->TriggerCallback = pCallback;
5758 break;
5759
5760 case HAL_TIM_TRIGGER_HALF_CB_ID :
5761 htim->TriggerHalfCpltCallback = pCallback;
5762 break;
5763
5764 case HAL_TIM_IC_CAPTURE_CB_ID :
5765 htim->IC_CaptureCallback = pCallback;
5766 break;
5767
5768 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5769 htim->IC_CaptureHalfCpltCallback = pCallback;
5770 break;
5771
5772 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5773 htim->OC_DelayElapsedCallback = pCallback;
5774 break;
5775
5776 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5777 htim->PWM_PulseFinishedCallback = pCallback;
5778 break;
5779
5780 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5781 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5782 break;
5783
5784 case HAL_TIM_ERROR_CB_ID :
5785 htim->ErrorCallback = pCallback;
5786 break;
5787
5788 case HAL_TIM_COMMUTATION_CB_ID :
5789 htim->CommutationCallback = pCallback;
5790 break;
5791
5792 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5793 htim->CommutationHalfCpltCallback = pCallback;
5794 break;
5795
5796 case HAL_TIM_BREAK_CB_ID :
5797 htim->BreakCallback = pCallback;
5798 break;
5799
5800 default :
5801 /* Return error status */
5802 status = HAL_ERROR;
5803 break;
5804 }
5805 }
5806 else if (htim->State == HAL_TIM_STATE_RESET)
5807 {
5808 switch (CallbackID)
5809 {
5810 case HAL_TIM_BASE_MSPINIT_CB_ID :
5811 htim->Base_MspInitCallback = pCallback;
5812 break;
5813
5814 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5815 htim->Base_MspDeInitCallback = pCallback;
5816 break;
5817
5818 case HAL_TIM_IC_MSPINIT_CB_ID :
5819 htim->IC_MspInitCallback = pCallback;
5820 break;
5821
5822 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5823 htim->IC_MspDeInitCallback = pCallback;
5824 break;
5825
5826 case HAL_TIM_OC_MSPINIT_CB_ID :
5827 htim->OC_MspInitCallback = pCallback;
5828 break;
5829
5830 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5831 htim->OC_MspDeInitCallback = pCallback;
5832 break;
5833
5834 case HAL_TIM_PWM_MSPINIT_CB_ID :
5835 htim->PWM_MspInitCallback = pCallback;
5836 break;
5837
5838 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5839 htim->PWM_MspDeInitCallback = pCallback;
5840 break;
5841
5842 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5843 htim->OnePulse_MspInitCallback = pCallback;
5844 break;
5845
5846 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5847 htim->OnePulse_MspDeInitCallback = pCallback;
5848 break;
5849
5850 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5851 htim->Encoder_MspInitCallback = pCallback;
5852 break;
5853
5854 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5855 htim->Encoder_MspDeInitCallback = pCallback;
5856 break;
5857
5858 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5859 htim->HallSensor_MspInitCallback = pCallback;
5860 break;
5861
5862 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5863 htim->HallSensor_MspDeInitCallback = pCallback;
5864 break;
5865
5866 default :
5867 /* Return error status */
5868 status = HAL_ERROR;
5869 break;
5870 }
5871 }
5872 else
5873 {
5874 /* Return error status */
5875 status = HAL_ERROR;
5876 }
5877
5878 /* Release Lock */
5879 __HAL_UNLOCK(htim);
5880
5881 return status;
5882}
5883
5884/**
5885 * @brief Unregister a TIM callback
5886 * TIM callback is redirected to the weak predefined callback
5887 * @param htim tim handle
5888 * @param CallbackID ID of the callback to be unregistered
5889 * This parameter can be one of the following values:
5890 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5891 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5892 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5893 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5894 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5895 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5896 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5897 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5898 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5899 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5900 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5901 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5902 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5903 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5904 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5905 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5906 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5907 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5908 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5909 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5910 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5911 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5912 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5913 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5914 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5915 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5916 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5917 * @retval status
5918 */
5919HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
5920{
5921 HAL_StatusTypeDef status = HAL_OK;
5922
5923 /* Process locked */
5924 __HAL_LOCK(htim);
5925
5926 if (htim->State == HAL_TIM_STATE_READY)
5927 {
5928 switch (CallbackID)
5929 {
5930 case HAL_TIM_BASE_MSPINIT_CB_ID :
5931 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
5932 break;
5933
5934 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5935 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
5936 break;
5937
5938 case HAL_TIM_IC_MSPINIT_CB_ID :
5939 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
5940 break;
5941
5942 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5943 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
5944 break;
5945
5946 case HAL_TIM_OC_MSPINIT_CB_ID :
5947 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
5948 break;
5949
5950 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5951 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
5952 break;
5953
5954 case HAL_TIM_PWM_MSPINIT_CB_ID :
5955 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
5956 break;
5957
5958 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5959 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
5960 break;
5961
5962 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5963 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
5964 break;
5965
5966 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5967 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
5968 break;
5969
5970 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5971 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
5972 break;
5973
5974 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5975 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
5976 break;
5977
5978 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5979 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
5980 break;
5981
5982 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5983 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
5984 break;
5985
5986 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5987 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
5988 break;
5989
5990 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5991 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
5992 break;
5993
5994 case HAL_TIM_TRIGGER_CB_ID :
5995 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
5996 break;
5997
5998 case HAL_TIM_TRIGGER_HALF_CB_ID :
5999 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
6000 break;
6001
6002 case HAL_TIM_IC_CAPTURE_CB_ID :
6003 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
6004 break;
6005
6006 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6007 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
6008 break;
6009
6010 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6011 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
6012 break;
6013
6014 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6015 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
6016 break;
6017
6018 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6019 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
6020 break;
6021
6022 case HAL_TIM_ERROR_CB_ID :
6023 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
6024 break;
6025
6026 case HAL_TIM_COMMUTATION_CB_ID :
6027 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
6028 break;
6029
6030 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6031 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
6032 break;
6033
6034 case HAL_TIM_BREAK_CB_ID :
6035 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
6036 break;
6037
6038 default :
6039 /* Return error status */
6040 status = HAL_ERROR;
6041 break;
6042 }
6043 }
6044 else if (htim->State == HAL_TIM_STATE_RESET)
6045 {
6046 switch (CallbackID)
6047 {
6048 case HAL_TIM_BASE_MSPINIT_CB_ID :
6049 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
6050 break;
6051
6052 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6053 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
6054 break;
6055
6056 case HAL_TIM_IC_MSPINIT_CB_ID :
6057 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
6058 break;
6059
6060 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6061 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
6062 break;
6063
6064 case HAL_TIM_OC_MSPINIT_CB_ID :
6065 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
6066 break;
6067
6068 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6069 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
6070 break;
6071
6072 case HAL_TIM_PWM_MSPINIT_CB_ID :
6073 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
6074 break;
6075
6076 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6077 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
6078 break;
6079
6080 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6081 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
6082 break;
6083
6084 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6085 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
6086 break;
6087
6088 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6089 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
6090 break;
6091
6092 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6093 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
6094 break;
6095
6096 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6097 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
6098 break;
6099
6100 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6101 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
6102 break;
6103
6104 default :
6105 /* Return error status */
6106 status = HAL_ERROR;
6107 break;
6108 }
6109 }
6110 else
6111 {
6112 /* Return error status */
6113 status = HAL_ERROR;
6114 }
6115
6116 /* Release Lock */
6117 __HAL_UNLOCK(htim);
6118
6119 return status;
6120}
6121#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6122
6123/**
6124 * @}
6125 */
6126
6127/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6128 * @brief TIM Peripheral State functions
6129 *
6130@verbatim
6131 ==============================================================================
6132 ##### Peripheral State functions #####
6133 ==============================================================================
6134 [..]
6135 This subsection permits to get in run-time the status of the peripheral
6136 and the data flow.
6137
6138@endverbatim
6139 * @{
6140 */
6141
6142/**
6143 * @brief Return the TIM Base handle state.
6144 * @param htim TIM Base handle
6145 * @retval HAL state
6146 */
6147HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
6148{
6149 return htim->State;
6150}
6151
6152/**
6153 * @brief Return the TIM OC handle state.
6154 * @param htim TIM Output Compare handle
6155 * @retval HAL state
6156 */
6157HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
6158{
6159 return htim->State;
6160}
6161
6162/**
6163 * @brief Return the TIM PWM handle state.
6164 * @param htim TIM handle
6165 * @retval HAL state
6166 */
6167HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
6168{
6169 return htim->State;
6170}
6171
6172/**
6173 * @brief Return the TIM Input Capture handle state.
6174 * @param htim TIM IC handle
6175 * @retval HAL state
6176 */
6177HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
6178{
6179 return htim->State;
6180}
6181
6182/**
6183 * @brief Return the TIM One Pulse Mode handle state.
6184 * @param htim TIM OPM handle
6185 * @retval HAL state
6186 */
6187HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
6188{
6189 return htim->State;
6190}
6191
6192/**
6193 * @brief Return the TIM Encoder Mode handle state.
6194 * @param htim TIM Encoder Interface handle
6195 * @retval HAL state
6196 */
6197HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
6198{
6199 return htim->State;
6200}
6201
6202/**
6203 * @brief Return the TIM Encoder Mode handle state.
6204 * @param htim TIM handle
6205 * @retval Active channel
6206 */
6207HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
6208{
6209 return htim->Channel;
6210}
6211
6212/**
6213 * @brief Return actual state of the TIM channel.
6214 * @param htim TIM handle
6215 * @param Channel TIM Channel
6216 * This parameter can be one of the following values:
6217 * @arg TIM_CHANNEL_1: TIM Channel 1
6218 * @arg TIM_CHANNEL_2: TIM Channel 2
6219 * @arg TIM_CHANNEL_3: TIM Channel 3
6220 * @arg TIM_CHANNEL_4: TIM Channel 4
6221 * @arg TIM_CHANNEL_5: TIM Channel 5
6222 * @arg TIM_CHANNEL_6: TIM Channel 6
6223 * @retval TIM Channel state
6224 */
6225HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
6226{
6227 HAL_TIM_ChannelStateTypeDef channel_state;
6228
6229 /* Check the parameters */
6230 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6231
6232 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6233
6234 return channel_state;
6235}
6236
6237/**
6238 * @brief Return actual state of a DMA burst operation.
6239 * @param htim TIM handle
6240 * @retval DMA burst state
6241 */
6242HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
6243{
6244 /* Check the parameters */
6245 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6246
6247 return htim->DMABurstState;
6248}
6249
6250/**
6251 * @}
6252 */
6253
6254/**
6255 * @}
6256 */
6257
6258/** @defgroup TIM_Private_Functions TIM Private Functions
6259 * @{
6260 */
6261
6262/**
6263 * @brief TIM DMA error callback
6264 * @param hdma pointer to DMA handle.
6265 * @retval None
6266 */
6267void TIM_DMAError(DMA_HandleTypeDef *hdma)
6268{
6269 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6270
6271 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6272 {
6273 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6274 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6275 }
6276 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6277 {
6278 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6279 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6280 }
6281 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6282 {
6283 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6284 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6285 }
6286 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6287 {
6288 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6289 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6290 }
6291 else
6292 {
6293 htim->State = HAL_TIM_STATE_READY;
6294 }
6295
6296#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6297 htim->ErrorCallback(htim);
6298#else
6299 HAL_TIM_ErrorCallback(htim);
6300#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6301
6302 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6303}
6304
6305/**
6306 * @brief TIM DMA Delay Pulse complete callback.
6307 * @param hdma pointer to DMA handle.
6308 * @retval None
6309 */
6310static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6311{
6312 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6313
6314 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6315 {
6316 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6317
6318 if (hdma->Init.Mode == DMA_NORMAL)
6319 {
6320 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6321 }
6322 }
6323 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6324 {
6325 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6326
6327 if (hdma->Init.Mode == DMA_NORMAL)
6328 {
6329 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6330 }
6331 }
6332 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6333 {
6334 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6335
6336 if (hdma->Init.Mode == DMA_NORMAL)
6337 {
6338 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6339 }
6340 }
6341 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6342 {
6343 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6344
6345 if (hdma->Init.Mode == DMA_NORMAL)
6346 {
6347 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6348 }
6349 }
6350 else
6351 {
6352 /* nothing to do */
6353 }
6354
6355#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6356 htim->PWM_PulseFinishedCallback(htim);
6357#else
6358 HAL_TIM_PWM_PulseFinishedCallback(htim);
6359#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6360
6361 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6362}
6363
6364/**
6365 * @brief TIM DMA Delay Pulse half complete callback.
6366 * @param hdma pointer to DMA handle.
6367 * @retval None
6368 */
6369void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6370{
6371 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6372
6373 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6374 {
6375 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6376 }
6377 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6378 {
6379 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6380 }
6381 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6382 {
6383 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6384 }
6385 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6386 {
6387 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6388 }
6389 else
6390 {
6391 /* nothing to do */
6392 }
6393
6394#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6395 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6396#else
6397 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6398#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6399
6400 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6401}
6402
6403/**
6404 * @brief TIM DMA Capture complete callback.
6405 * @param hdma pointer to DMA handle.
6406 * @retval None
6407 */
6408void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6409{
6410 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6411
6412 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6413 {
6414 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6415
6416 if (hdma->Init.Mode == DMA_NORMAL)
6417 {
6418 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6419 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6420 }
6421 }
6422 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6423 {
6424 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6425
6426 if (hdma->Init.Mode == DMA_NORMAL)
6427 {
6428 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6429 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6430 }
6431 }
6432 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6433 {
6434 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6435
6436 if (hdma->Init.Mode == DMA_NORMAL)
6437 {
6438 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6439 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6440 }
6441 }
6442 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6443 {
6444 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6445
6446 if (hdma->Init.Mode == DMA_NORMAL)
6447 {
6448 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6449 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6450 }
6451 }
6452 else
6453 {
6454 /* nothing to do */
6455 }
6456
6457#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6458 htim->IC_CaptureCallback(htim);
6459#else
6460 HAL_TIM_IC_CaptureCallback(htim);
6461#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6462
6463 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6464}
6465
6466/**
6467 * @brief TIM DMA Capture half complete callback.
6468 * @param hdma pointer to DMA handle.
6469 * @retval None
6470 */
6471void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6472{
6473 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6474
6475 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6476 {
6477 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6478 }
6479 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6480 {
6481 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6482 }
6483 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6484 {
6485 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6486 }
6487 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6488 {
6489 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6490 }
6491 else
6492 {
6493 /* nothing to do */
6494 }
6495
6496#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6497 htim->IC_CaptureHalfCpltCallback(htim);
6498#else
6499 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6500#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6501
6502 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6503}
6504
6505/**
6506 * @brief TIM DMA Period Elapse complete callback.
6507 * @param hdma pointer to DMA handle.
6508 * @retval None
6509 */
6510static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6511{
6512 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6513
6514 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6515 {
6516 htim->State = HAL_TIM_STATE_READY;
6517 }
6518
6519#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6520 htim->PeriodElapsedCallback(htim);
6521#else
6522 HAL_TIM_PeriodElapsedCallback(htim);
6523#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6524}
6525
6526/**
6527 * @brief TIM DMA Period Elapse half complete callback.
6528 * @param hdma pointer to DMA handle.
6529 * @retval None
6530 */
6531static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6532{
6533 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6534
6535#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6536 htim->PeriodElapsedHalfCpltCallback(htim);
6537#else
6538 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6539#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6540}
6541
6542/**
6543 * @brief TIM DMA Trigger callback.
6544 * @param hdma pointer to DMA handle.
6545 * @retval None
6546 */
6547static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6548{
6549 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6550
6551 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6552 {
6553 htim->State = HAL_TIM_STATE_READY;
6554 }
6555
6556#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6557 htim->TriggerCallback(htim);
6558#else
6559 HAL_TIM_TriggerCallback(htim);
6560#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6561}
6562
6563/**
6564 * @brief TIM DMA Trigger half complete callback.
6565 * @param hdma pointer to DMA handle.
6566 * @retval None
6567 */
6568static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6569{
6570 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6571
6572#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6573 htim->TriggerHalfCpltCallback(htim);
6574#else
6575 HAL_TIM_TriggerHalfCpltCallback(htim);
6576#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6577}
6578
6579/**
6580 * @brief Time Base configuration
6581 * @param TIMx TIM peripheral
6582 * @param Structure TIM Base configuration structure
6583 * @retval None
6584 */
6585void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
6586{
6587 uint32_t tmpcr1;
6588 tmpcr1 = TIMx->CR1;
6589
6590 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6591 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6592 {
6593 /* Select the Counter Mode */
6594 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6595 tmpcr1 |= Structure->CounterMode;
6596 }
6597
6598 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6599 {
6600 /* Set the clock division */
6601 tmpcr1 &= ~TIM_CR1_CKD;
6602 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6603 }
6604
6605 /* Set the auto-reload preload */
6606 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6607
6608 TIMx->CR1 = tmpcr1;
6609
6610 /* Set the Autoreload value */
6611 TIMx->ARR = (uint32_t)Structure->Period ;
6612
6613 /* Set the Prescaler value */
6614 TIMx->PSC = Structure->Prescaler;
6615
6616 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6617 {
6618 /* Set the Repetition Counter value */
6619 TIMx->RCR = Structure->RepetitionCounter;
6620 }
6621
6622 /* Generate an update event to reload the Prescaler
6623 and the repetition counter (only for advanced timer) value immediately */
6624 TIMx->EGR = TIM_EGR_UG;
6625}
6626
6627/**
6628 * @brief Timer Output Compare 1 configuration
6629 * @param TIMx to select the TIM peripheral
6630 * @param OC_Config The output configuration structure
6631 * @retval None
6632 */
6633static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6634{
6635 uint32_t tmpccmrx;
6636 uint32_t tmpccer;
6637 uint32_t tmpcr2;
6638
6639 /* Disable the Channel 1: Reset the CC1E Bit */
6640 TIMx->CCER &= ~TIM_CCER_CC1E;
6641
6642 /* Get the TIMx CCER register value */
6643 tmpccer = TIMx->CCER;
6644 /* Get the TIMx CR2 register value */
6645 tmpcr2 = TIMx->CR2;
6646
6647 /* Get the TIMx CCMR1 register value */
6648 tmpccmrx = TIMx->CCMR1;
6649
6650 /* Reset the Output Compare Mode Bits */
6651 tmpccmrx &= ~TIM_CCMR1_OC1M;
6652 tmpccmrx &= ~TIM_CCMR1_CC1S;
6653 /* Select the Output Compare Mode */
6654 tmpccmrx |= OC_Config->OCMode;
6655
6656 /* Reset the Output Polarity level */
6657 tmpccer &= ~TIM_CCER_CC1P;
6658 /* Set the Output Compare Polarity */
6659 tmpccer |= OC_Config->OCPolarity;
6660
6661 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
6662 {
6663 /* Check parameters */
6664 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6665
6666 /* Reset the Output N Polarity level */
6667 tmpccer &= ~TIM_CCER_CC1NP;
6668 /* Set the Output N Polarity */
6669 tmpccer |= OC_Config->OCNPolarity;
6670 /* Reset the Output N State */
6671 tmpccer &= ~TIM_CCER_CC1NE;
6672 }
6673
6674 if (IS_TIM_BREAK_INSTANCE(TIMx))
6675 {
6676 /* Check parameters */
6677 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6678 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6679
6680 /* Reset the Output Compare and Output Compare N IDLE State */
6681 tmpcr2 &= ~TIM_CR2_OIS1;
6682 tmpcr2 &= ~TIM_CR2_OIS1N;
6683 /* Set the Output Idle state */
6684 tmpcr2 |= OC_Config->OCIdleState;
6685 /* Set the Output N Idle state */
6686 tmpcr2 |= OC_Config->OCNIdleState;
6687 }
6688
6689 /* Write to TIMx CR2 */
6690 TIMx->CR2 = tmpcr2;
6691
6692 /* Write to TIMx CCMR1 */
6693 TIMx->CCMR1 = tmpccmrx;
6694
6695 /* Set the Capture Compare Register value */
6696 TIMx->CCR1 = OC_Config->Pulse;
6697
6698 /* Write to TIMx CCER */
6699 TIMx->CCER = tmpccer;
6700}
6701
6702/**
6703 * @brief Timer Output Compare 2 configuration
6704 * @param TIMx to select the TIM peripheral
6705 * @param OC_Config The output configuration structure
6706 * @retval None
6707 */
6708void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6709{
6710 uint32_t tmpccmrx;
6711 uint32_t tmpccer;
6712 uint32_t tmpcr2;
6713
6714 /* Disable the Channel 2: Reset the CC2E Bit */
6715 TIMx->CCER &= ~TIM_CCER_CC2E;
6716
6717 /* Get the TIMx CCER register value */
6718 tmpccer = TIMx->CCER;
6719 /* Get the TIMx CR2 register value */
6720 tmpcr2 = TIMx->CR2;
6721
6722 /* Get the TIMx CCMR1 register value */
6723 tmpccmrx = TIMx->CCMR1;
6724
6725 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6726 tmpccmrx &= ~TIM_CCMR1_OC2M;
6727 tmpccmrx &= ~TIM_CCMR1_CC2S;
6728
6729 /* Select the Output Compare Mode */
6730 tmpccmrx |= (OC_Config->OCMode << 8U);
6731
6732 /* Reset the Output Polarity level */
6733 tmpccer &= ~TIM_CCER_CC2P;
6734 /* Set the Output Compare Polarity */
6735 tmpccer |= (OC_Config->OCPolarity << 4U);
6736
6737 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
6738 {
6739 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6740
6741 /* Reset the Output N Polarity level */
6742 tmpccer &= ~TIM_CCER_CC2NP;
6743 /* Set the Output N Polarity */
6744 tmpccer |= (OC_Config->OCNPolarity << 4U);
6745 /* Reset the Output N State */
6746 tmpccer &= ~TIM_CCER_CC2NE;
6747
6748 }
6749
6750 if (IS_TIM_BREAK_INSTANCE(TIMx))
6751 {
6752 /* Check parameters */
6753 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6754 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6755
6756 /* Reset the Output Compare and Output Compare N IDLE State */
6757 tmpcr2 &= ~TIM_CR2_OIS2;
6758 tmpcr2 &= ~TIM_CR2_OIS2N;
6759 /* Set the Output Idle state */
6760 tmpcr2 |= (OC_Config->OCIdleState << 2U);
6761 /* Set the Output N Idle state */
6762 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
6763 }
6764
6765 /* Write to TIMx CR2 */
6766 TIMx->CR2 = tmpcr2;
6767
6768 /* Write to TIMx CCMR1 */
6769 TIMx->CCMR1 = tmpccmrx;
6770
6771 /* Set the Capture Compare Register value */
6772 TIMx->CCR2 = OC_Config->Pulse;
6773
6774 /* Write to TIMx CCER */
6775 TIMx->CCER = tmpccer;
6776}
6777
6778/**
6779 * @brief Timer Output Compare 3 configuration
6780 * @param TIMx to select the TIM peripheral
6781 * @param OC_Config The output configuration structure
6782 * @retval None
6783 */
6784static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6785{
6786 uint32_t tmpccmrx;
6787 uint32_t tmpccer;
6788 uint32_t tmpcr2;
6789
6790 /* Disable the Channel 3: Reset the CC2E Bit */
6791 TIMx->CCER &= ~TIM_CCER_CC3E;
6792
6793 /* Get the TIMx CCER register value */
6794 tmpccer = TIMx->CCER;
6795 /* Get the TIMx CR2 register value */
6796 tmpcr2 = TIMx->CR2;
6797
6798 /* Get the TIMx CCMR2 register value */
6799 tmpccmrx = TIMx->CCMR2;
6800
6801 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6802 tmpccmrx &= ~TIM_CCMR2_OC3M;
6803 tmpccmrx &= ~TIM_CCMR2_CC3S;
6804 /* Select the Output Compare Mode */
6805 tmpccmrx |= OC_Config->OCMode;
6806
6807 /* Reset the Output Polarity level */
6808 tmpccer &= ~TIM_CCER_CC3P;
6809 /* Set the Output Compare Polarity */
6810 tmpccer |= (OC_Config->OCPolarity << 8U);
6811
6812 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
6813 {
6814 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6815
6816 /* Reset the Output N Polarity level */
6817 tmpccer &= ~TIM_CCER_CC3NP;
6818 /* Set the Output N Polarity */
6819 tmpccer |= (OC_Config->OCNPolarity << 8U);
6820 /* Reset the Output N State */
6821 tmpccer &= ~TIM_CCER_CC3NE;
6822 }
6823
6824 if (IS_TIM_BREAK_INSTANCE(TIMx))
6825 {
6826 /* Check parameters */
6827 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6828 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6829
6830 /* Reset the Output Compare and Output Compare N IDLE State */
6831 tmpcr2 &= ~TIM_CR2_OIS3;
6832 tmpcr2 &= ~TIM_CR2_OIS3N;
6833 /* Set the Output Idle state */
6834 tmpcr2 |= (OC_Config->OCIdleState << 4U);
6835 /* Set the Output N Idle state */
6836 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
6837 }
6838
6839 /* Write to TIMx CR2 */
6840 TIMx->CR2 = tmpcr2;
6841
6842 /* Write to TIMx CCMR2 */
6843 TIMx->CCMR2 = tmpccmrx;
6844
6845 /* Set the Capture Compare Register value */
6846 TIMx->CCR3 = OC_Config->Pulse;
6847
6848 /* Write to TIMx CCER */
6849 TIMx->CCER = tmpccer;
6850}
6851
6852/**
6853 * @brief Timer Output Compare 4 configuration
6854 * @param TIMx to select the TIM peripheral
6855 * @param OC_Config The output configuration structure
6856 * @retval None
6857 */
6858static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6859{
6860 uint32_t tmpccmrx;
6861 uint32_t tmpccer;
6862 uint32_t tmpcr2;
6863
6864 /* Disable the Channel 4: Reset the CC4E Bit */
6865 TIMx->CCER &= ~TIM_CCER_CC4E;
6866
6867 /* Get the TIMx CCER register value */
6868 tmpccer = TIMx->CCER;
6869 /* Get the TIMx CR2 register value */
6870 tmpcr2 = TIMx->CR2;
6871
6872 /* Get the TIMx CCMR2 register value */
6873 tmpccmrx = TIMx->CCMR2;
6874
6875 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6876 tmpccmrx &= ~TIM_CCMR2_OC4M;
6877 tmpccmrx &= ~TIM_CCMR2_CC4S;
6878
6879 /* Select the Output Compare Mode */
6880 tmpccmrx |= (OC_Config->OCMode << 8U);
6881
6882 /* Reset the Output Polarity level */
6883 tmpccer &= ~TIM_CCER_CC4P;
6884 /* Set the Output Compare Polarity */
6885 tmpccer |= (OC_Config->OCPolarity << 12U);
6886
6887 if (IS_TIM_BREAK_INSTANCE(TIMx))
6888 {
6889 /* Check parameters */
6890 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6891
6892 /* Reset the Output Compare IDLE State */
6893 tmpcr2 &= ~TIM_CR2_OIS4;
6894
6895 /* Set the Output Idle state */
6896 tmpcr2 |= (OC_Config->OCIdleState << 6U);
6897 }
6898
6899 /* Write to TIMx CR2 */
6900 TIMx->CR2 = tmpcr2;
6901
6902 /* Write to TIMx CCMR2 */
6903 TIMx->CCMR2 = tmpccmrx;
6904
6905 /* Set the Capture Compare Register value */
6906 TIMx->CCR4 = OC_Config->Pulse;
6907
6908 /* Write to TIMx CCER */
6909 TIMx->CCER = tmpccer;
6910}
6911
6912/**
6913 * @brief Slave Timer configuration function
6914 * @param htim TIM handle
6915 * @param sSlaveConfig Slave timer configuration
6916 * @retval None
6917 */
6918static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
6919 TIM_SlaveConfigTypeDef *sSlaveConfig)
6920{
6921 uint32_t tmpsmcr;
6922 uint32_t tmpccmr1;
6923 uint32_t tmpccer;
6924
6925 /* Get the TIMx SMCR register value */
6926 tmpsmcr = htim->Instance->SMCR;
6927
6928 /* Reset the Trigger Selection Bits */
6929 tmpsmcr &= ~TIM_SMCR_TS;
6930 /* Set the Input Trigger source */
6931 tmpsmcr |= sSlaveConfig->InputTrigger;
6932
6933 /* Reset the slave mode Bits */
6934 tmpsmcr &= ~TIM_SMCR_SMS;
6935 /* Set the slave mode */
6936 tmpsmcr |= sSlaveConfig->SlaveMode;
6937
6938 /* Write to TIMx SMCR */
6939 htim->Instance->SMCR = tmpsmcr;
6940
6941 /* Configure the trigger prescaler, filter, and polarity */
6942 switch (sSlaveConfig->InputTrigger)
6943 {
6944 case TIM_TS_ETRF:
6945 {
6946 /* Check the parameters */
6947 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
6948 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
6949 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6950 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6951 /* Configure the ETR Trigger source */
6952 TIM_ETR_SetConfig(htim->Instance,
6953 sSlaveConfig->TriggerPrescaler,
6954 sSlaveConfig->TriggerPolarity,
6955 sSlaveConfig->TriggerFilter);
6956 break;
6957 }
6958
6959 case TIM_TS_TI1F_ED:
6960 {
6961 /* Check the parameters */
6962 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6963 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6964
6965 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
6966 {
6967 return HAL_ERROR;
6968 }
6969
6970 /* Disable the Channel 1: Reset the CC1E Bit */
6971 tmpccer = htim->Instance->CCER;
6972 htim->Instance->CCER &= ~TIM_CCER_CC1E;
6973 tmpccmr1 = htim->Instance->CCMR1;
6974
6975 /* Set the filter */
6976 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6977 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
6978
6979 /* Write to TIMx CCMR1 and CCER registers */
6980 htim->Instance->CCMR1 = tmpccmr1;
6981 htim->Instance->CCER = tmpccer;
6982 break;
6983 }
6984
6985 case TIM_TS_TI1FP1:
6986 {
6987 /* Check the parameters */
6988 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6989 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6990 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6991
6992 /* Configure TI1 Filter and Polarity */
6993 TIM_TI1_ConfigInputStage(htim->Instance,
6994 sSlaveConfig->TriggerPolarity,
6995 sSlaveConfig->TriggerFilter);
6996 break;
6997 }
6998
6999 case TIM_TS_TI2FP2:
7000 {
7001 /* Check the parameters */
7002 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7003 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7004 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7005
7006 /* Configure TI2 Filter and Polarity */
7007 TIM_TI2_ConfigInputStage(htim->Instance,
7008 sSlaveConfig->TriggerPolarity,
7009 sSlaveConfig->TriggerFilter);
7010 break;
7011 }
7012
7013 case TIM_TS_ITR0:
7014 case TIM_TS_ITR1:
7015 case TIM_TS_ITR2:
7016 case TIM_TS_ITR3:
7017 {
7018 /* Check the parameter */
7019 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7020 break;
7021 }
7022
7023 default:
7024 break;
7025 }
7026 return HAL_OK;
7027}
7028
7029/**
7030 * @brief Configure the TI1 as Input.
7031 * @param TIMx to select the TIM peripheral.
7032 * @param TIM_ICPolarity The Input Polarity.
7033 * This parameter can be one of the following values:
7034 * @arg TIM_ICPOLARITY_RISING
7035 * @arg TIM_ICPOLARITY_FALLING
7036 * @arg TIM_ICPOLARITY_BOTHEDGE
7037 * @param TIM_ICSelection specifies the input to be used.
7038 * This parameter can be one of the following values:
7039 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7040 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7041 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7042 * @param TIM_ICFilter Specifies the Input Capture Filter.
7043 * This parameter must be a value between 0x00 and 0x0F.
7044 * @retval None
7045 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7046 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7047 * protected against un-initialized filter and polarity values.
7048 */
7049void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7050 uint32_t TIM_ICFilter)
7051{
7052 uint32_t tmpccmr1;
7053 uint32_t tmpccer;
7054
7055 /* Disable the Channel 1: Reset the CC1E Bit */
7056 TIMx->CCER &= ~TIM_CCER_CC1E;
7057 tmpccmr1 = TIMx->CCMR1;
7058 tmpccer = TIMx->CCER;
7059
7060 /* Select the Input */
7061 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7062 {
7063 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7064 tmpccmr1 |= TIM_ICSelection;
7065 }
7066 else
7067 {
7068 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7069 }
7070
7071 /* Set the filter */
7072 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7073 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7074
7075 /* Select the Polarity and set the CC1E Bit */
7076 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7077 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7078
7079 /* Write to TIMx CCMR1 and CCER registers */
7080 TIMx->CCMR1 = tmpccmr1;
7081 TIMx->CCER = tmpccer;
7082}
7083
7084/**
7085 * @brief Configure the Polarity and Filter for TI1.
7086 * @param TIMx to select the TIM peripheral.
7087 * @param TIM_ICPolarity The Input Polarity.
7088 * This parameter can be one of the following values:
7089 * @arg TIM_ICPOLARITY_RISING
7090 * @arg TIM_ICPOLARITY_FALLING
7091 * @arg TIM_ICPOLARITY_BOTHEDGE
7092 * @param TIM_ICFilter Specifies the Input Capture Filter.
7093 * This parameter must be a value between 0x00 and 0x0F.
7094 * @retval None
7095 */
7096static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7097{
7098 uint32_t tmpccmr1;
7099 uint32_t tmpccer;
7100
7101 /* Disable the Channel 1: Reset the CC1E Bit */
7102 tmpccer = TIMx->CCER;
7103 TIMx->CCER &= ~TIM_CCER_CC1E;
7104 tmpccmr1 = TIMx->CCMR1;
7105
7106 /* Set the filter */
7107 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7108 tmpccmr1 |= (TIM_ICFilter << 4U);
7109
7110 /* Select the Polarity and set the CC1E Bit */
7111 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7112 tmpccer |= TIM_ICPolarity;
7113
7114 /* Write to TIMx CCMR1 and CCER registers */
7115 TIMx->CCMR1 = tmpccmr1;
7116 TIMx->CCER = tmpccer;
7117}
7118
7119/**
7120 * @brief Configure the TI2 as Input.
7121 * @param TIMx to select the TIM peripheral
7122 * @param TIM_ICPolarity The Input Polarity.
7123 * This parameter can be one of the following values:
7124 * @arg TIM_ICPOLARITY_RISING
7125 * @arg TIM_ICPOLARITY_FALLING
7126 * @arg TIM_ICPOLARITY_BOTHEDGE
7127 * @param TIM_ICSelection specifies the input to be used.
7128 * This parameter can be one of the following values:
7129 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7130 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7131 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7132 * @param TIM_ICFilter Specifies the Input Capture Filter.
7133 * This parameter must be a value between 0x00 and 0x0F.
7134 * @retval None
7135 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7136 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7137 * protected against un-initialized filter and polarity values.
7138 */
7139static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7140 uint32_t TIM_ICFilter)
7141{
7142 uint32_t tmpccmr1;
7143 uint32_t tmpccer;
7144
7145 /* Disable the Channel 2: Reset the CC2E Bit */
7146 TIMx->CCER &= ~TIM_CCER_CC2E;
7147 tmpccmr1 = TIMx->CCMR1;
7148 tmpccer = TIMx->CCER;
7149
7150 /* Select the Input */
7151 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7152 tmpccmr1 |= (TIM_ICSelection << 8U);
7153
7154 /* Set the filter */
7155 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7156 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7157
7158 /* Select the Polarity and set the CC2E Bit */
7159 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7160 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7161
7162 /* Write to TIMx CCMR1 and CCER registers */
7163 TIMx->CCMR1 = tmpccmr1 ;
7164 TIMx->CCER = tmpccer;
7165}
7166
7167/**
7168 * @brief Configure the Polarity and Filter for TI2.
7169 * @param TIMx to select the TIM peripheral.
7170 * @param TIM_ICPolarity The Input Polarity.
7171 * This parameter can be one of the following values:
7172 * @arg TIM_ICPOLARITY_RISING
7173 * @arg TIM_ICPOLARITY_FALLING
7174 * @arg TIM_ICPOLARITY_BOTHEDGE
7175 * @param TIM_ICFilter Specifies the Input Capture Filter.
7176 * This parameter must be a value between 0x00 and 0x0F.
7177 * @retval None
7178 */
7179static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7180{
7181 uint32_t tmpccmr1;
7182 uint32_t tmpccer;
7183
7184 /* Disable the Channel 2: Reset the CC2E Bit */
7185 TIMx->CCER &= ~TIM_CCER_CC2E;
7186 tmpccmr1 = TIMx->CCMR1;
7187 tmpccer = TIMx->CCER;
7188
7189 /* Set the filter */
7190 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7191 tmpccmr1 |= (TIM_ICFilter << 12U);
7192
7193 /* Select the Polarity and set the CC2E Bit */
7194 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7195 tmpccer |= (TIM_ICPolarity << 4U);
7196
7197 /* Write to TIMx CCMR1 and CCER registers */
7198 TIMx->CCMR1 = tmpccmr1 ;
7199 TIMx->CCER = tmpccer;
7200}
7201
7202/**
7203 * @brief Configure the TI3 as Input.
7204 * @param TIMx to select the TIM peripheral
7205 * @param TIM_ICPolarity The Input Polarity.
7206 * This parameter can be one of the following values:
7207 * @arg TIM_ICPOLARITY_RISING
7208 * @arg TIM_ICPOLARITY_FALLING
7209 * @arg TIM_ICPOLARITY_BOTHEDGE
7210 * @param TIM_ICSelection specifies the input to be used.
7211 * This parameter can be one of the following values:
7212 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7213 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7214 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7215 * @param TIM_ICFilter Specifies the Input Capture Filter.
7216 * This parameter must be a value between 0x00 and 0x0F.
7217 * @retval None
7218 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7219 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7220 * protected against un-initialized filter and polarity values.
7221 */
7222static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7223 uint32_t TIM_ICFilter)
7224{
7225 uint32_t tmpccmr2;
7226 uint32_t tmpccer;
7227
7228 /* Disable the Channel 3: Reset the CC3E Bit */
7229 TIMx->CCER &= ~TIM_CCER_CC3E;
7230 tmpccmr2 = TIMx->CCMR2;
7231 tmpccer = TIMx->CCER;
7232
7233 /* Select the Input */
7234 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7235 tmpccmr2 |= TIM_ICSelection;
7236
7237 /* Set the filter */
7238 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7239 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7240
7241 /* Select the Polarity and set the CC3E Bit */
7242 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7243 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7244
7245 /* Write to TIMx CCMR2 and CCER registers */
7246 TIMx->CCMR2 = tmpccmr2;
7247 TIMx->CCER = tmpccer;
7248}
7249
7250/**
7251 * @brief Configure the TI4 as Input.
7252 * @param TIMx to select the TIM peripheral
7253 * @param TIM_ICPolarity The Input Polarity.
7254 * This parameter can be one of the following values:
7255 * @arg TIM_ICPOLARITY_RISING
7256 * @arg TIM_ICPOLARITY_FALLING
7257 * @arg TIM_ICPOLARITY_BOTHEDGE
7258 * @param TIM_ICSelection specifies the input to be used.
7259 * This parameter can be one of the following values:
7260 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7261 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7262 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7263 * @param TIM_ICFilter Specifies the Input Capture Filter.
7264 * This parameter must be a value between 0x00 and 0x0F.
7265 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7266 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7267 * protected against un-initialized filter and polarity values.
7268 * @retval None
7269 */
7270static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7271 uint32_t TIM_ICFilter)
7272{
7273 uint32_t tmpccmr2;
7274 uint32_t tmpccer;
7275
7276 /* Disable the Channel 4: Reset the CC4E Bit */
7277 TIMx->CCER &= ~TIM_CCER_CC4E;
7278 tmpccmr2 = TIMx->CCMR2;
7279 tmpccer = TIMx->CCER;
7280
7281 /* Select the Input */
7282 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7283 tmpccmr2 |= (TIM_ICSelection << 8U);
7284
7285 /* Set the filter */
7286 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7287 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7288
7289 /* Select the Polarity and set the CC4E Bit */
7290 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7291 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7292
7293 /* Write to TIMx CCMR2 and CCER registers */
7294 TIMx->CCMR2 = tmpccmr2;
7295 TIMx->CCER = tmpccer ;
7296}
7297
7298/**
7299 * @brief Selects the Input Trigger source
7300 * @param TIMx to select the TIM peripheral
7301 * @param InputTriggerSource The Input Trigger source.
7302 * This parameter can be one of the following values:
7303 * @arg TIM_TS_ITR0: Internal Trigger 0
7304 * @arg TIM_TS_ITR1: Internal Trigger 1
7305 * @arg TIM_TS_ITR2: Internal Trigger 2
7306 * @arg TIM_TS_ITR3: Internal Trigger 3
7307 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7308 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7309 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7310 * @arg TIM_TS_ETRF: External Trigger input
7311 * @retval None
7312 */
7313static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7314{
7315 uint32_t tmpsmcr;
7316
7317 /* Get the TIMx SMCR register value */
7318 tmpsmcr = TIMx->SMCR;
7319 /* Reset the TS Bits */
7320 tmpsmcr &= ~TIM_SMCR_TS;
7321 /* Set the Input Trigger source and the slave mode*/
7322 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7323 /* Write to TIMx SMCR */
7324 TIMx->SMCR = tmpsmcr;
7325}
7326/**
7327 * @brief Configures the TIMx External Trigger (ETR).
7328 * @param TIMx to select the TIM peripheral
7329 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7330 * This parameter can be one of the following values:
7331 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7332 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7333 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7334 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7335 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7336 * This parameter can be one of the following values:
7337 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7338 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7339 * @param ExtTRGFilter External Trigger Filter.
7340 * This parameter must be a value between 0x00 and 0x0F
7341 * @retval None
7342 */
7343void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7344 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7345{
7346 uint32_t tmpsmcr;
7347
7348 tmpsmcr = TIMx->SMCR;
7349
7350 /* Reset the ETR Bits */
7351 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7352
7353 /* Set the Prescaler, the Filter value and the Polarity */
7354 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7355
7356 /* Write to TIMx SMCR */
7357 TIMx->SMCR = tmpsmcr;
7358}
7359
7360/**
7361 * @brief Enables or disables the TIM Capture Compare Channel x.
7362 * @param TIMx to select the TIM peripheral
7363 * @param Channel specifies the TIM Channel
7364 * This parameter can be one of the following values:
7365 * @arg TIM_CHANNEL_1: TIM Channel 1
7366 * @arg TIM_CHANNEL_2: TIM Channel 2
7367 * @arg TIM_CHANNEL_3: TIM Channel 3
7368 * @arg TIM_CHANNEL_4: TIM Channel 4
7369 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7370 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7371 * @retval None
7372 */
7373void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7374{
7375 uint32_t tmp;
7376
7377 /* Check the parameters */
7378 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7379 assert_param(IS_TIM_CHANNELS(Channel));
7380
7381 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7382
7383 /* Reset the CCxE Bit */
7384 TIMx->CCER &= ~tmp;
7385
7386 /* Set or reset the CCxE Bit */
7387 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7388}
7389
7390#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7391/**
7392 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7393 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7394 * the configuration information for TIM module.
7395 * @retval None
7396 */
7397void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7398{
7399 /* Reset the TIM callback to the legacy weak callbacks */
7400 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
7401 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
7402 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
7403 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
7404 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
7405 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
7406 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
7407 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
7408 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
7409 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
7410 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
7411 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
7412 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
7413}
7414#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7415
7416/**
7417 * @}
7418 */
7419
7420#endif /* HAL_TIM_MODULE_ENABLED */
7421/**
7422 * @}
7423 */
7424
7425/**
7426 * @}
7427 */
7428/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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