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stm32f4xx_ll_adc.c

Last change on this file was 1, checked in by AlexLir, 4 years ago

File size: 42.8 KB

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_ll_adc.c
4	* @author MCD Application Team
5	* @brief ADC LL module driver
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19	#if defined(USE_FULL_LL_DRIVER)
20
21	/* Includes ------------------------------------------------------------------*/
22	#include "stm32f4xx_ll_adc.h"
23	#include "stm32f4xx_ll_bus.h"
24
25	#ifdef USE_FULL_ASSERT
26	#include "stm32_assert.h"
27	#else
28	#define assert_param(expr) ((void)0U)
29	#endif
30
31	/** @addtogroup STM32F4xx_LL_Driver
32	* @{
33	*/
34
35	#if defined (ADC1) \|\| defined (ADC2) \|\| defined (ADC3)
36
37	/** @addtogroup ADC_LL ADC
38	* @{
39	*/
40
41	/* Private types -------------------------------------------------------------*/
42	/* Private variables ---------------------------------------------------------*/
43	/* Private constants ---------------------------------------------------------*/
44	/* Private macros ------------------------------------------------------------*/
45
46	/** @addtogroup ADC_LL_Private_Macros
47	* @{
48	*/
49
50	/* Check of parameters for configuration of ADC hierarchical scope: */
51	/* common to several ADC instances. */
52	#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
53	( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
54	\|\| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
55	\|\| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
56	\|\| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
57	)
58
59	/* Check of parameters for configuration of ADC hierarchical scope: */
60	/* ADC instance. */
61	#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
62	( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
63	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
64	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
65	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
66	)
67
68	#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
69	( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
70	\|\| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
71	)
72
73	#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
74	( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
75	\|\| ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
76	)
77
78	#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
79	( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
80	\|\| ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
81	)
82
83	/* Check of parameters for configuration of ADC hierarchical scope: */
84	/* ADC group regular */
85	#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
86	( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
87	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
88	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
89	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
90	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
91	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
92	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
93	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
94	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
95	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
96	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
97	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
98	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \
99	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
100	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
101	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
102	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
103	)
104	#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
105	( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
106	\|\| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
107	)
108
109	#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
110	( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
111	\|\| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
112	\|\| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
113	)
114
115	#define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
116	( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
117	\|\| ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
118	)
119
120	#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
121	( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
122	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
123	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
124	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
125	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
126	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
127	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
128	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
129	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
130	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
131	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
132	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
133	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
134	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
135	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
136	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
137	)
138
139	#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
140	( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
141	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
142	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
143	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
144	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
145	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
146	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
147	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
148	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
149	)
150
151	/* Check of parameters for configuration of ADC hierarchical scope: */
152	/* ADC group injected */
153	#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
154	( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
155	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
156	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
157	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
158	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
159	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \
160	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
161	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \
162	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \
163	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
164	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
165	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
166	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
167	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
168	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \
169	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
170	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
171	)
172
173	#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
174	( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
175	\|\| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
176	\|\| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
177	)
178
179	#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
180	( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
181	\|\| ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
182	)
183
184	#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
185	( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
186	\|\| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
187	\|\| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
188	\|\| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
189	)
190
191	#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
192	( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
193	\|\| ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
194	)
195
196	#if defined(ADC_MULTIMODE_SUPPORT)
197	/* Check of parameters for configuration of ADC hierarchical scope: */
198	/* multimode. */
199	#if defined(ADC3)
200	#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
201	( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
202	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
203	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
204	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
205	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
206	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
207	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
208	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
209	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
210	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
211	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
212	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
213	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
214	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
215	)
216	#else
217	#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
218	( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
219	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
220	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
221	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
222	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
223	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
224	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
225	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
226	)
227	#endif
228
229	#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
230	( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
231	\|\| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
232	\|\| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
233	\|\| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
234	\|\| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
235	\|\| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
236	\|\| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
237	)
238
239	#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
240	( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
241	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
242	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
243	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
244	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
245	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
246	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
247	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
248	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
249	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
250	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
251	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
252	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
253	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
254	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
255	\|\| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
256	)
257
258	#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
259	( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
260	\|\| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
261	\|\| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
262	)
263
264	#endif /* ADC_MULTIMODE_SUPPORT */
265	/**
266	* @}
267	*/
268
269
270	/* Private function prototypes -----------------------------------------------*/
271
272	/* Exported functions --------------------------------------------------------*/
273	/** @addtogroup ADC_LL_Exported_Functions
274	* @{
275	*/
276
277	/** @addtogroup ADC_LL_EF_Init
278	* @{
279	*/
280
281	/**
282	* @brief De-initialize registers of all ADC instances belonging to
283	* the same ADC common instance to their default reset values.
284	* @param ADCxy_COMMON ADC common instance
285	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
286	* @retval An ErrorStatus enumeration value:
287	* - SUCCESS: ADC common registers are de-initialized
288	* - ERROR: not applicable
289	*/
290	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
291	{
292	/* Check the parameters */
293	assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
294
295
296	/* Force reset of ADC clock (core clock) */
297	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
298
299	/* Release reset of ADC clock (core clock) */
300	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
301
302	return SUCCESS;
303	}
304
305	/**
306	* @brief Initialize some features of ADC common parameters
307	* (all ADC instances belonging to the same ADC common instance)
308	* and multimode (for devices with several ADC instances available).
309	* @note The setting of ADC common parameters is conditioned to
310	* ADC instances state:
311	* All ADC instances belonging to the same ADC common instance
312	* must be disabled.
313	* @param ADCxy_COMMON ADC common instance
314	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
315	* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
316	* @retval An ErrorStatus enumeration value:
317	* - SUCCESS: ADC common registers are initialized
318	* - ERROR: ADC common registers are not initialized
319	*/
320	ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef ADCxy_COMMON, LL_ADC_CommonInitTypeDef ADC_CommonInitStruct)
321	{
322	ErrorStatus status = SUCCESS;
323
324	/* Check the parameters */
325	assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
326	assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
327
328	#if defined(ADC_MULTIMODE_SUPPORT)
329	assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
330	if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
331	{
332	assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
333	assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
334	}
335	#endif /* ADC_MULTIMODE_SUPPORT */
336
337	/* Note: Hardware constraint (refer to description of functions */
338	/* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
339	/* On this STM32 series, setting of these features is conditioned to */
340	/* ADC state: */
341	/* All ADC instances of the ADC common group must be disabled. */
342	if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
343	{
344	/* Configuration of ADC hierarchical scope: */
345	/* - common to several ADC */
346	/* (all ADC instances belonging to the same ADC common instance) */
347	/* - Set ADC clock (conversion clock) */
348	/* - multimode (if several ADC instances available on the */
349	/* selected device) */
350	/* - Set ADC multimode configuration */
351	/* - Set ADC multimode DMA transfer */
352	/* - Set ADC multimode: delay between 2 sampling phases */
353	#if defined(ADC_MULTIMODE_SUPPORT)
354	if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
355	{
356	MODIFY_REG(ADCxy_COMMON->CCR,
357	ADC_CCR_ADCPRE
358	\| ADC_CCR_MULTI
359	\| ADC_CCR_DMA
360	\| ADC_CCR_DDS
361	\| ADC_CCR_DELAY
362	,
363	ADC_CommonInitStruct->CommonClock
364	\| ADC_CommonInitStruct->Multimode
365	\| ADC_CommonInitStruct->MultiDMATransfer
366	\| ADC_CommonInitStruct->MultiTwoSamplingDelay
367	);
368	}
369	else
370	{
371	MODIFY_REG(ADCxy_COMMON->CCR,
372	ADC_CCR_ADCPRE
373	\| ADC_CCR_MULTI
374	\| ADC_CCR_DMA
375	\| ADC_CCR_DDS
376	\| ADC_CCR_DELAY
377	,
378	ADC_CommonInitStruct->CommonClock
379	\| LL_ADC_MULTI_INDEPENDENT
380	);
381	}
382	#else
383	LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
384	#endif
385	}
386	else
387	{
388	/* Initialization error: One or several ADC instances belonging to */
389	/* the same ADC common instance are not disabled. */
390	status = ERROR;
391	}
392
393	return status;
394	}
395
396	/**
397	* @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
398	* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
399	* whose fields will be set to default values.
400	* @retval None
401	*/
402	void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
403	{
404	/* Set ADC_CommonInitStruct fields to default values */
405	/* Set fields of ADC common */
406	/* (all ADC instances belonging to the same ADC common instance) */
407	ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
408
409	#if defined(ADC_MULTIMODE_SUPPORT)
410	/* Set fields of ADC multimode */
411	ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
412	ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
413	ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
414	#endif /* ADC_MULTIMODE_SUPPORT */
415	}
416
417	/**
418	* @brief De-initialize registers of the selected ADC instance
419	* to their default reset values.
420	* @note To reset all ADC instances quickly (perform a hard reset),
421	* use function @ref LL_ADC_CommonDeInit().
422	* @param ADCx ADC instance
423	* @retval An ErrorStatus enumeration value:
424	* - SUCCESS: ADC registers are de-initialized
425	* - ERROR: ADC registers are not de-initialized
426	*/
427	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
428	{
429	ErrorStatus status = SUCCESS;
430
431	/* Check the parameters */
432	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
433
434	/* Disable ADC instance if not already disabled. */
435	if(LL_ADC_IsEnabled(ADCx) == 1UL)
436	{
437	/* Set ADC group regular trigger source to SW start to ensure to not */
438	/* have an external trigger event occurring during the conversion stop */
439	/* ADC disable process. */
440	LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
441
442	/* Set ADC group injected trigger source to SW start to ensure to not */
443	/* have an external trigger event occurring during the conversion stop */
444	/* ADC disable process. */
445	LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
446
447	/* Disable the ADC instance */
448	LL_ADC_Disable(ADCx);
449	}
450
451	/* Check whether ADC state is compliant with expected state */
452	/* (hardware requirements of bits state to reset registers below) */
453	if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL)
454	{
455	/* ========== Reset ADC registers ========== */
456	/* Reset register SR */
457	CLEAR_BIT(ADCx->SR,
458	( LL_ADC_FLAG_STRT
459	\| LL_ADC_FLAG_JSTRT
460	\| LL_ADC_FLAG_EOCS
461	\| LL_ADC_FLAG_OVR
462	\| LL_ADC_FLAG_JEOS
463	\| LL_ADC_FLAG_AWD1 )
464	);
465
466	/* Reset register CR1 */
467	CLEAR_BIT(ADCx->CR1,
468	( ADC_CR1_OVRIE \| ADC_CR1_RES \| ADC_CR1_AWDEN
469	\| ADC_CR1_JAWDEN
470	\| ADC_CR1_DISCNUM \| ADC_CR1_JDISCEN \| ADC_CR1_DISCEN
471	\| ADC_CR1_JAUTO \| ADC_CR1_AWDSGL \| ADC_CR1_SCAN
472	\| ADC_CR1_JEOCIE \| ADC_CR1_AWDIE \| ADC_CR1_EOCIE
473	\| ADC_CR1_AWDCH )
474	);
475
476	/* Reset register CR2 */
477	CLEAR_BIT(ADCx->CR2,
478	( ADC_CR2_SWSTART \| ADC_CR2_EXTEN \| ADC_CR2_EXTSEL
479	\| ADC_CR2_JSWSTART \| ADC_CR2_JEXTEN \| ADC_CR2_JEXTSEL
480	\| ADC_CR2_ALIGN \| ADC_CR2_EOCS
481	\| ADC_CR2_DDS \| ADC_CR2_DMA
482	\| ADC_CR2_CONT \| ADC_CR2_ADON )
483	);
484
485	/* Reset register SMPR1 */
486	CLEAR_BIT(ADCx->SMPR1,
487	( ADC_SMPR1_SMP18 \| ADC_SMPR1_SMP17 \| ADC_SMPR1_SMP16
488	\| ADC_SMPR1_SMP15 \| ADC_SMPR1_SMP14 \| ADC_SMPR1_SMP13
489	\| ADC_SMPR1_SMP12 \| ADC_SMPR1_SMP11 \| ADC_SMPR1_SMP10)
490	);
491
492	/* Reset register SMPR2 */
493	CLEAR_BIT(ADCx->SMPR2,
494	( ADC_SMPR2_SMP9
495	\| ADC_SMPR2_SMP8 \| ADC_SMPR2_SMP7 \| ADC_SMPR2_SMP6
496	\| ADC_SMPR2_SMP5 \| ADC_SMPR2_SMP4 \| ADC_SMPR2_SMP3
497	\| ADC_SMPR2_SMP2 \| ADC_SMPR2_SMP1 \| ADC_SMPR2_SMP0)
498	);
499
500	/* Reset register JOFR1 */
501	CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
502	/* Reset register JOFR2 */
503	CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
504	/* Reset register JOFR3 */
505	CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
506	/* Reset register JOFR4 */
507	CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
508
509	/* Reset register HTR */
510	SET_BIT(ADCx->HTR, ADC_HTR_HT);
511	/* Reset register LTR */
512	CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
513
514	/* Reset register SQR1 */
515	CLEAR_BIT(ADCx->SQR1,
516	( ADC_SQR1_L
517	\| ADC_SQR1_SQ16
518	\| ADC_SQR1_SQ15 \| ADC_SQR1_SQ14 \| ADC_SQR1_SQ13)
519	);
520
521	/* Reset register SQR2 */
522	CLEAR_BIT(ADCx->SQR2,
523	( ADC_SQR2_SQ12 \| ADC_SQR2_SQ11 \| ADC_SQR2_SQ10
524	\| ADC_SQR2_SQ9 \| ADC_SQR2_SQ8 \| ADC_SQR2_SQ7)
525	);
526
527
528	/* Reset register JSQR */
529	CLEAR_BIT(ADCx->JSQR,
530	( ADC_JSQR_JL
531	\| ADC_JSQR_JSQ4 \| ADC_JSQR_JSQ3
532	\| ADC_JSQR_JSQ2 \| ADC_JSQR_JSQ1 )
533	);
534
535	/* Reset register DR */
536	/* bits in access mode read only, no direct reset applicable */
537
538	/* Reset registers JDR1, JDR2, JDR3, JDR4 */
539	/* bits in access mode read only, no direct reset applicable */
540
541	/* Reset register CCR */
542	CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE \| ADC_CCR_ADCPRE);
543	}
544
545	return status;
546	}
547
548	/**
549	* @brief Initialize some features of ADC instance.
550	* @note These parameters have an impact on ADC scope: ADC instance.
551	* Affects both group regular and group injected (availability
552	* of ADC group injected depends on STM32 families).
553	* Refer to corresponding unitary functions into
554	* @ref ADC_LL_EF_Configuration_ADC_Instance .
555	* @note The setting of these parameters by function @ref LL_ADC_Init()
556	* is conditioned to ADC state:
557	* ADC instance must be disabled.
558	* This condition is applied to all ADC features, for efficiency
559	* and compatibility over all STM32 families. However, the different
560	* features can be set under different ADC state conditions
561	* (setting possible with ADC enabled without conversion on going,
562	* ADC enabled with conversion on going, ...)
563	* Each feature can be updated afterwards with a unitary function
564	* and potentially with ADC in a different state than disabled,
565	* refer to description of each function for setting
566	* conditioned to ADC state.
567	* @note After using this function, some other features must be configured
568	* using LL unitary functions.
569	* The minimum configuration remaining to be done is:
570	* - Set ADC group regular or group injected sequencer:
571	* map channel on the selected sequencer rank.
572	* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
573	* - Set ADC channel sampling time
574	* Refer to function LL_ADC_SetChannelSamplingTime();
575	* @param ADCx ADC instance
576	* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
577	* @retval An ErrorStatus enumeration value:
578	* - SUCCESS: ADC registers are initialized
579	* - ERROR: ADC registers are not initialized
580	*/
581	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct)
582	{
583	ErrorStatus status = SUCCESS;
584
585	/* Check the parameters */
586	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
587
588	assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
589	assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
590	assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
591
592	/* Note: Hardware constraint (refer to description of this function): */
593	/* ADC instance must be disabled. */
594	if(LL_ADC_IsEnabled(ADCx) == 0UL)
595	{
596	/* Configuration of ADC hierarchical scope: */
597	/* - ADC instance */
598	/* - Set ADC data resolution */
599	/* - Set ADC conversion data alignment */
600	MODIFY_REG(ADCx->CR1,
601	ADC_CR1_RES
602	\| ADC_CR1_SCAN
603	,
604	ADC_InitStruct->Resolution
605	\| ADC_InitStruct->SequencersScanMode
606	);
607
608	MODIFY_REG(ADCx->CR2,
609	ADC_CR2_ALIGN
610	,
611	ADC_InitStruct->DataAlignment
612	);
613
614	}
615	else
616	{
617	/* Initialization error: ADC instance is not disabled. */
618	status = ERROR;
619	}
620	return status;
621	}
622
623	/**
624	* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
625	* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
626	* whose fields will be set to default values.
627	* @retval None
628	*/
629	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
630	{
631	/* Set ADC_InitStruct fields to default values */
632	/* Set fields of ADC instance */
633	ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
634	ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
635
636	/* Enable scan mode to have a generic behavior with ADC of other */
637	/* STM32 families, without this setting available: */
638	/* ADC group regular sequencer and ADC group injected sequencer depend */
639	/* only of their own configuration. */
640	ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
641
642	}
643
644	/**
645	* @brief Initialize some features of ADC group regular.
646	* @note These parameters have an impact on ADC scope: ADC group regular.
647	* Refer to corresponding unitary functions into
648	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
649	* (functions with prefix "REG").
650	* @note The setting of these parameters by function @ref LL_ADC_Init()
651	* is conditioned to ADC state:
652	* ADC instance must be disabled.
653	* This condition is applied to all ADC features, for efficiency
654	* and compatibility over all STM32 families. However, the different
655	* features can be set under different ADC state conditions
656	* (setting possible with ADC enabled without conversion on going,
657	* ADC enabled with conversion on going, ...)
658	* Each feature can be updated afterwards with a unitary function
659	* and potentially with ADC in a different state than disabled,
660	* refer to description of each function for setting
661	* conditioned to ADC state.
662	* @note After using this function, other features must be configured
663	* using LL unitary functions.
664	* The minimum configuration remaining to be done is:
665	* - Set ADC group regular or group injected sequencer:
666	* map channel on the selected sequencer rank.
667	* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
668	* - Set ADC channel sampling time
669	* Refer to function LL_ADC_SetChannelSamplingTime();
670	* @param ADCx ADC instance
671	* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
672	* @retval An ErrorStatus enumeration value:
673	* - SUCCESS: ADC registers are initialized
674	* - ERROR: ADC registers are not initialized
675	*/
676	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct)
677	{
678	ErrorStatus status = SUCCESS;
679
680	/* Check the parameters */
681	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
682	assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
683	assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
684	if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
685	{
686	assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
687	}
688	assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
689	assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
690
691	/* ADC group regular continuous mode and discontinuous mode */
692	/* can not be enabled simultenaeously */
693	assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
694	\|\| (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
695
696	/* Note: Hardware constraint (refer to description of this function): */
697	/* ADC instance must be disabled. */
698	if(LL_ADC_IsEnabled(ADCx) == 0UL)
699	{
700	/* Configuration of ADC hierarchical scope: */
701	/* - ADC group regular */
702	/* - Set ADC group regular trigger source */
703	/* - Set ADC group regular sequencer length */
704	/* - Set ADC group regular sequencer discontinuous mode */
705	/* - Set ADC group regular continuous mode */
706	/* - Set ADC group regular conversion data transfer: no transfer or */
707	/* transfer by DMA, and DMA requests mode */
708	/* Note: On this STM32 series, ADC trigger edge is set when starting */
709	/* ADC conversion. */
710	/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
711	if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
712	{
713	MODIFY_REG(ADCx->CR1,
714	ADC_CR1_DISCEN
715	\| ADC_CR1_DISCNUM
716	,
717	ADC_REG_InitStruct->SequencerDiscont
718	);
719	}
720	else
721	{
722	MODIFY_REG(ADCx->CR1,
723	ADC_CR1_DISCEN
724	\| ADC_CR1_DISCNUM
725	,
726	LL_ADC_REG_SEQ_DISCONT_DISABLE
727	);
728	}
729
730	MODIFY_REG(ADCx->CR2,
731	ADC_CR2_EXTSEL
732	\| ADC_CR2_EXTEN
733	\| ADC_CR2_CONT
734	\| ADC_CR2_DMA
735	\| ADC_CR2_DDS
736	,
737	(ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
738	\| ADC_REG_InitStruct->ContinuousMode
739	\| ADC_REG_InitStruct->DMATransfer
740	);
741
742	/* Set ADC group regular sequencer length and scan direction */
743	/* Note: Hardware constraint (refer to description of this function): */
744	/* Note: If ADC instance feature scan mode is disabled */
745	/* (refer to ADC instance initialization structure */
746	/* parameter @ref SequencersScanMode */
747	/* or function @ref LL_ADC_SetSequencersScanMode() ), */
748	/* this parameter is discarded. */
749	LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
750	}
751	else
752	{
753	/* Initialization error: ADC instance is not disabled. */
754	status = ERROR;
755	}
756	return status;
757	}
758
759	/**
760	* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
761	* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
762	* whose fields will be set to default values.
763	* @retval None
764	*/
765	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
766	{
767	/* Set ADC_REG_InitStruct fields to default values */
768	/* Set fields of ADC group regular */
769	/* Note: On this STM32 series, ADC trigger edge is set when starting */
770	/* ADC conversion. */
771	/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
772	ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
773	ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
774	ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
775	ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
776	ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
777	}
778
779	/**
780	* @brief Initialize some features of ADC group injected.
781	* @note These parameters have an impact on ADC scope: ADC group injected.
782	* Refer to corresponding unitary functions into
783	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
784	* (functions with prefix "INJ").
785	* @note The setting of these parameters by function @ref LL_ADC_Init()
786	* is conditioned to ADC state:
787	* ADC instance must be disabled.
788	* This condition is applied to all ADC features, for efficiency
789	* and compatibility over all STM32 families. However, the different
790	* features can be set under different ADC state conditions
791	* (setting possible with ADC enabled without conversion on going,
792	* ADC enabled with conversion on going, ...)
793	* Each feature can be updated afterwards with a unitary function
794	* and potentially with ADC in a different state than disabled,
795	* refer to description of each function for setting
796	* conditioned to ADC state.
797	* @note After using this function, other features must be configured
798	* using LL unitary functions.
799	* The minimum configuration remaining to be done is:
800	* - Set ADC group injected sequencer:
801	* map channel on the selected sequencer rank.
802	* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
803	* - Set ADC channel sampling time
804	* Refer to function LL_ADC_SetChannelSamplingTime();
805	* @param ADCx ADC instance
806	* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
807	* @retval An ErrorStatus enumeration value:
808	* - SUCCESS: ADC registers are initialized
809	* - ERROR: ADC registers are not initialized
810	*/
811	ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef ADCx, LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct)
812	{
813	ErrorStatus status = SUCCESS;
814
815	/* Check the parameters */
816	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
817	assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
818	assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
819	if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
820	{
821	assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
822	}
823	assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
824
825	/* Note: Hardware constraint (refer to description of this function): */
826	/* ADC instance must be disabled. */
827	if(LL_ADC_IsEnabled(ADCx) == 0UL)
828	{
829	/* Configuration of ADC hierarchical scope: */
830	/* - ADC group injected */
831	/* - Set ADC group injected trigger source */
832	/* - Set ADC group injected sequencer length */
833	/* - Set ADC group injected sequencer discontinuous mode */
834	/* - Set ADC group injected conversion trigger: independent or */
835	/* from ADC group regular */
836	/* Note: On this STM32 series, ADC trigger edge is set when starting */
837	/* ADC conversion. */
838	/* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
839	if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
840	{
841	MODIFY_REG(ADCx->CR1,
842	ADC_CR1_JDISCEN
843	\| ADC_CR1_JAUTO
844	,
845	ADC_INJ_InitStruct->SequencerDiscont
846	\| ADC_INJ_InitStruct->TrigAuto
847	);
848	}
849	else
850	{
851	MODIFY_REG(ADCx->CR1,
852	ADC_CR1_JDISCEN
853	\| ADC_CR1_JAUTO
854	,
855	LL_ADC_REG_SEQ_DISCONT_DISABLE
856	\| ADC_INJ_InitStruct->TrigAuto
857	);
858	}
859
860	MODIFY_REG(ADCx->CR2,
861	ADC_CR2_JEXTSEL
862	\| ADC_CR2_JEXTEN
863	,
864	(ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
865	);
866
867	/* Note: Hardware constraint (refer to description of this function): */
868	/* Note: If ADC instance feature scan mode is disabled */
869	/* (refer to ADC instance initialization structure */
870	/* parameter @ref SequencersScanMode */
871	/* or function @ref LL_ADC_SetSequencersScanMode() ), */
872	/* this parameter is discarded. */
873	LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
874	}
875	else
876	{
877	/* Initialization error: ADC instance is not disabled. */
878	status = ERROR;
879	}
880	return status;
881	}
882
883	/**
884	* @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
885	* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
886	* whose fields will be set to default values.
887	* @retval None
888	*/
889	void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
890	{
891	/* Set ADC_INJ_InitStruct fields to default values */
892	/* Set fields of ADC group injected */
893	ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
894	ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
895	ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
896	ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
897	}
898
899	/**
900	* @}
901	*/
902
903	/**
904	* @}
905	*/
906
907	/**
908	* @}
909	*/
910
911	#endif /* ADC1 \|\| ADC2 \|\| ADC3 */
912
913	/**
914	* @}
915	*/
916
917	#endif /* USE_FULL_LL_DRIVER */
918
919	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c

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