| 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_ll_dma.c
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| 4 | * @author MCD Application Team
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| 5 | * @brief DMA LL module driver.
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| 6 | ******************************************************************************
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| 7 | * @attention
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| 8 | *
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| 9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics.
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| 10 | * All rights reserved.</center></h2>
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| 11 | *
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| 12 | * This software component is licensed by ST under BSD 3-Clause license,
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| 13 | * the "License"; You may not use this file except in compliance with the
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| 14 | * License. You may obtain a copy of the License at:
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| 15 | * opensource.org/licenses/BSD-3-Clause
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| 16 | *
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| 17 | ******************************************************************************
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| 18 | */
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| 19 | #if defined(USE_FULL_LL_DRIVER)
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| 20 |
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| 21 | /* Includes ------------------------------------------------------------------*/
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| 22 | #include "stm32f4xx_ll_dma.h"
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| 23 | #include "stm32f4xx_ll_bus.h"
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| 24 | #ifdef USE_FULL_ASSERT
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| 25 | #include "stm32_assert.h"
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| 26 | #else
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| 27 | #define assert_param(expr) ((void)0U)
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| 28 | #endif
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| 29 |
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| 30 | /** @addtogroup STM32F4xx_LL_Driver
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| 31 | * @{
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| 32 | */
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| 33 |
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| 34 | #if defined (DMA1) || defined (DMA2)
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| 35 |
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| 36 | /** @defgroup DMA_LL DMA
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| 37 | * @{
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| 38 | */
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| 39 |
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| 40 | /* Private types -------------------------------------------------------------*/
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| 41 | /* Private variables ---------------------------------------------------------*/
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| 42 | /* Private constants ---------------------------------------------------------*/
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| 43 | /* Private macros ------------------------------------------------------------*/
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| 44 | /** @addtogroup DMA_LL_Private_Macros
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| 45 | * @{
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| 46 | */
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| 47 | #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
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| 48 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
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| 49 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
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| 50 |
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| 51 | #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
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| 52 | ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
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| 53 | ((__VALUE__) == LL_DMA_MODE_PFCTRL))
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| 54 |
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| 55 | #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
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| 56 | ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
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| 57 |
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| 58 | #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
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| 59 | ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
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| 60 |
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| 61 | #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
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| 62 | ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
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| 63 | ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
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| 64 |
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| 65 | #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
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| 66 | ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
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| 67 | ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
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| 68 |
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| 69 | #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
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| 70 |
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| 71 | #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
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| 72 | ((__VALUE__) == LL_DMA_CHANNEL_1) || \
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| 73 | ((__VALUE__) == LL_DMA_CHANNEL_2) || \
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| 74 | ((__VALUE__) == LL_DMA_CHANNEL_3) || \
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| 75 | ((__VALUE__) == LL_DMA_CHANNEL_4) || \
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| 76 | ((__VALUE__) == LL_DMA_CHANNEL_5) || \
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| 77 | ((__VALUE__) == LL_DMA_CHANNEL_6) || \
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| 78 | ((__VALUE__) == LL_DMA_CHANNEL_7))
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| 79 |
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| 80 | #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
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| 81 | ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
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| 82 | ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
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| 83 | ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
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| 84 |
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| 85 | #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
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| 86 | (((STREAM) == LL_DMA_STREAM_0) || \
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| 87 | ((STREAM) == LL_DMA_STREAM_1) || \
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| 88 | ((STREAM) == LL_DMA_STREAM_2) || \
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| 89 | ((STREAM) == LL_DMA_STREAM_3) || \
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| 90 | ((STREAM) == LL_DMA_STREAM_4) || \
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| 91 | ((STREAM) == LL_DMA_STREAM_5) || \
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| 92 | ((STREAM) == LL_DMA_STREAM_6) || \
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| 93 | ((STREAM) == LL_DMA_STREAM_7) || \
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| 94 | ((STREAM) == LL_DMA_STREAM_ALL))) ||\
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| 95 | (((INSTANCE) == DMA2) && \
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| 96 | (((STREAM) == LL_DMA_STREAM_0) || \
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| 97 | ((STREAM) == LL_DMA_STREAM_1) || \
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| 98 | ((STREAM) == LL_DMA_STREAM_2) || \
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| 99 | ((STREAM) == LL_DMA_STREAM_3) || \
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| 100 | ((STREAM) == LL_DMA_STREAM_4) || \
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| 101 | ((STREAM) == LL_DMA_STREAM_5) || \
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| 102 | ((STREAM) == LL_DMA_STREAM_6) || \
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| 103 | ((STREAM) == LL_DMA_STREAM_7) || \
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| 104 | ((STREAM) == LL_DMA_STREAM_ALL))))
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| 105 |
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| 106 | #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
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| 107 | ((STATE) == LL_DMA_FIFOMODE_ENABLE))
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| 108 |
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| 109 | #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
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| 110 | ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
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| 111 | ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
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| 112 | ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
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| 113 |
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| 114 | #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
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| 115 | ((BURST) == LL_DMA_MBURST_INC4) || \
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| 116 | ((BURST) == LL_DMA_MBURST_INC8) || \
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| 117 | ((BURST) == LL_DMA_MBURST_INC16))
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| 118 |
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| 119 | #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
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| 120 | ((BURST) == LL_DMA_PBURST_INC4) || \
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| 121 | ((BURST) == LL_DMA_PBURST_INC8) || \
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| 122 | ((BURST) == LL_DMA_PBURST_INC16))
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| 123 |
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| 124 | /**
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| 125 | * @}
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| 126 | */
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| 127 |
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| 128 | /* Private function prototypes -----------------------------------------------*/
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| 129 |
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| 130 | /* Exported functions --------------------------------------------------------*/
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| 131 | /** @addtogroup DMA_LL_Exported_Functions
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| 132 | * @{
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| 133 | */
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| 134 |
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| 135 | /** @addtogroup DMA_LL_EF_Init
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| 136 | * @{
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| 137 | */
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| 138 |
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| 139 | /**
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| 140 | * @brief De-initialize the DMA registers to their default reset values.
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| 141 | * @param DMAx DMAx Instance
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| 142 | * @param Stream This parameter can be one of the following values:
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| 143 | * @arg @ref LL_DMA_STREAM_0
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| 144 | * @arg @ref LL_DMA_STREAM_1
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| 145 | * @arg @ref LL_DMA_STREAM_2
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| 146 | * @arg @ref LL_DMA_STREAM_3
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| 147 | * @arg @ref LL_DMA_STREAM_4
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| 148 | * @arg @ref LL_DMA_STREAM_5
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| 149 | * @arg @ref LL_DMA_STREAM_6
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| 150 | * @arg @ref LL_DMA_STREAM_7
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| 151 | * @arg @ref LL_DMA_STREAM_ALL
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| 152 | * @retval An ErrorStatus enumeration value:
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| 153 | * - SUCCESS: DMA registers are de-initialized
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| 154 | * - ERROR: DMA registers are not de-initialized
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| 155 | */
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| 156 | uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
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| 157 | {
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| 158 | DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
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| 159 | ErrorStatus status = SUCCESS;
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| 160 |
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| 161 | /* Check the DMA Instance DMAx and Stream parameters*/
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| 162 | assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
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| 163 |
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| 164 | if (Stream == LL_DMA_STREAM_ALL)
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| 165 | {
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| 166 | if (DMAx == DMA1)
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| 167 | {
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| 168 | /* Force reset of DMA clock */
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| 169 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
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| 170 |
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| 171 | /* Release reset of DMA clock */
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| 172 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
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| 173 | }
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| 174 | else if (DMAx == DMA2)
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| 175 | {
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| 176 | /* Force reset of DMA clock */
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| 177 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
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| 178 |
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| 179 | /* Release reset of DMA clock */
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| 180 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
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| 181 | }
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| 182 | else
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| 183 | {
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| 184 | status = ERROR;
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| 185 | }
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| 186 | }
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| 187 | else
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| 188 | {
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| 189 | /* Disable the selected Stream */
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| 190 | LL_DMA_DisableStream(DMAx,Stream);
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| 191 |
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| 192 | /* Get the DMA Stream Instance */
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| 193 | tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
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| 194 |
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| 195 | /* Reset DMAx_Streamy configuration register */
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| 196 | LL_DMA_WriteReg(tmp, CR, 0U);
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| 197 |
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| 198 | /* Reset DMAx_Streamy remaining bytes register */
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| 199 | LL_DMA_WriteReg(tmp, NDTR, 0U);
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| 200 |
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| 201 | /* Reset DMAx_Streamy peripheral address register */
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| 202 | LL_DMA_WriteReg(tmp, PAR, 0U);
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| 203 |
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| 204 | /* Reset DMAx_Streamy memory address register */
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| 205 | LL_DMA_WriteReg(tmp, M0AR, 0U);
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| 206 |
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| 207 | /* Reset DMAx_Streamy memory address register */
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| 208 | LL_DMA_WriteReg(tmp, M1AR, 0U);
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| 209 |
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| 210 | /* Reset DMAx_Streamy FIFO control register */
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| 211 | LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
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| 212 |
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| 213 | /* Reset Channel register field for DMAx Stream*/
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| 214 | LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
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| 215 |
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| 216 | if(Stream == LL_DMA_STREAM_0)
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| 217 | {
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| 218 | /* Reset the Stream0 pending flags */
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| 219 | DMAx->LIFCR = 0x0000003FU;
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| 220 | }
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| 221 | else if(Stream == LL_DMA_STREAM_1)
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| 222 | {
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| 223 | /* Reset the Stream1 pending flags */
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| 224 | DMAx->LIFCR = 0x00000F40U;
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| 225 | }
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| 226 | else if(Stream == LL_DMA_STREAM_2)
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| 227 | {
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| 228 | /* Reset the Stream2 pending flags */
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| 229 | DMAx->LIFCR = 0x003F0000U;
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| 230 | }
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| 231 | else if(Stream == LL_DMA_STREAM_3)
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| 232 | {
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| 233 | /* Reset the Stream3 pending flags */
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| 234 | DMAx->LIFCR = 0x0F400000U;
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| 235 | }
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| 236 | else if(Stream == LL_DMA_STREAM_4)
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| 237 | {
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| 238 | /* Reset the Stream4 pending flags */
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| 239 | DMAx->HIFCR = 0x0000003FU;
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| 240 | }
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| 241 | else if(Stream == LL_DMA_STREAM_5)
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| 242 | {
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| 243 | /* Reset the Stream5 pending flags */
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| 244 | DMAx->HIFCR = 0x00000F40U;
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| 245 | }
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| 246 | else if(Stream == LL_DMA_STREAM_6)
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| 247 | {
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| 248 | /* Reset the Stream6 pending flags */
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| 249 | DMAx->HIFCR = 0x003F0000U;
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| 250 | }
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| 251 | else if(Stream == LL_DMA_STREAM_7)
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| 252 | {
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| 253 | /* Reset the Stream7 pending flags */
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| 254 | DMAx->HIFCR = 0x0F400000U;
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| 255 | }
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| 256 | else
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| 257 | {
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| 258 | status = ERROR;
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| 259 | }
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| 260 | }
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| 261 |
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| 262 | return status;
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| 263 | }
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| 264 |
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| 265 | /**
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| 266 | * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
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| 267 | * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
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| 268 | * @arg @ref __LL_DMA_GET_INSTANCE
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| 269 | * @arg @ref __LL_DMA_GET_STREAM
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| 270 | * @param DMAx DMAx Instance
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| 271 | * @param Stream This parameter can be one of the following values:
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| 272 | * @arg @ref LL_DMA_STREAM_0
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| 273 | * @arg @ref LL_DMA_STREAM_1
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| 274 | * @arg @ref LL_DMA_STREAM_2
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| 275 | * @arg @ref LL_DMA_STREAM_3
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| 276 | * @arg @ref LL_DMA_STREAM_4
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| 277 | * @arg @ref LL_DMA_STREAM_5
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| 278 | * @arg @ref LL_DMA_STREAM_6
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| 279 | * @arg @ref LL_DMA_STREAM_7
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| 280 | * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
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| 281 | * @retval An ErrorStatus enumeration value:
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| 282 | * - SUCCESS: DMA registers are initialized
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| 283 | * - ERROR: Not applicable
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| 284 | */
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| 285 | uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
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| 286 | {
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| 287 | /* Check the DMA Instance DMAx and Stream parameters*/
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| 288 | assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
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| 289 |
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| 290 | /* Check the DMA parameters from DMA_InitStruct */
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| 291 | assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
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| 292 | assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
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| 293 | assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
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| 294 | assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
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| 295 | assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
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| 296 | assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
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| 297 | assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
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| 298 | assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
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| 299 | assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
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| 300 | assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
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| 301 | /* Check the memory burst, peripheral burst and FIFO threshold parameters only
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| 302 | when FIFO mode is enabled */
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| 303 | if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
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| 304 | {
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| 305 | assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
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| 306 | assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
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| 307 | assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
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| 308 | }
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| 309 |
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| 310 | /*---------------------------- DMAx SxCR Configuration ------------------------
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| 311 | * Configure DMAx_Streamy: data transfer direction, data transfer mode,
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| 312 | * peripheral and memory increment mode,
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| 313 | * data size alignment and priority level with parameters :
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| 314 | * - Direction: DMA_SxCR_DIR[1:0] bits
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| 315 | * - Mode: DMA_SxCR_CIRC bit
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| 316 | * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
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| 317 | * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
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| 318 | * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
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| 319 | * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
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| 320 | * - Priority: DMA_SxCR_PL[1:0] bits
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| 321 | */
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| 322 | LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
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| 323 | DMA_InitStruct->Mode | \
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| 324 | DMA_InitStruct->PeriphOrM2MSrcIncMode | \
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| 325 | DMA_InitStruct->MemoryOrM2MDstIncMode | \
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| 326 | DMA_InitStruct->PeriphOrM2MSrcDataSize | \
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| 327 | DMA_InitStruct->MemoryOrM2MDstDataSize | \
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| 328 | DMA_InitStruct->Priority
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| 329 | );
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| 330 |
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| 331 | if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
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| 332 | {
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| 333 | /*---------------------------- DMAx SxFCR Configuration ------------------------
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| 334 | * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
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| 335 | * - FIFOMode: DMA_SxFCR_DMDIS bit
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| 336 | * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
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| 337 | */
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| 338 | LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
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| 339 |
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| 340 | /*---------------------------- DMAx SxCR Configuration --------------------------
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| 341 | * Configure DMAx_Streamy: memory burst transfer with parameters :
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| 342 | * - MemBurst: DMA_SxCR_MBURST[1:0] bits
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| 343 | */
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| 344 | LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
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| 345 |
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| 346 | /*---------------------------- DMAx SxCR Configuration --------------------------
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| 347 | * Configure DMAx_Streamy: peripheral burst transfer with parameters :
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| 348 | * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
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| 349 | */
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| 350 | LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
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| 351 | }
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| 352 |
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| 353 | /*-------------------------- DMAx SxM0AR Configuration --------------------------
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| 354 | * Configure the memory or destination base address with parameter :
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| 355 | * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
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| 356 | */
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| 357 | LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
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| 358 |
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| 359 | /*-------------------------- DMAx SxPAR Configuration ---------------------------
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| 360 | * Configure the peripheral or source base address with parameter :
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| 361 | * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
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| 362 | */
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| 363 | LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
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| 364 |
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| 365 | /*--------------------------- DMAx SxNDTR Configuration -------------------------
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| 366 | * Configure the peripheral base address with parameter :
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| 367 | * - NbData: DMA_SxNDT[15:0] bits
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| 368 | */
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| 369 | LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
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| 370 |
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| 371 | /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
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| 372 | * Configure the peripheral base address with parameter :
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| 373 | * - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits
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| 374 | */
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| 375 | LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
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| 376 |
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| 377 | return SUCCESS;
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| 378 | }
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| 379 |
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| 380 | /**
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| 381 | * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
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| 382 | * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
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| 383 | * @retval None
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| 384 | */
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| 385 | void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
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| 386 | {
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| 387 | /* Set DMA_InitStruct fields to default values */
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| 388 | DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
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| 389 | DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
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| 390 | DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
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| 391 | DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
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| 392 | DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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| 393 | DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
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| 394 | DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
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| 395 | DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
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| 396 | DMA_InitStruct->NbData = 0x00000000U;
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| 397 | DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
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| 398 | DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
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| 399 | DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
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| 400 | DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
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| 401 | DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
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| 402 | DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
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| 403 | }
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| 404 |
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| 405 | /**
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| 406 | * @}
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| 407 | */
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| 408 |
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| 409 | /**
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| 410 | * @}
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| 411 | */
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| 412 |
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| 413 | /**
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| 414 | * @}
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| 415 | */
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| 416 |
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| 417 | #endif /* DMA1 || DMA2 */
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| 418 |
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| 419 | /**
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| 420 | * @}
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| 421 | */
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| 422 |
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| 423 | #endif /* USE_FULL_LL_DRIVER */
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| 424 |
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| 425 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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