source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c

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1/**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### FMC peripheral features #####
16 ==============================================================================
17 [..] The Flexible memory controller (FMC) includes three memory controllers:
18 (+) The NOR/PSRAM memory controller
19 (+) The NAND/PC Card memory controller
20 (+) The Synchronous DRAM (SDRAM) controller
21
22 [..] The FMC functional block makes the interface with synchronous and asynchronous static
23 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
24 (+) to translate AHB transactions into the appropriate external device protocol
25 (+) to meet the access time requirements of the external memory devices
26
27 [..] All external memories share the addresses, data and control signals with the controller.
28 Each external device is accessed by means of a unique Chip Select. The FMC performs
29 only one access at a time to an external device.
30 The main features of the FMC controller are the following:
31 (+) Interface with static-memory mapped devices including:
32 (++) Static random access memory (SRAM)
33 (++) Read-only memory (ROM)
34 (++) NOR Flash memory/OneNAND Flash memory
35 (++) PSRAM (4 memory banks)
36 (++) 16-bit PC Card compatible devices
37 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
38 data
39 (+) Interface with synchronous DRAM (SDRAM) memories
40 (+) Independent Chip Select control for each memory bank
41 (+) Independent configuration for each memory bank
42
43 @endverbatim
44 ******************************************************************************
45 * @attention
46 *
47 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
48 * All rights reserved.</center></h2>
49 *
50 * This software component is licensed by ST under BSD 3-Clause license,
51 * the "License"; You may not use this file except in compliance with the
52 * License. You may obtain a copy of the License at:
53 * opensource.org/licenses/BSD-3-Clause
54 *
55 ******************************************************************************
56 */
57
58/* Includes ------------------------------------------------------------------*/
59#include "stm32f4xx_hal.h"
60
61/** @addtogroup STM32F4xx_HAL_Driver
62 * @{
63 */
64
65/** @defgroup FMC_LL FMC Low Layer
66 * @brief FMC driver modules
67 * @{
68 */
69
70#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
71
72#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
73
74/* Private typedef -----------------------------------------------------------*/
75/* Private define ------------------------------------------------------------*/
76/* Private macro -------------------------------------------------------------*/
77/* Private variables ---------------------------------------------------------*/
78/* Private function prototypes -----------------------------------------------*/
79/* Private functions ---------------------------------------------------------*/
80/** @addtogroup FMC_LL_Private_Functions
81 * @{
82 */
83
84/** @addtogroup FMC_LL_NORSRAM
85 * @brief NORSRAM Controller functions
86 *
87 @verbatim
88 ==============================================================================
89 ##### How to use NORSRAM device driver #####
90 ==============================================================================
91
92 [..]
93 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
94 to run the NORSRAM external devices.
95
96 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
97 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
98 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
99 (+) FMC NORSRAM bank extended timing configuration using the function
100 FMC_NORSRAM_Extended_Timing_Init()
101 (+) FMC NORSRAM bank enable/disable write operation using the functions
102 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
103
104
105@endverbatim
106 * @{
107 */
108
109/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1
110 * @brief Initialization and Configuration functions
111 *
112 @verbatim
113 ==============================================================================
114 ##### Initialization and de_initialization functions #####
115 ==============================================================================
116 [..]
117 This section provides functions allowing to:
118 (+) Initialize and configure the FMC NORSRAM interface
119 (+) De-initialize the FMC NORSRAM interface
120 (+) Configure the FMC clock and associated GPIOs
121
122@endverbatim
123 * @{
124 */
125
126/**
127 * @brief Initialize the FMC_NORSRAM device according to the specified
128 * control parameters in the FMC_NORSRAM_InitTypeDef
129 * @param Device Pointer to NORSRAM device instance
130 * @param Init Pointer to NORSRAM Initialization structure
131 * @retval HAL status
132 */
133HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
134{
135 uint32_t tmpr = 0U;
136
137 /* Check the parameters */
138 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
139 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
140 assert_param(IS_FMC_MUX(Init->DataAddressMux));
141 assert_param(IS_FMC_MEMORY(Init->MemoryType));
142 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
143 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
144 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
145#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
146 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
147#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
148 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
149 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
150 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
151 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
152 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
153 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
154 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
155 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
156#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
157 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
158#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
159
160 /* Get the BTCR register value */
161 tmpr = Device->BTCR[Init->NSBank];
162
163#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
164 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
165 WAITEN, EXTMOD, ASYNCWAIT, CPSIZE, CBURSTRW and CCLKEN bits */
166 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
167 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
168 FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \
169 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
170 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CPSIZE | FMC_BCR1_CBURSTRW | \
171 FMC_BCR1_CCLKEN));
172
173 /* Set NORSRAM device control parameters */
174 tmpr |= (uint32_t)(Init->DataAddressMux |\
175 Init->MemoryType |\
176 Init->MemoryDataWidth |\
177 Init->BurstAccessMode |\
178 Init->WaitSignalPolarity |\
179 Init->WrapMode |\
180 Init->WaitSignalActive |\
181 Init->WriteOperation |\
182 Init->WaitSignal |\
183 Init->ExtendedMode |\
184 Init->AsynchronousWait |\
185 Init->PageSize |\
186 Init->WriteBurst |\
187 Init->ContinuousClock);
188#else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
189 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN,
190 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */
191 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
192 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
193 FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \
194 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
195 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \
196 FMC_BCR1_WFDIS));
197
198 /* Set NORSRAM device control parameters */
199 tmpr |= (uint32_t)(Init->DataAddressMux |\
200 Init->MemoryType |\
201 Init->MemoryDataWidth |\
202 Init->BurstAccessMode |\
203 Init->WaitSignalPolarity |\
204 Init->WaitSignalActive |\
205 Init->WriteOperation |\
206 Init->WaitSignal |\
207 Init->ExtendedMode |\
208 Init->AsynchronousWait |\
209 Init->WriteBurst |\
210 Init->ContinuousClock |\
211 Init->PageSize |\
212 Init->WriteFifo);
213#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
214
215 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
216 {
217 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
218 }
219
220 Device->BTCR[Init->NSBank] = tmpr;
221
222 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
223 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
224 {
225 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
226 }
227
228#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
229 if(Init->NSBank != FMC_NORSRAM_BANK1)
230 {
231 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
232 }
233#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
234
235 return HAL_OK;
236}
237
238/**
239 * @brief DeInitialize the FMC_NORSRAM peripheral
240 * @param Device Pointer to NORSRAM device instance
241 * @param ExDevice Pointer to NORSRAM extended mode device instance
242 * @param Bank NORSRAM bank number
243 * @retval HAL status
244 */
245HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
246{
247 /* Check the parameters */
248 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
249 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
250 assert_param(IS_FMC_NORSRAM_BANK(Bank));
251
252 /* Disable the FMC_NORSRAM device */
253 __FMC_NORSRAM_DISABLE(Device, Bank);
254
255 /* De-initialize the FMC_NORSRAM device */
256 /* FMC_NORSRAM_BANK1 */
257 if(Bank == FMC_NORSRAM_BANK1)
258 {
259 Device->BTCR[Bank] = 0x000030DBU;
260 }
261 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
262 else
263 {
264 Device->BTCR[Bank] = 0x000030D2U;
265 }
266
267 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
268 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
269
270 return HAL_OK;
271}
272
273/**
274 * @brief Initialize the FMC_NORSRAM Timing according to the specified
275 * parameters in the FMC_NORSRAM_TimingTypeDef
276 * @param Device Pointer to NORSRAM device instance
277 * @param Timing Pointer to NORSRAM Timing structure
278 * @param Bank NORSRAM bank number
279 * @retval HAL status
280 */
281HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
282{
283 uint32_t tmpr = 0U;
284
285 /* Check the parameters */
286 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
287 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
288 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
289 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
290 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
291 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
292 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
293 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
294 assert_param(IS_FMC_NORSRAM_BANK(Bank));
295
296 /* Get the BTCR register value */
297 tmpr = Device->BTCR[Bank + 1U];
298
299 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
300 tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
301 FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
302 FMC_BTR1_ACCMOD));
303
304 /* Set FMC_NORSRAM device timing parameters */
305 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
306 ((Timing->AddressHoldTime) << 4U) |\
307 ((Timing->DataSetupTime) << 8U) |\
308 ((Timing->BusTurnAroundDuration) << 16U) |\
309 (((Timing->CLKDivision) - 1U) << 20U) |\
310 (((Timing->DataLatency) - 2U) << 24U) |\
311 (Timing->AccessMode));
312
313 Device->BTCR[Bank + 1U] = tmpr;
314
315 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
316 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
317 {
318 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U));
319 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << 20U);
320 Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpr;
321 }
322
323 return HAL_OK;
324}
325
326/**
327 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
328 * parameters in the FMC_NORSRAM_TimingTypeDef
329 * @param Device Pointer to NORSRAM device instance
330 * @param Timing Pointer to NORSRAM Timing structure
331 * @param Bank NORSRAM bank number
332 * @retval HAL status
333 */
334HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
335{
336 uint32_t tmpr = 0U;
337
338 /* Check the parameters */
339 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
340
341 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
342 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
343 {
344 /* Check the parameters */
345 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
346 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
347 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
348 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
349 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
350 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
351 assert_param(IS_FMC_NORSRAM_BANK(Bank));
352
353 /* Get the BWTR register value */
354 tmpr = Device->BWTR[Bank];
355
356 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
357 tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
358 FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
359
360 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
361 ((Timing->AddressHoldTime) << 4U) |\
362 ((Timing->DataSetupTime) << 8U) |\
363 ((Timing->BusTurnAroundDuration) << 16U) |\
364 (Timing->AccessMode));
365
366 Device->BWTR[Bank] = tmpr;
367 }
368 else
369 {
370 Device->BWTR[Bank] = 0x0FFFFFFFU;
371 }
372
373 return HAL_OK;
374}
375/**
376 * @}
377 */
378
379/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
380 * @brief management functions
381 *
382@verbatim
383 ==============================================================================
384 ##### FMC_NORSRAM Control functions #####
385 ==============================================================================
386 [..]
387 This subsection provides a set of functions allowing to control dynamically
388 the FMC NORSRAM interface.
389
390@endverbatim
391 * @{
392 */
393/**
394 * @brief Enables dynamically FMC_NORSRAM write operation.
395 * @param Device Pointer to NORSRAM device instance
396 * @param Bank NORSRAM bank number
397 * @retval HAL status
398 */
399HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
400{
401 /* Check the parameters */
402 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
403 assert_param(IS_FMC_NORSRAM_BANK(Bank));
404
405 /* Enable write operation */
406 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
407
408 return HAL_OK;
409}
410
411/**
412 * @brief Disables dynamically FMC_NORSRAM write operation.
413 * @param Device Pointer to NORSRAM device instance
414 * @param Bank NORSRAM bank number
415 * @retval HAL status
416 */
417HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
418{
419 /* Check the parameters */
420 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
421 assert_param(IS_FMC_NORSRAM_BANK(Bank));
422
423 /* Disable write operation */
424 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
425
426 return HAL_OK;
427}
428
429/**
430 * @}
431 */
432
433/**
434 * @}
435 */
436
437/** @addtogroup FMC_LL_NAND
438 * @brief NAND Controller functions
439 *
440 @verbatim
441 ==============================================================================
442 ##### How to use NAND device driver #####
443 ==============================================================================
444 [..]
445 This driver contains a set of APIs to interface with the FMC NAND banks in order
446 to run the NAND external devices.
447
448 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
449 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
450 (+) FMC NAND bank common space timing configuration using the function
451 FMC_NAND_CommonSpace_Timing_Init()
452 (+) FMC NAND bank attribute space timing configuration using the function
453 FMC_NAND_AttributeSpace_Timing_Init()
454 (+) FMC NAND bank enable/disable ECC correction feature using the functions
455 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
456 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
457
458@endverbatim
459 * @{
460 */
461
462#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
463/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
464 * @brief Initialization and Configuration functions
465 *
466@verbatim
467 ==============================================================================
468 ##### Initialization and de_initialization functions #####
469 ==============================================================================
470 [..]
471 This section provides functions allowing to:
472 (+) Initialize and configure the FMC NAND interface
473 (+) De-initialize the FMC NAND interface
474 (+) Configure the FMC clock and associated GPIOs
475
476@endverbatim
477 * @{
478 */
479
480/**
481 * @brief Initializes the FMC_NAND device according to the specified
482 * control parameters in the FMC_NAND_HandleTypeDef
483 * @param Device Pointer to NAND device instance
484 * @param Init Pointer to NAND Initialization structure
485 * @retval HAL status
486 */
487HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
488{
489 uint32_t tmpr = 0U;
490
491 /* Check the parameters */
492 assert_param(IS_FMC_NAND_DEVICE(Device));
493 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
494 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
495 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
496 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
497 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
498 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
499 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
500
501 /* Get the NAND bank register value */
502 tmpr = Device->PCR;
503
504 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
505 tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
506 FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
507 FMC_PCR_TAR | FMC_PCR_ECCPS));
508
509 /* Set NAND device control parameters */
510 tmpr |= (uint32_t)(Init->Waitfeature |\
511 FMC_PCR_MEMORY_TYPE_NAND |\
512 Init->MemoryDataWidth |\
513 Init->EccComputation |\
514 Init->ECCPageSize |\
515 ((Init->TCLRSetupTime) << 9U) |\
516 ((Init->TARSetupTime) << 13U));
517
518 /* NAND bank registers configuration */
519 Device->PCR = tmpr;
520
521 return HAL_OK;
522}
523
524/**
525 * @brief Initializes the FMC_NAND Common space Timing according to the specified
526 * parameters in the FMC_NAND_PCC_TimingTypeDef
527 * @param Device Pointer to NAND device instance
528 * @param Timing Pointer to NAND timing structure
529 * @param Bank NAND bank number
530 * @retval HAL status
531 */
532HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
533{
534 uint32_t tmpr = 0U;
535
536 /* Check the parameters */
537 assert_param(IS_FMC_NAND_DEVICE(Device));
538 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
539 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
540 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
541 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
542 assert_param(IS_FMC_NAND_BANK(Bank));
543
544 /* Get the NAND bank 2 register value */
545 tmpr = Device->PMEM;
546
547
548 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
549 tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \
550 FMC_PMEM_MEMHIZ2));
551
552 /* Set FMC_NAND device timing parameters */
553 tmpr |= (uint32_t)(Timing->SetupTime |\
554 ((Timing->WaitSetupTime) << 8U) |\
555 ((Timing->HoldSetupTime) << 16U) |\
556 ((Timing->HiZSetupTime) << 24U)
557 );
558
559 /* NAND bank registers configuration */
560 Device->PMEM = tmpr;
561
562 return HAL_OK;
563}
564
565/**
566 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
567 * parameters in the FMC_NAND_PCC_TimingTypeDef
568 * @param Device Pointer to NAND device instance
569 * @param Timing Pointer to NAND timing structure
570 * @param Bank NAND bank number
571 * @retval HAL status
572 */
573HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
574{
575 uint32_t tmpr = 0U;
576
577 /* Check the parameters */
578 assert_param(IS_FMC_NAND_DEVICE(Device));
579 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
580 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
581 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
582 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
583 assert_param(IS_FMC_NAND_BANK(Bank));
584
585 /* Get the NAND bank register value */
586 tmpr = Device->PATT;
587
588 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
589 tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \
590 FMC_PATT_ATTHIZ2));
591
592 /* Set FMC_NAND device timing parameters */
593 tmpr |= (uint32_t)(Timing->SetupTime |\
594 ((Timing->WaitSetupTime) << 8U) |\
595 ((Timing->HoldSetupTime) << 16U) |\
596 ((Timing->HiZSetupTime) << 24U));
597
598 /* NAND bank registers configuration */
599 Device->PATT = tmpr;
600
601 return HAL_OK;
602}
603
604
605/**
606 * @brief DeInitializes the FMC_NAND device
607 * @param Device Pointer to NAND device instance
608 * @param Bank NAND bank number
609 * @retval HAL status
610 */
611HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
612{
613 /* Check the parameters */
614 assert_param(IS_FMC_NAND_DEVICE(Device));
615 assert_param(IS_FMC_NAND_BANK(Bank));
616
617 /* Disable the NAND Bank */
618 __FMC_NAND_DISABLE(Device, Bank);
619
620 /* De-initialize the NAND Bank */
621 /* Set the FMC_NAND_BANK registers to their reset values */
622 Device->PCR = 0x00000018U;
623 Device->SR = 0x00000040U;
624 Device->PMEM = 0xFCFCFCFCU;
625 Device->PATT = 0xFCFCFCFCU;
626
627 return HAL_OK;
628}
629
630/**
631 * @}
632 */
633
634
635/** @defgroup HAL_FMC_NAND_Group2 Control functions
636 * @brief management functions
637 *
638@verbatim
639 ==============================================================================
640 ##### FMC_NAND Control functions #####
641 ==============================================================================
642 [..]
643 This subsection provides a set of functions allowing to control dynamically
644 the FMC NAND interface.
645
646@endverbatim
647 * @{
648 */
649
650
651/**
652 * @brief Enables dynamically FMC_NAND ECC feature.
653 * @param Device Pointer to NAND device instance
654 * @param Bank NAND bank number
655 * @retval HAL status
656 */
657HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
658{
659 /* Check the parameters */
660 assert_param(IS_FMC_NAND_DEVICE(Device));
661 assert_param(IS_FMC_NAND_BANK(Bank));
662
663 /* Enable ECC feature */
664 Device->PCR |= FMC_PCR_ECCEN;
665
666 return HAL_OK;
667}
668
669
670/**
671 * @brief Disables dynamically FMC_NAND ECC feature.
672 * @param Device Pointer to NAND device instance
673 * @param Bank NAND bank number
674 * @retval HAL status
675 */
676HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
677{
678 /* Check the parameters */
679 assert_param(IS_FMC_NAND_DEVICE(Device));
680 assert_param(IS_FMC_NAND_BANK(Bank));
681
682 /* Disable ECC feature */
683 Device->PCR &= ~FMC_PCR_ECCEN;
684
685 return HAL_OK;
686}
687
688/**
689 * @brief Disables dynamically FMC_NAND ECC feature.
690 * @param Device Pointer to NAND device instance
691 * @param ECCval Pointer to ECC value
692 * @param Bank NAND bank number
693 * @param Timeout Timeout wait value
694 * @retval HAL status
695 */
696HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
697{
698 uint32_t tickstart = 0U;
699
700 /* Check the parameters */
701 assert_param(IS_FMC_NAND_DEVICE(Device));
702 assert_param(IS_FMC_NAND_BANK(Bank));
703
704 /* Get tick */
705 tickstart = HAL_GetTick();
706
707 /* Wait until FIFO is empty */
708 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
709 {
710 /* Check for the Timeout */
711 if(Timeout != HAL_MAX_DELAY)
712 {
713 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
714 {
715 return HAL_TIMEOUT;
716 }
717 }
718 }
719
720 /* Get the ECCR register value */
721 *ECCval = (uint32_t)Device->ECCR;
722
723 return HAL_OK;
724}
725
726/**
727 * @}
728 */
729
730#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
731/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
732 * @brief Initialization and Configuration functions
733 *
734@verbatim
735 ==============================================================================
736 ##### Initialization and de_initialization functions #####
737 ==============================================================================
738 [..]
739 This section provides functions allowing to:
740 (+) Initialize and configure the FMC NAND interface
741 (+) De-initialize the FMC NAND interface
742 (+) Configure the FMC clock and associated GPIOs
743
744@endverbatim
745 * @{
746 */
747/**
748 * @brief Initializes the FMC_NAND device according to the specified
749 * control parameters in the FMC_NAND_HandleTypeDef
750 * @param Device Pointer to NAND device instance
751 * @param Init Pointer to NAND Initialization structure
752 * @retval HAL status
753 */
754HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
755{
756 uint32_t tmpr = 0U;
757
758 /* Check the parameters */
759 assert_param(IS_FMC_NAND_DEVICE(Device));
760 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
761 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
762 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
763 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
764 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
765 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
766 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
767
768 if(Init->NandBank == FMC_NAND_BANK2)
769 {
770 /* Get the NAND bank 2 register value */
771 tmpr = Device->PCR2;
772 }
773 else
774 {
775 /* Get the NAND bank 3 register value */
776 tmpr = Device->PCR3;
777 }
778
779 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
780 tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \
781 FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \
782 FMC_PCR2_TAR | FMC_PCR2_ECCPS));
783
784 /* Set NAND device control parameters */
785 tmpr |= (uint32_t)(Init->Waitfeature |\
786 FMC_PCR_MEMORY_TYPE_NAND |\
787 Init->MemoryDataWidth |\
788 Init->EccComputation |\
789 Init->ECCPageSize |\
790 ((Init->TCLRSetupTime) << 9U) |\
791 ((Init->TARSetupTime) << 13U));
792
793 if(Init->NandBank == FMC_NAND_BANK2)
794 {
795 /* NAND bank 2 registers configuration */
796 Device->PCR2 = tmpr;
797 }
798 else
799 {
800 /* NAND bank 3 registers configuration */
801 Device->PCR3 = tmpr;
802 }
803
804 return HAL_OK;
805
806}
807
808/**
809 * @brief Initializes the FMC_NAND Common space Timing according to the specified
810 * parameters in the FMC_NAND_PCC_TimingTypeDef
811 * @param Device Pointer to NAND device instance
812 * @param Timing Pointer to NAND timing structure
813 * @param Bank NAND bank number
814 * @retval HAL status
815 */
816HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
817{
818 uint32_t tmpr = 0U;
819
820 /* Check the parameters */
821 assert_param(IS_FMC_NAND_DEVICE(Device));
822 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
823 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
824 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
825 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
826 assert_param(IS_FMC_NAND_BANK(Bank));
827
828 if(Bank == FMC_NAND_BANK2)
829 {
830 /* Get the NAND bank 2 register value */
831 tmpr = Device->PMEM2;
832 }
833 else
834 {
835 /* Get the NAND bank 3 register value */
836 tmpr = Device->PMEM3;
837 }
838
839 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
840 tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \
841 FMC_PMEM2_MEMHIZ2));
842
843 /* Set FMC_NAND device timing parameters */
844 tmpr |= (uint32_t)(Timing->SetupTime |\
845 ((Timing->WaitSetupTime) << 8U) |\
846 ((Timing->HoldSetupTime) << 16U) |\
847 ((Timing->HiZSetupTime) << 24U)
848 );
849
850 if(Bank == FMC_NAND_BANK2)
851 {
852 /* NAND bank 2 registers configuration */
853 Device->PMEM2 = tmpr;
854 }
855 else
856 {
857 /* NAND bank 3 registers configuration */
858 Device->PMEM3 = tmpr;
859 }
860
861 return HAL_OK;
862}
863
864/**
865 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
866 * parameters in the FMC_NAND_PCC_TimingTypeDef
867 * @param Device Pointer to NAND device instance
868 * @param Timing Pointer to NAND timing structure
869 * @param Bank NAND bank number
870 * @retval HAL status
871 */
872HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
873{
874 uint32_t tmpr = 0U;
875
876 /* Check the parameters */
877 assert_param(IS_FMC_NAND_DEVICE(Device));
878 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
879 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
880 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
881 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
882 assert_param(IS_FMC_NAND_BANK(Bank));
883
884 if(Bank == FMC_NAND_BANK2)
885 {
886 /* Get the NAND bank 2 register value */
887 tmpr = Device->PATT2;
888 }
889 else
890 {
891 /* Get the NAND bank 3 register value */
892 tmpr = Device->PATT3;
893 }
894
895 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
896 tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \
897 FMC_PATT2_ATTHIZ2));
898
899 /* Set FMC_NAND device timing parameters */
900 tmpr |= (uint32_t)(Timing->SetupTime |\
901 ((Timing->WaitSetupTime) << 8U) |\
902 ((Timing->HoldSetupTime) << 16U) |\
903 ((Timing->HiZSetupTime) << 24U));
904
905 if(Bank == FMC_NAND_BANK2)
906 {
907 /* NAND bank 2 registers configuration */
908 Device->PATT2 = tmpr;
909 }
910 else
911 {
912 /* NAND bank 3 registers configuration */
913 Device->PATT3 = tmpr;
914 }
915
916 return HAL_OK;
917}
918
919/**
920 * @brief DeInitializes the FMC_NAND device
921 * @param Device Pointer to NAND device instance
922 * @param Bank NAND bank number
923 * @retval HAL status
924 */
925HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
926{
927 /* Check the parameters */
928 assert_param(IS_FMC_NAND_DEVICE(Device));
929 assert_param(IS_FMC_NAND_BANK(Bank));
930
931 /* Disable the NAND Bank */
932 __FMC_NAND_DISABLE(Device, Bank);
933
934 /* De-initialize the NAND Bank */
935 if(Bank == FMC_NAND_BANK2)
936 {
937 /* Set the FMC_NAND_BANK2 registers to their reset values */
938 Device->PCR2 = 0x00000018U;
939 Device->SR2 = 0x00000040U;
940 Device->PMEM2 = 0xFCFCFCFCU;
941 Device->PATT2 = 0xFCFCFCFCU;
942 }
943 /* FMC_Bank3_NAND */
944 else
945 {
946 /* Set the FMC_NAND_BANK3 registers to their reset values */
947 Device->PCR3 = 0x00000018U;
948 Device->SR3 = 0x00000040U;
949 Device->PMEM3 = 0xFCFCFCFCU;
950 Device->PATT3 = 0xFCFCFCFCU;
951 }
952
953 return HAL_OK;
954}
955
956/**
957 * @}
958 */
959
960/** @addtogroup FMC_LL_NAND_Private_Functions_Group2
961 * @brief management functions
962 *
963@verbatim
964 ==============================================================================
965 ##### FMC_NAND Control functions #####
966 ==============================================================================
967 [..]
968 This subsection provides a set of functions allowing to control dynamically
969 the FMC NAND interface.
970
971@endverbatim
972 * @{
973 */
974/**
975 * @brief Enables dynamically FMC_NAND ECC feature.
976 * @param Device Pointer to NAND device instance
977 * @param Bank NAND bank number
978 * @retval HAL status
979 */
980HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
981{
982 /* Check the parameters */
983 assert_param(IS_FMC_NAND_DEVICE(Device));
984 assert_param(IS_FMC_NAND_BANK(Bank));
985
986 /* Enable ECC feature */
987 if(Bank == FMC_NAND_BANK2)
988 {
989 Device->PCR2 |= FMC_PCR2_ECCEN;
990 }
991 else
992 {
993 Device->PCR3 |= FMC_PCR3_ECCEN;
994 }
995
996 return HAL_OK;
997}
998
999/**
1000 * @brief Disables dynamically FMC_NAND ECC feature.
1001 * @param Device Pointer to NAND device instance
1002 * @param Bank NAND bank number
1003 * @retval HAL status
1004 */
1005HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
1006{
1007 /* Check the parameters */
1008 assert_param(IS_FMC_NAND_DEVICE(Device));
1009 assert_param(IS_FMC_NAND_BANK(Bank));
1010
1011 /* Disable ECC feature */
1012 if(Bank == FMC_NAND_BANK2)
1013 {
1014 Device->PCR2 &= ~FMC_PCR2_ECCEN;
1015 }
1016 else
1017 {
1018 Device->PCR3 &= ~FMC_PCR3_ECCEN;
1019 }
1020
1021 return HAL_OK;
1022}
1023
1024/**
1025 * @brief Disables dynamically FMC_NAND ECC feature.
1026 * @param Device Pointer to NAND device instance
1027 * @param ECCval Pointer to ECC value
1028 * @param Bank NAND bank number
1029 * @param Timeout Timeout wait value
1030 * @retval HAL status
1031 */
1032HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
1033{
1034 uint32_t tickstart = 0U;
1035
1036 /* Check the parameters */
1037 assert_param(IS_FMC_NAND_DEVICE(Device));
1038 assert_param(IS_FMC_NAND_BANK(Bank));
1039
1040 /* Get tick */
1041 tickstart = HAL_GetTick();
1042
1043 /* Wait until FIFO is empty */
1044 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
1045 {
1046 /* Check for the Timeout */
1047 if(Timeout != HAL_MAX_DELAY)
1048 {
1049 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
1050 {
1051 return HAL_TIMEOUT;
1052 }
1053 }
1054 }
1055
1056 if(Bank == FMC_NAND_BANK2)
1057 {
1058 /* Get the ECCR2 register value */
1059 *ECCval = (uint32_t)Device->ECCR2;
1060 }
1061 else
1062 {
1063 /* Get the ECCR3 register value */
1064 *ECCval = (uint32_t)Device->ECCR3;
1065 }
1066
1067 return HAL_OK;
1068}
1069
1070/**
1071 * @}
1072 */
1073
1074#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
1075/**
1076 * @}
1077 */
1078
1079#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
1080/** @addtogroup FMC_LL_PCCARD
1081 * @brief PCCARD Controller functions
1082 *
1083 @verbatim
1084 ==============================================================================
1085 ##### How to use PCCARD device driver #####
1086 ==============================================================================
1087 [..]
1088 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
1089 to run the PCCARD/compact flash external devices.
1090
1091 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
1092 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
1093 (+) FMC PCCARD bank common space timing configuration using the function
1094 FMC_PCCARD_CommonSpace_Timing_Init()
1095 (+) FMC PCCARD bank attribute space timing configuration using the function
1096 FMC_PCCARD_AttributeSpace_Timing_Init()
1097 (+) FMC PCCARD bank IO space timing configuration using the function
1098 FMC_PCCARD_IOSpace_Timing_Init()
1099@endverbatim
1100 * @{
1101 */
1102
1103/** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
1104 * @brief Initialization and Configuration functions
1105 *
1106@verbatim
1107 ==============================================================================
1108 ##### Initialization and de_initialization functions #####
1109 ==============================================================================
1110 [..]
1111 This section provides functions allowing to:
1112 (+) Initialize and configure the FMC PCCARD interface
1113 (+) De-initialize the FMC PCCARD interface
1114 (+) Configure the FMC clock and associated GPIOs
1115
1116@endverbatim
1117 * @{
1118 */
1119
1120/**
1121 * @brief Initializes the FMC_PCCARD device according to the specified
1122 * control parameters in the FMC_PCCARD_HandleTypeDef
1123 * @param Device Pointer to PCCARD device instance
1124 * @param Init Pointer to PCCARD Initialization structure
1125 * @retval HAL status
1126 */
1127HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
1128{
1129 uint32_t tmpr = 0U;
1130
1131 /* Check the parameters */
1132 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1133 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
1134 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
1135 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
1136
1137 /* Get PCCARD control register value */
1138 tmpr = Device->PCR4;
1139
1140 /* Clear TAR, TCLR, PWAITEN and PWID bits */
1141 tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \
1142 FMC_PCR4_PWID | FMC_PCR4_PTYP));
1143
1144 /* Set FMC_PCCARD device control parameters */
1145 tmpr |= (uint32_t)(Init->Waitfeature |\
1146 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
1147 (Init->TCLRSetupTime << 9U) |\
1148 (Init->TARSetupTime << 13U));
1149
1150 Device->PCR4 = tmpr;
1151
1152 return HAL_OK;
1153}
1154
1155/**
1156 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
1157 * parameters in the FMC_NAND_PCC_TimingTypeDef
1158 * @param Device Pointer to PCCARD device instance
1159 * @param Timing Pointer to PCCARD timing structure
1160 * @retval HAL status
1161 */
1162HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
1163{
1164 uint32_t tmpr = 0U;
1165
1166 /* Check the parameters */
1167 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1168 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1169 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1170 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1171 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1172
1173 /* Get PCCARD common space timing register value */
1174 tmpr = Device->PMEM4;
1175
1176 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
1177 tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \
1178 FMC_PMEM4_MEMHIZ4));
1179 /* Set PCCARD timing parameters */
1180 tmpr |= (uint32_t)(Timing->SetupTime |\
1181 ((Timing->WaitSetupTime) << 8U) |\
1182 ((Timing->HoldSetupTime) << 16U) |\
1183 ((Timing->HiZSetupTime) << 24U));
1184
1185 Device->PMEM4 = tmpr;
1186
1187 return HAL_OK;
1188}
1189
1190/**
1191 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
1192 * parameters in the FMC_NAND_PCC_TimingTypeDef
1193 * @param Device Pointer to PCCARD device instance
1194 * @param Timing Pointer to PCCARD timing structure
1195 * @retval HAL status
1196 */
1197HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
1198{
1199 uint32_t tmpr = 0U;
1200
1201 /* Check the parameters */
1202 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1203 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1204 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1205 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1206 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1207
1208 /* Get PCCARD timing parameters */
1209 tmpr = Device->PATT4;
1210
1211 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
1212 tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \
1213 FMC_PATT4_ATTHIZ4));
1214
1215 /* Set PCCARD timing parameters */
1216 tmpr |= (uint32_t)(Timing->SetupTime |\
1217 ((Timing->WaitSetupTime) << 8U) |\
1218 ((Timing->HoldSetupTime) << 16U) |\
1219 ((Timing->HiZSetupTime) << 24U));
1220 Device->PATT4 = tmpr;
1221
1222 return HAL_OK;
1223}
1224
1225/**
1226 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
1227 * parameters in the FMC_NAND_PCC_TimingTypeDef
1228 * @param Device Pointer to PCCARD device instance
1229 * @param Timing Pointer to PCCARD timing structure
1230 * @retval HAL status
1231 */
1232HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
1233{
1234 uint32_t tmpr = 0;
1235
1236 /* Check the parameters */
1237 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1238 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1239 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1240 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1241 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1242
1243 /* Get FMC_PCCARD device timing parameters */
1244 tmpr = Device->PIO4;
1245
1246 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
1247 tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \
1248 FMC_PIO4_IOHIZ4));
1249
1250 /* Set FMC_PCCARD device timing parameters */
1251 tmpr |= (uint32_t)(Timing->SetupTime |\
1252 ((Timing->WaitSetupTime) << 8U) |\
1253 ((Timing->HoldSetupTime) << 16U) |\
1254 ((Timing->HiZSetupTime) << 24U));
1255
1256 Device->PIO4 = tmpr;
1257
1258 return HAL_OK;
1259}
1260
1261/**
1262 * @brief DeInitializes the FMC_PCCARD device
1263 * @param Device Pointer to PCCARD device instance
1264 * @retval HAL status
1265 */
1266HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
1267{
1268 /* Check the parameters */
1269 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1270
1271 /* Disable the FMC_PCCARD device */
1272 __FMC_PCCARD_DISABLE(Device);
1273
1274 /* De-initialize the FMC_PCCARD device */
1275 Device->PCR4 = 0x00000018U;
1276 Device->SR4 = 0x00000000U;
1277 Device->PMEM4 = 0xFCFCFCFCU;
1278 Device->PATT4 = 0xFCFCFCFCU;
1279 Device->PIO4 = 0xFCFCFCFCU;
1280
1281 return HAL_OK;
1282}
1283
1284/**
1285 * @}
1286 */
1287#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1288
1289
1290/** @addtogroup FMC_LL_SDRAM
1291 * @brief SDRAM Controller functions
1292 *
1293 @verbatim
1294 ==============================================================================
1295 ##### How to use SDRAM device driver #####
1296 ==============================================================================
1297 [..]
1298 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
1299 to run the SDRAM external devices.
1300
1301 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
1302 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
1303 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
1304 (+) FMC SDRAM bank enable/disable write operation using the functions
1305 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
1306 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
1307
1308@endverbatim
1309 * @{
1310 */
1311
1312/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
1313 * @brief Initialization and Configuration functions
1314 *
1315@verbatim
1316 ==============================================================================
1317 ##### Initialization and de_initialization functions #####
1318 ==============================================================================
1319 [..]
1320 This section provides functions allowing to:
1321 (+) Initialize and configure the FMC SDRAM interface
1322 (+) De-initialize the FMC SDRAM interface
1323 (+) Configure the FMC clock and associated GPIOs
1324
1325@endverbatim
1326 * @{
1327 */
1328
1329/**
1330 * @brief Initializes the FMC_SDRAM device according to the specified
1331 * control parameters in the FMC_SDRAM_InitTypeDef
1332 * @param Device Pointer to SDRAM device instance
1333 * @param Init Pointer to SDRAM Initialization structure
1334 * @retval HAL status
1335 */
1336HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
1337{
1338 uint32_t tmpr1 = 0U;
1339 uint32_t tmpr2 = 0U;
1340
1341 /* Check the parameters */
1342 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1343 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
1344 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
1345 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
1346 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
1347 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
1348 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
1349 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
1350 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
1351 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
1352 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
1353
1354 /* Set SDRAM bank configuration parameters */
1355 if (Init->SDBank != FMC_SDRAM_BANK2)
1356 {
1357 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
1358
1359 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
1360 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
1361 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
1362 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
1363
1364
1365 tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
1366 Init->RowBitsNumber |\
1367 Init->MemoryDataWidth |\
1368 Init->InternalBankNumber |\
1369 Init->CASLatency |\
1370 Init->WriteProtection |\
1371 Init->SDClockPeriod |\
1372 Init->ReadBurst |\
1373 Init->ReadPipeDelay
1374 );
1375 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
1376 }
1377 else /* FMC_Bank2_SDRAM */
1378 {
1379 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
1380
1381 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
1382 tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
1383
1384 tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
1385 Init->ReadBurst |\
1386 Init->ReadPipeDelay);
1387
1388 tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
1389
1390 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
1391 tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
1392 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
1393 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
1394
1395 tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
1396 Init->RowBitsNumber |\
1397 Init->MemoryDataWidth |\
1398 Init->InternalBankNumber |\
1399 Init->CASLatency |\
1400 Init->WriteProtection);
1401
1402 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
1403 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
1404 }
1405
1406 return HAL_OK;
1407}
1408
1409/**
1410 * @brief Initializes the FMC_SDRAM device timing according to the specified
1411 * parameters in the FMC_SDRAM_TimingTypeDef
1412 * @param Device Pointer to SDRAM device instance
1413 * @param Timing Pointer to SDRAM Timing structure
1414 * @param Bank SDRAM bank number
1415 * @retval HAL status
1416 */
1417HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
1418{
1419 uint32_t tmpr1 = 0U;
1420 uint32_t tmpr2 = 0U;
1421
1422 /* Check the parameters */
1423 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1424 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
1425 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
1426 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
1427 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
1428 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
1429 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
1430 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
1431 assert_param(IS_FMC_SDRAM_BANK(Bank));
1432
1433 /* Set SDRAM device timing parameters */
1434 if (Bank != FMC_SDRAM_BANK2)
1435 {
1436 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
1437
1438 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
1439 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
1440 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
1441 FMC_SDTR1_TRCD));
1442
1443 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\
1444 (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
1445 (((Timing->SelfRefreshTime)-1U) << 8U) |\
1446 (((Timing->RowCycleDelay)-1U) << 12U) |\
1447 (((Timing->WriteRecoveryTime)-1U) <<16U) |\
1448 (((Timing->RPDelay)-1U) << 20U) |\
1449 (((Timing->RCDDelay)-1U) << 24U));
1450 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
1451 }
1452 else /* FMC_Bank2_SDRAM */
1453 {
1454 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
1455
1456 /* Clear TRC and TRP bits */
1457 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
1458
1459 tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U) |\
1460 (((Timing->RPDelay)-1U) << 20U));
1461
1462 tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
1463
1464 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
1465 tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
1466 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
1467 FMC_SDTR1_TRCD));
1468
1469 tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1U) |\
1470 (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
1471 (((Timing->SelfRefreshTime)-1U) << 8U) |\
1472 (((Timing->WriteRecoveryTime)-1U) <<16U) |\
1473 (((Timing->RCDDelay)-1U) << 24U)));
1474
1475 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
1476 Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
1477 }
1478 return HAL_OK;
1479}
1480
1481/**
1482 * @brief DeInitializes the FMC_SDRAM peripheral
1483 * @param Device Pointer to SDRAM device instance
1484 * @retval HAL status
1485 */
1486HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1487{
1488 /* Check the parameters */
1489 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1490 assert_param(IS_FMC_SDRAM_BANK(Bank));
1491
1492 /* De-initialize the SDRAM device */
1493 Device->SDCR[Bank] = 0x000002D0U;
1494 Device->SDTR[Bank] = 0x0FFFFFFFU;
1495 Device->SDCMR = 0x00000000U;
1496 Device->SDRTR = 0x00000000U;
1497 Device->SDSR = 0x00000000U;
1498
1499 return HAL_OK;
1500}
1501
1502/**
1503 * @}
1504 */
1505
1506/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
1507 * @brief management functions
1508 *
1509@verbatim
1510 ==============================================================================
1511 ##### FMC_SDRAM Control functions #####
1512 ==============================================================================
1513 [..]
1514 This subsection provides a set of functions allowing to control dynamically
1515 the FMC SDRAM interface.
1516
1517@endverbatim
1518 * @{
1519 */
1520/**
1521 * @brief Enables dynamically FMC_SDRAM write protection.
1522 * @param Device Pointer to SDRAM device instance
1523 * @param Bank SDRAM bank number
1524 * @retval HAL status
1525 */
1526HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1527{
1528 /* Check the parameters */
1529 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1530 assert_param(IS_FMC_SDRAM_BANK(Bank));
1531
1532 /* Enable write protection */
1533 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
1534
1535 return HAL_OK;
1536}
1537
1538/**
1539 * @brief Disables dynamically FMC_SDRAM write protection.
1540 * @param hsdram FMC_SDRAM handle
1541 * @retval HAL status
1542 */
1543HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1544{
1545 /* Check the parameters */
1546 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1547 assert_param(IS_FMC_SDRAM_BANK(Bank));
1548
1549 /* Disable write protection */
1550 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
1551
1552 return HAL_OK;
1553}
1554
1555/**
1556 * @brief Send Command to the FMC SDRAM bank
1557 * @param Device Pointer to SDRAM device instance
1558 * @param Command Pointer to SDRAM command structure
1559 * @param Timing Pointer to SDRAM Timing structure
1560 * @param Timeout Timeout wait value
1561 * @retval HAL state
1562 */
1563HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
1564{
1565 __IO uint32_t tmpr = 0U;
1566 uint32_t tickstart = 0U;
1567
1568 /* Check the parameters */
1569 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1570 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
1571 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
1572 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
1573 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
1574
1575 /* Set command register */
1576 tmpr = (uint32_t)((Command->CommandMode) |\
1577 (Command->CommandTarget) |\
1578 (((Command->AutoRefreshNumber)-1U) << 5U) |\
1579 ((Command->ModeRegisterDefinition) << 9U)
1580 );
1581
1582 Device->SDCMR = tmpr;
1583
1584 /* Get tick */
1585 tickstart = HAL_GetTick();
1586
1587 /* Wait until command is send */
1588 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
1589 {
1590 /* Check for the Timeout */
1591 if(Timeout != HAL_MAX_DELAY)
1592 {
1593 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
1594 {
1595 return HAL_TIMEOUT;
1596 }
1597 }
1598 }
1599
1600 return HAL_OK;
1601}
1602
1603/**
1604 * @brief Program the SDRAM Memory Refresh rate.
1605 * @param Device Pointer to SDRAM device instance
1606 * @param RefreshRate The SDRAM refresh rate value.
1607 * @retval HAL state
1608 */
1609HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1610{
1611 /* Check the parameters */
1612 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1613 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1614
1615 /* Set the refresh rate in command register */
1616 Device->SDRTR |= (RefreshRate<<1U);
1617
1618 return HAL_OK;
1619}
1620
1621/**
1622 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
1623 * @param Device Pointer to SDRAM device instance
1624 * @param AutoRefreshNumber Specifies the auto Refresh number.
1625 * @retval None
1626 */
1627HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
1628{
1629 /* Check the parameters */
1630 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1631 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1632
1633 /* Set the Auto-refresh number in command register */
1634 Device->SDCMR |= (AutoRefreshNumber << 5U);
1635
1636 return HAL_OK;
1637}
1638
1639/**
1640 * @brief Returns the indicated FMC SDRAM bank mode status.
1641 * @param Device Pointer to SDRAM device instance
1642 * @param Bank Defines the FMC SDRAM bank. This parameter can be
1643 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1644 * @retval The FMC SDRAM bank mode status, could be on of the following values:
1645 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1646 * FMC_SDRAM_POWER_DOWN_MODE.
1647 */
1648uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1649{
1650 uint32_t tmpreg = 0U;
1651
1652 /* Check the parameters */
1653 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1654 assert_param(IS_FMC_SDRAM_BANK(Bank));
1655
1656 /* Get the corresponding bank mode */
1657 if(Bank == FMC_SDRAM_BANK1)
1658 {
1659 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1660 }
1661 else
1662 {
1663 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1664 }
1665
1666 /* Return the mode status */
1667 return tmpreg;
1668}
1669
1670/**
1671 * @}
1672 */
1673
1674/**
1675 * @}
1676 */
1677
1678/**
1679 * @}
1680 */
1681#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
1682#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
1683
1684/**
1685 * @}
1686 */
1687
1688/**
1689 * @}
1690 */
1691
1692/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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