source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c

Last change on this file was 1, checked in by AlexLir, 4 years ago
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19#if defined(USE_FULL_LL_DRIVER)
20
21/* Includes ------------------------------------------------------------------*/
22#include "stm32f4xx_ll_rcc.h"
23#ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25#else
26 #define assert_param(expr) ((void)0U)
27#endif
28/** @addtogroup STM32F4xx_LL_Driver
29 * @{
30 */
31
32#if defined(RCC)
33
34/** @addtogroup RCC_LL
35 * @{
36 */
37
38/* Private types -------------------------------------------------------------*/
39/* Private variables ---------------------------------------------------------*/
40/* Private constants ---------------------------------------------------------*/
41/* Private macros ------------------------------------------------------------*/
42/** @addtogroup RCC_LL_Private_Macros
43 * @{
44 */
45#if defined(FMPI2C1)
46#define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE)
47#endif /* FMPI2C1 */
48
49#if defined(LPTIM1)
50#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
51#endif /* LPTIM1 */
52
53#if defined(SAI1)
54#if defined(RCC_DCKCFGR_SAI1SRC)
55#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
56 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
57#elif defined(RCC_DCKCFGR_SAI1ASRC)
58#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \
59 || ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE))
60#endif /* RCC_DCKCFGR_SAI1SRC */
61#endif /* SAI1 */
62
63#if defined(SDIO)
64#define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE))
65#endif /* SDIO */
66
67#if defined(RNG)
68#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
69#endif /* RNG */
70
71#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
72#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
73#endif /* USB_OTG_FS || USB_OTG_HS */
74
75#if defined(DFSDM2_Channel0)
76#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
77
78#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \
79 || ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE))
80#elif defined(DFSDM1_Channel0)
81#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
82
83#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
84#endif /* DFSDM2_Channel0 */
85
86#if defined(RCC_DCKCFGR_I2S2SRC)
87#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
88 || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))
89#else
90#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
91#endif /* RCC_DCKCFGR_I2S2SRC */
92
93#if defined(CEC)
94#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
95#endif /* CEC */
96
97#if defined(DSI)
98#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
99#endif /* DSI */
100
101#if defined(LTDC)
102#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
103#endif /* LTDC */
104
105#if defined(SPDIFRX)
106#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
107#endif /* SPDIFRX */
108/**
109 * @}
110 */
111
112/* Private function prototypes -----------------------------------------------*/
113/** @defgroup RCC_LL_Private_Functions RCC Private functions
114 * @{
115 */
116uint32_t RCC_GetSystemClockFreq(void);
117uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
118uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
119uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
120uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);
121uint32_t RCC_PLL_GetFreqDomain_48M(void);
122#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
123uint32_t RCC_PLL_GetFreqDomain_I2S(void);
124#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
125#if defined(SPDIFRX)
126uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void);
127#endif /* SPDIFRX */
128#if defined(RCC_PLLCFGR_PLLR)
129#if defined(SAI1)
130uint32_t RCC_PLL_GetFreqDomain_SAI(void);
131#endif /* SAI1 */
132#endif /* RCC_PLLCFGR_PLLR */
133#if defined(DSI)
134uint32_t RCC_PLL_GetFreqDomain_DSI(void);
135#endif /* DSI */
136#if defined(RCC_PLLSAI_SUPPORT)
137uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
138#if defined(RCC_PLLSAICFGR_PLLSAIP)
139uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
140#endif /* RCC_PLLSAICFGR_PLLSAIP */
141#if defined(LTDC)
142uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
143#endif /* LTDC */
144#endif /* RCC_PLLSAI_SUPPORT */
145#if defined(RCC_PLLI2S_SUPPORT)
146uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
147#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
148uint32_t RCC_PLLI2S_GetFreqDomain_48M(void);
149#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
150#if defined(SAI1)
151uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
152#endif /* SAI1 */
153#if defined(SPDIFRX)
154uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
155#endif /* SPDIFRX */
156#endif /* RCC_PLLI2S_SUPPORT */
157/**
158 * @}
159 */
160
161
162/* Exported functions --------------------------------------------------------*/
163/** @addtogroup RCC_LL_Exported_Functions
164 * @{
165 */
166
167/** @addtogroup RCC_LL_EF_Init
168 * @{
169 */
170
171/**
172 * @brief Reset the RCC clock configuration to the default reset state.
173 * @note The default reset state of the clock configuration is given below:
174 * - HSI ON and used as system clock source
175 * - HSE and PLL OFF
176 * - AHB, APB1 and APB2 prescaler set to 1.
177 * - CSS, MCO OFF
178 * - All interrupts disabled
179 * @note This function doesn't modify the configuration of the
180 * - Peripheral clocks
181 * - LSI, LSE and RTC clocks
182 * @retval An ErrorStatus enumeration value:
183 * - SUCCESS: RCC registers are de-initialized
184 * - ERROR: not applicable
185 */
186ErrorStatus LL_RCC_DeInit(void)
187{
188 __IO uint32_t vl_mask;
189
190 /* Set HSION bit */
191 LL_RCC_HSI_Enable();
192
193 /* Wait for HSI READY bit */
194 while(LL_RCC_HSI_IsReady() != 1U)
195 {}
196
197 /* Reset CFGR register */
198 LL_RCC_WriteReg(CFGR, 0x00000000U);
199
200 /* Read CR register */
201 vl_mask = LL_RCC_ReadReg(CR);
202
203 /* Reset HSEON, HSEBYP, PLLON, CSSON bits */
204 CLEAR_BIT(vl_mask,
205 (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
206
207#if defined(RCC_PLLSAI_SUPPORT)
208 /* Reset PLLSAION bit */
209 CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);
210#endif /* RCC_PLLSAI_SUPPORT */
211
212#if defined(RCC_PLLI2S_SUPPORT)
213 /* Reset PLLI2SON bit */
214 CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
215#endif /* RCC_PLLI2S_SUPPORT */
216
217 /* Write new value in CR register */
218 LL_RCC_WriteReg(CR, vl_mask);
219
220 /* Set HSITRIM bits to the reset value*/
221 LL_RCC_HSI_SetCalibTrimming(0x10U);
222
223 /* Wait for PLL READY bit to be reset */
224 while(LL_RCC_PLL_IsReady() != 0U)
225 {}
226
227 /* Reset PLLCFGR register */
228 LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);
229
230#if defined(RCC_PLLI2S_SUPPORT)
231 /* Reset PLLI2SCFGR register */
232 LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE);
233#endif /* RCC_PLLI2S_SUPPORT */
234
235#if defined(RCC_PLLSAI_SUPPORT)
236 /* Reset PLLSAICFGR register */
237 LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);
238#endif /* RCC_PLLSAI_SUPPORT */
239
240 /* Disable all interrupts */
241 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
242
243#if defined(RCC_CIR_PLLI2SRDYIE)
244 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
245#endif /* RCC_CIR_PLLI2SRDYIE */
246
247#if defined(RCC_CIR_PLLSAIRDYIE)
248 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
249#endif /* RCC_CIR_PLLSAIRDYIE */
250
251 /* Clear all interrupt flags */
252 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
253
254#if defined(RCC_CIR_PLLI2SRDYC)
255 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
256#endif /* RCC_CIR_PLLI2SRDYC */
257
258#if defined(RCC_CIR_PLLSAIRDYC)
259 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
260#endif /* RCC_CIR_PLLSAIRDYC */
261
262 /* Clear LSION bit */
263 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
264
265 /* Reset all CSR flags */
266 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
267
268 return SUCCESS;
269}
270
271/**
272 * @}
273 */
274
275/** @addtogroup RCC_LL_EF_Get_Freq
276 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
277 * and different peripheral clocks available on the device.
278 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
279 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
280 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
281 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
282 * @note (**) HSI_VALUE is a constant defined in this file (default value
283 * 16 MHz) but the real value may vary depending on the variations
284 * in voltage and temperature.
285 * @note (***) HSE_VALUE is a constant defined in this file (default value
286 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
287 * frequency of the crystal used. Otherwise, this function may
288 * have wrong result.
289 * @note The result of this function could be incorrect when using fractional
290 * value for HSE crystal.
291 * @note This function can be used by the user application to compute the
292 * baud-rate for the communication peripherals or configure other parameters.
293 * @{
294 */
295
296/**
297 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
298 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
299 * must be called to update structure fields. Otherwise, any
300 * configuration based on this function will be incorrect.
301 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
302 * @retval None
303 */
304void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
305{
306 /* Get SYSCLK frequency */
307 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
308
309 /* HCLK clock frequency */
310 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
311
312 /* PCLK1 clock frequency */
313 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
314
315 /* PCLK2 clock frequency */
316 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
317}
318
319#if defined(FMPI2C1)
320/**
321 * @brief Return FMPI2Cx clock frequency
322 * @param FMPI2CxSource This parameter can be one of the following values:
323 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
324 * @retval FMPI2C clock frequency (in Hz)
325 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
326 */
327uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)
328{
329 uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
330
331 /* Check parameter */
332 assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource));
333
334 if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE)
335 {
336 /* FMPI2C1 CLK clock frequency */
337 switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource))
338 {
339 case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */
340 FMPI2C_frequency = RCC_GetSystemClockFreq();
341 break;
342
343 case LL_RCC_FMPI2C1_CLKSOURCE_HSI: /* FMPI2C1 Clock is HSI Osc. */
344 if (LL_RCC_HSI_IsReady())
345 {
346 FMPI2C_frequency = HSI_VALUE;
347 }
348 break;
349
350 case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1: /* FMPI2C1 Clock is PCLK1 */
351 default:
352 FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
353 break;
354 }
355 }
356
357 return FMPI2C_frequency;
358}
359#endif /* FMPI2C1 */
360
361/**
362 * @brief Return I2Sx clock frequency
363 * @param I2SxSource This parameter can be one of the following values:
364 * @arg @ref LL_RCC_I2S1_CLKSOURCE
365 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
366 *
367 * (*) value not defined in all devices.
368 * @retval I2S clock frequency (in Hz)
369 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
370 */
371uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
372{
373 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
374
375 /* Check parameter */
376 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
377
378 if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
379 {
380 /* I2S1 CLK clock frequency */
381 switch (LL_RCC_GetI2SClockSource(I2SxSource))
382 {
383#if defined(RCC_PLLI2S_SUPPORT)
384 case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
385 if (LL_RCC_PLLI2S_IsReady())
386 {
387 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
388 }
389 break;
390#endif /* RCC_PLLI2S_SUPPORT */
391
392#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
393 case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL */
394 if (LL_RCC_PLL_IsReady())
395 {
396 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
397 }
398 break;
399
400 case LL_RCC_I2S1_CLKSOURCE_PLLSRC: /* I2S1 Clock is PLL Main source */
401 switch (LL_RCC_PLL_GetMainSource())
402 {
403 case LL_RCC_PLLSOURCE_HSE: /* I2S1 Clock is HSE Osc. */
404 if (LL_RCC_HSE_IsReady())
405 {
406 i2s_frequency = HSE_VALUE;
407 }
408 break;
409
410 case LL_RCC_PLLSOURCE_HSI: /* I2S1 Clock is HSI Osc. */
411 default:
412 if (LL_RCC_HSI_IsReady())
413 {
414 i2s_frequency = HSI_VALUE;
415 }
416 break;
417 }
418 break;
419#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
420
421 case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
422 default:
423 i2s_frequency = EXTERNAL_CLOCK_VALUE;
424 break;
425 }
426 }
427#if defined(RCC_DCKCFGR_I2S2SRC)
428 else
429 {
430 /* I2S2 CLK clock frequency */
431 switch (LL_RCC_GetI2SClockSource(I2SxSource))
432 {
433 case LL_RCC_I2S2_CLKSOURCE_PLLI2S: /* I2S2 Clock is PLLI2S */
434 if (LL_RCC_PLLI2S_IsReady())
435 {
436 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
437 }
438 break;
439
440 case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */
441 if (LL_RCC_PLL_IsReady())
442 {
443 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
444 }
445 break;
446
447 case LL_RCC_I2S2_CLKSOURCE_PLLSRC: /* I2S2 Clock is PLL Main source */
448 switch (LL_RCC_PLL_GetMainSource())
449 {
450 case LL_RCC_PLLSOURCE_HSE: /* I2S2 Clock is HSE Osc. */
451 if (LL_RCC_HSE_IsReady())
452 {
453 i2s_frequency = HSE_VALUE;
454 }
455 break;
456
457 case LL_RCC_PLLSOURCE_HSI: /* I2S2 Clock is HSI Osc. */
458 default:
459 if (LL_RCC_HSI_IsReady())
460 {
461 i2s_frequency = HSI_VALUE;
462 }
463 break;
464 }
465 break;
466
467 case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
468 default:
469 i2s_frequency = EXTERNAL_CLOCK_VALUE;
470 break;
471 }
472 }
473#endif /* RCC_DCKCFGR_I2S2SRC */
474
475 return i2s_frequency;
476}
477
478#if defined(LPTIM1)
479/**
480 * @brief Return LPTIMx clock frequency
481 * @param LPTIMxSource This parameter can be one of the following values:
482 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
483 * @retval LPTIM clock frequency (in Hz)
484 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
485 */
486uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
487{
488 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
489
490 /* Check parameter */
491 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
492
493 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
494 {
495 /* LPTIM1CLK clock frequency */
496 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
497 {
498 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
499 if (LL_RCC_LSI_IsReady())
500 {
501 lptim_frequency = LSI_VALUE;
502 }
503 break;
504
505 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
506 if (LL_RCC_HSI_IsReady())
507 {
508 lptim_frequency = HSI_VALUE;
509 }
510 break;
511
512 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
513 if (LL_RCC_LSE_IsReady())
514 {
515 lptim_frequency = LSE_VALUE;
516 }
517 break;
518
519 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
520 default:
521 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
522 break;
523 }
524 }
525
526 return lptim_frequency;
527}
528#endif /* LPTIM1 */
529
530#if defined(SAI1)
531/**
532 * @brief Return SAIx clock frequency
533 * @param SAIxSource This parameter can be one of the following values:
534 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
535 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
536 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
537 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
538 *
539 * (*) value not defined in all devices.
540 * @retval SAI clock frequency (in Hz)
541 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
542 */
543uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
544{
545 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
546
547 /* Check parameter */
548 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
549
550#if defined(RCC_DCKCFGR_SAI1SRC)
551 if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) || (SAIxSource == LL_RCC_SAI2_CLKSOURCE))
552 {
553 /* SAI1CLK clock frequency */
554 switch (LL_RCC_GetSAIClockSource(SAIxSource))
555 {
556 case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
557 case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
558 if (LL_RCC_PLLSAI_IsReady())
559 {
560 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
561 }
562 break;
563
564 case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
565 case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
566 if (LL_RCC_PLLI2S_IsReady())
567 {
568 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
569 }
570 break;
571
572 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
573 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
574 if (LL_RCC_PLL_IsReady())
575 {
576 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
577 }
578 break;
579
580 case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
581 switch (LL_RCC_PLL_GetMainSource())
582 {
583 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
584 if (LL_RCC_HSE_IsReady())
585 {
586 sai_frequency = HSE_VALUE;
587 }
588 break;
589
590 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
591 default:
592 if (LL_RCC_HSI_IsReady())
593 {
594 sai_frequency = HSI_VALUE;
595 }
596 break;
597 }
598 break;
599
600 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
601 default:
602 sai_frequency = EXTERNAL_CLOCK_VALUE;
603 break;
604 }
605 }
606#endif /* RCC_DCKCFGR_SAI1SRC */
607#if defined(RCC_DCKCFGR_SAI1ASRC)
608 if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) || (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE))
609 {
610 /* SAI1CLK clock frequency */
611 switch (LL_RCC_GetSAIClockSource(SAIxSource))
612 {
613#if defined(RCC_PLLSAI_SUPPORT)
614 case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block A clock source */
615 case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block B clock source */
616 if (LL_RCC_PLLSAI_IsReady())
617 {
618 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
619 }
620 break;
621#endif /* RCC_PLLSAI_SUPPORT */
622
623 case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block A clock source */
624 case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block B clock source */
625 if (LL_RCC_PLLI2S_IsReady())
626 {
627 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
628 }
629 break;
630
631#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
632 case LL_RCC_SAI1_A_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block A clock source */
633 case LL_RCC_SAI1_B_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block B clock source */
634 if (LL_RCC_PLL_IsReady())
635 {
636 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
637 }
638 break;
639
640 case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC:
641 case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC:
642 switch (LL_RCC_PLL_GetMainSource())
643 {
644 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 Block A or B clock source */
645 if (LL_RCC_HSE_IsReady())
646 {
647 sai_frequency = HSE_VALUE;
648 }
649 break;
650
651 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 Block A or B clock source */
652 default:
653 if (LL_RCC_HSI_IsReady())
654 {
655 sai_frequency = HSI_VALUE;
656 }
657 break;
658 }
659 break;
660#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
661
662 case LL_RCC_SAI1_A_CLKSOURCE_PIN: /* External input clock used as SAI1 Block A clock source */
663 case LL_RCC_SAI1_B_CLKSOURCE_PIN: /* External input clock used as SAI1 Block B clock source */
664 default:
665 sai_frequency = EXTERNAL_CLOCK_VALUE;
666 break;
667 }
668 }
669#endif /* RCC_DCKCFGR_SAI1ASRC */
670
671 return sai_frequency;
672}
673#endif /* SAI1 */
674
675#if defined(SDIO)
676/**
677 * @brief Return SDIOx clock frequency
678 * @param SDIOxSource This parameter can be one of the following values:
679 * @arg @ref LL_RCC_SDIO_CLKSOURCE
680 * @retval SDIO clock frequency (in Hz)
681 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
682 */
683uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)
684{
685 uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
686
687 /* Check parameter */
688 assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource));
689
690 if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE)
691 {
692#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
693 /* SDIOCLK clock frequency */
694 switch (LL_RCC_GetSDIOClockSource(SDIOxSource))
695 {
696 case LL_RCC_SDIO_CLKSOURCE_PLL48CLK: /* PLL48M clock used as SDIO clock source */
697 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
698 {
699 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
700 if (LL_RCC_PLL_IsReady())
701 {
702 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
703 }
704 break;
705
706#if defined(RCC_PLLSAI_SUPPORT)
707 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
708 default:
709 if (LL_RCC_PLLSAI_IsReady())
710 {
711 SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M();
712 }
713 break;
714#endif /* RCC_PLLSAI_SUPPORT */
715
716#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
717 case LL_RCC_CK48M_CLKSOURCE_PLLI2S: /* PLLI2S clock used as 48Mhz domain clock */
718 default:
719 if (LL_RCC_PLLI2S_IsReady())
720 {
721 SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M();
722 }
723 break;
724#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
725 }
726 break;
727
728 case LL_RCC_SDIO_CLKSOURCE_SYSCLK: /* PLL clock used as SDIO clock source */
729 default:
730 SDIO_frequency = RCC_GetSystemClockFreq();
731 break;
732 }
733#else
734 /* PLL clock used as 48Mhz domain clock */
735 if (LL_RCC_PLL_IsReady())
736 {
737 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
738 }
739#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
740 }
741
742 return SDIO_frequency;
743}
744#endif /* SDIO */
745
746#if defined(RNG)
747/**
748 * @brief Return RNGx clock frequency
749 * @param RNGxSource This parameter can be one of the following values:
750 * @arg @ref LL_RCC_RNG_CLKSOURCE
751 * @retval RNG clock frequency (in Hz)
752 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
753 */
754uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
755{
756 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
757
758 /* Check parameter */
759 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
760
761#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
762 /* RNGCLK clock frequency */
763 switch (LL_RCC_GetRNGClockSource(RNGxSource))
764 {
765#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
766 case LL_RCC_RNG_CLKSOURCE_PLLI2S: /* PLLI2S clock used as RNG clock source */
767 if (LL_RCC_PLLI2S_IsReady())
768 {
769 rng_frequency = RCC_PLLI2S_GetFreqDomain_48M();
770 }
771 break;
772#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
773
774#if defined(RCC_PLLSAI_SUPPORT)
775 case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
776 if (LL_RCC_PLLSAI_IsReady())
777 {
778 rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
779 }
780 break;
781#endif /* RCC_PLLSAI_SUPPORT */
782
783 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
784 default:
785 if (LL_RCC_PLL_IsReady())
786 {
787 rng_frequency = RCC_PLL_GetFreqDomain_48M();
788 }
789 break;
790 }
791#else
792 /* PLL clock used as RNG clock source */
793 if (LL_RCC_PLL_IsReady())
794 {
795 rng_frequency = RCC_PLL_GetFreqDomain_48M();
796 }
797#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
798
799 return rng_frequency;
800}
801#endif /* RNG */
802
803#if defined(CEC)
804/**
805 * @brief Return CEC clock frequency
806 * @param CECxSource This parameter can be one of the following values:
807 * @arg @ref LL_RCC_CEC_CLKSOURCE
808 * @retval CEC clock frequency (in Hz)
809 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
810 */
811uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
812{
813 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
814
815 /* Check parameter */
816 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
817
818 /* CECCLK clock frequency */
819 switch (LL_RCC_GetCECClockSource(CECxSource))
820 {
821 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
822 if (LL_RCC_LSE_IsReady())
823 {
824 cec_frequency = LSE_VALUE;
825 }
826 break;
827
828 case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
829 default:
830 if (LL_RCC_HSI_IsReady())
831 {
832 cec_frequency = HSI_VALUE/488U;
833 }
834 break;
835 }
836
837 return cec_frequency;
838}
839#endif /* CEC */
840
841#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
842/**
843 * @brief Return USBx clock frequency
844 * @param USBxSource This parameter can be one of the following values:
845 * @arg @ref LL_RCC_USB_CLKSOURCE
846 * @retval USB clock frequency (in Hz)
847 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
848 */
849uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
850{
851 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
852
853 /* Check parameter */
854 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
855
856#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
857 /* USBCLK clock frequency */
858 switch (LL_RCC_GetUSBClockSource(USBxSource))
859 {
860#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
861 case LL_RCC_USB_CLKSOURCE_PLLI2S: /* PLLI2S clock used as USB clock source */
862 if (LL_RCC_PLLI2S_IsReady())
863 {
864 usb_frequency = RCC_PLLI2S_GetFreqDomain_48M();
865 }
866 break;
867
868#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
869
870#if defined(RCC_PLLSAI_SUPPORT)
871 case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
872 if (LL_RCC_PLLSAI_IsReady())
873 {
874 usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
875 }
876 break;
877#endif /* RCC_PLLSAI_SUPPORT */
878
879 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
880 default:
881 if (LL_RCC_PLL_IsReady())
882 {
883 usb_frequency = RCC_PLL_GetFreqDomain_48M();
884 }
885 break;
886 }
887#else
888 /* PLL clock used as USB clock source */
889 if (LL_RCC_PLL_IsReady())
890 {
891 usb_frequency = RCC_PLL_GetFreqDomain_48M();
892 }
893#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
894
895 return usb_frequency;
896}
897#endif /* USB_OTG_FS || USB_OTG_HS */
898
899#if defined(DFSDM1_Channel0)
900/**
901 * @brief Return DFSDMx clock frequency
902 * @param DFSDMxSource This parameter can be one of the following values:
903 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
904 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
905 *
906 * (*) value not defined in all devices.
907 * @retval DFSDM clock frequency (in Hz)
908 */
909uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
910{
911 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
912
913 /* Check parameter */
914 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
915
916 if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE)
917 {
918 /* DFSDM1CLK clock frequency */
919 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
920 {
921 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
922 dfsdm_frequency = RCC_GetSystemClockFreq();
923 break;
924
925 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
926 default:
927 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
928 break;
929 }
930 }
931#if defined(DFSDM2_Channel0)
932 else
933 {
934 /* DFSDM2CLK clock frequency */
935 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
936 {
937 case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK: /* DFSDM2 Clock is SYSCLK */
938 dfsdm_frequency = RCC_GetSystemClockFreq();
939 break;
940
941 case LL_RCC_DFSDM2_CLKSOURCE_PCLK2: /* DFSDM2 Clock is PCLK2 */
942 default:
943 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
944 break;
945 }
946 }
947#endif /* DFSDM2_Channel0 */
948
949 return dfsdm_frequency;
950}
951
952/**
953 * @brief Return DFSDMx Audio clock frequency
954 * @param DFSDMxSource This parameter can be one of the following values:
955 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
956 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
957 *
958 * (*) value not defined in all devices.
959 * @retval DFSDM clock frequency (in Hz)
960 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
961 */
962uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
963{
964 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
965
966 /* Check parameter */
967 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
968
969 if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)
970 {
971 /* DFSDM1CLK clock frequency */
972 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
973 {
974 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM1 clock */
975 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
976 break;
977
978 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM1 clock */
979 default:
980 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
981 break;
982 }
983 }
984#if defined(DFSDM2_Channel0)
985 else
986 {
987 /* DFSDM2CLK clock frequency */
988 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
989 {
990 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM2 clock */
991 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
992 break;
993
994 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM2 clock */
995 default:
996 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
997 break;
998 }
999 }
1000#endif /* DFSDM2_Channel0 */
1001
1002 return dfsdm_frequency;
1003}
1004#endif /* DFSDM1_Channel0 */
1005
1006#if defined(DSI)
1007/**
1008 * @brief Return DSI clock frequency
1009 * @param DSIxSource This parameter can be one of the following values:
1010 * @arg @ref LL_RCC_DSI_CLKSOURCE
1011 * @retval DSI clock frequency (in Hz)
1012 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1013 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1014 */
1015uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1016{
1017 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1018
1019 /* Check parameter */
1020 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1021
1022 /* DSICLK clock frequency */
1023 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1024 {
1025 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
1026 if (LL_RCC_PLL_IsReady())
1027 {
1028 dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
1029 }
1030 break;
1031
1032 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
1033 default:
1034 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1035 break;
1036 }
1037
1038 return dsi_frequency;
1039}
1040#endif /* DSI */
1041
1042#if defined(LTDC)
1043/**
1044 * @brief Return LTDC clock frequency
1045 * @param LTDCxSource This parameter can be one of the following values:
1046 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1047 * @retval LTDC clock frequency (in Hz)
1048 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1049 */
1050uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1051{
1052 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1053
1054 /* Check parameter */
1055 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
1056
1057 if (LL_RCC_PLLSAI_IsReady())
1058 {
1059 ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
1060 }
1061
1062 return ltdc_frequency;
1063}
1064#endif /* LTDC */
1065
1066#if defined(SPDIFRX)
1067/**
1068 * @brief Return SPDIFRX clock frequency
1069 * @param SPDIFRXxSource This parameter can be one of the following values:
1070 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
1071 * @retval SPDIFRX clock frequency (in Hz)
1072 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1073 */
1074uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
1075{
1076 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1077
1078 /* Check parameter */
1079 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
1080
1081 /* SPDIFRX1CLK clock frequency */
1082 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
1083 {
1084 case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S: /* SPDIFRX Clock is PLLI2S Osc. */
1085 if (LL_RCC_PLLI2S_IsReady())
1086 {
1087 spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
1088 }
1089 break;
1090
1091 case LL_RCC_SPDIFRX1_CLKSOURCE_PLL: /* SPDIFRX Clock is PLL Osc. */
1092 default:
1093 if (LL_RCC_PLL_IsReady())
1094 {
1095 spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX();
1096 }
1097 break;
1098 }
1099
1100 return spdifrx_frequency;
1101}
1102#endif /* SPDIFRX */
1103
1104/**
1105 * @}
1106 */
1107
1108/**
1109 * @}
1110 */
1111
1112/** @addtogroup RCC_LL_Private_Functions
1113 * @{
1114 */
1115
1116/**
1117 * @brief Return SYSTEM clock frequency
1118 * @retval SYSTEM clock frequency (in Hz)
1119 */
1120uint32_t RCC_GetSystemClockFreq(void)
1121{
1122 uint32_t frequency = 0U;
1123
1124 /* Get SYSCLK source -------------------------------------------------------*/
1125 switch (LL_RCC_GetSysClkSource())
1126 {
1127 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1128 frequency = HSI_VALUE;
1129 break;
1130
1131 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1132 frequency = HSE_VALUE;
1133 break;
1134
1135 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1136 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
1137 break;
1138
1139#if defined(RCC_PLLR_SYSCLK_SUPPORT)
1140 case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock source */
1141 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR);
1142 break;
1143#endif /* RCC_PLLR_SYSCLK_SUPPORT */
1144
1145 default:
1146 frequency = HSI_VALUE;
1147 break;
1148 }
1149
1150 return frequency;
1151}
1152
1153/**
1154 * @brief Return HCLK clock frequency
1155 * @param SYSCLK_Frequency SYSCLK clock frequency
1156 * @retval HCLK clock frequency (in Hz)
1157 */
1158uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1159{
1160 /* HCLK clock frequency */
1161 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1162}
1163
1164/**
1165 * @brief Return PCLK1 clock frequency
1166 * @param HCLK_Frequency HCLK clock frequency
1167 * @retval PCLK1 clock frequency (in Hz)
1168 */
1169uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1170{
1171 /* PCLK1 clock frequency */
1172 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1173}
1174
1175/**
1176 * @brief Return PCLK2 clock frequency
1177 * @param HCLK_Frequency HCLK clock frequency
1178 * @retval PCLK2 clock frequency (in Hz)
1179 */
1180uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1181{
1182 /* PCLK2 clock frequency */
1183 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1184}
1185
1186/**
1187 * @brief Return PLL clock frequency used for system domain
1188 * @param SYSCLK_Source System clock source
1189 * @retval PLL clock frequency (in Hz)
1190 */
1191uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)
1192{
1193 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
1194
1195 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1196 SYSCLK = PLL_VCO / (PLLP or PLLR)
1197 */
1198 pllsource = LL_RCC_PLL_GetMainSource();
1199
1200 switch (pllsource)
1201 {
1202 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1203 pllinputfreq = HSI_VALUE;
1204 break;
1205
1206 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1207 pllinputfreq = HSE_VALUE;
1208 break;
1209
1210 default:
1211 pllinputfreq = HSI_VALUE;
1212 break;
1213 }
1214
1215 if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
1216 {
1217 plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1218 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1219 }
1220#if defined(RCC_PLLR_SYSCLK_SUPPORT)
1221 else
1222 {
1223 plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1224 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1225 }
1226#endif /* RCC_PLLR_SYSCLK_SUPPORT */
1227
1228 return plloutputfreq;
1229}
1230
1231/**
1232 * @brief Return PLL clock frequency used for 48 MHz domain
1233 * @retval PLL clock frequency (in Hz)
1234 */
1235uint32_t RCC_PLL_GetFreqDomain_48M(void)
1236{
1237 uint32_t pllinputfreq = 0U, pllsource = 0U;
1238
1239 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
1240 48M Domain clock = PLL_VCO / PLLQ
1241 */
1242 pllsource = LL_RCC_PLL_GetMainSource();
1243
1244 switch (pllsource)
1245 {
1246 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1247 pllinputfreq = HSI_VALUE;
1248 break;
1249
1250 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1251 pllinputfreq = HSE_VALUE;
1252 break;
1253
1254 default:
1255 pllinputfreq = HSI_VALUE;
1256 break;
1257 }
1258 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1259 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1260}
1261
1262#if defined(DSI)
1263/**
1264 * @brief Return PLL clock frequency used for DSI clock
1265 * @retval PLL clock frequency (in Hz)
1266 */
1267uint32_t RCC_PLL_GetFreqDomain_DSI(void)
1268{
1269 uint32_t pllinputfreq = 0U, pllsource = 0U;
1270
1271 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1272 DSICLK = PLL_VCO / PLLR
1273 */
1274 pllsource = LL_RCC_PLL_GetMainSource();
1275
1276 switch (pllsource)
1277 {
1278 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1279 pllinputfreq = HSE_VALUE;
1280 break;
1281
1282 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1283 default:
1284 pllinputfreq = HSI_VALUE;
1285 break;
1286 }
1287 return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1288 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1289}
1290#endif /* DSI */
1291
1292#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
1293/**
1294 * @brief Return PLL clock frequency used for I2S clock
1295 * @retval PLL clock frequency (in Hz)
1296 */
1297uint32_t RCC_PLL_GetFreqDomain_I2S(void)
1298{
1299 uint32_t pllinputfreq = 0U, pllsource = 0U;
1300
1301 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1302 I2SCLK = PLL_VCO / PLLR
1303 */
1304 pllsource = LL_RCC_PLL_GetMainSource();
1305
1306 switch (pllsource)
1307 {
1308 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1309 pllinputfreq = HSE_VALUE;
1310 break;
1311
1312 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1313 default:
1314 pllinputfreq = HSI_VALUE;
1315 break;
1316 }
1317 return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1318 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1319}
1320#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
1321
1322#if defined(SPDIFRX)
1323/**
1324 * @brief Return PLL clock frequency used for SPDIFRX clock
1325 * @retval PLL clock frequency (in Hz)
1326 */
1327uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void)
1328{
1329 uint32_t pllinputfreq = 0U, pllsource = 0U;
1330
1331 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1332 SPDIFRXCLK = PLL_VCO / PLLR
1333 */
1334 pllsource = LL_RCC_PLL_GetMainSource();
1335
1336 switch (pllsource)
1337 {
1338 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1339 pllinputfreq = HSE_VALUE;
1340 break;
1341
1342 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1343 default:
1344 pllinputfreq = HSI_VALUE;
1345 break;
1346 }
1347 return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1348 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1349}
1350#endif /* SPDIFRX */
1351
1352#if defined(RCC_PLLCFGR_PLLR)
1353#if defined(SAI1)
1354/**
1355 * @brief Return PLL clock frequency used for SAI clock
1356 * @retval PLL clock frequency (in Hz)
1357 */
1358uint32_t RCC_PLL_GetFreqDomain_SAI(void)
1359{
1360 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
1361
1362 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1363 SAICLK = (PLL_VCO / PLLR) / PLLDIVR
1364 or
1365 SAICLK = PLL_VCO / PLLR
1366 */
1367 pllsource = LL_RCC_PLL_GetMainSource();
1368
1369 switch (pllsource)
1370 {
1371 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1372 pllinputfreq = HSE_VALUE;
1373 break;
1374
1375 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1376 default:
1377 pllinputfreq = HSI_VALUE;
1378 break;
1379 }
1380
1381#if defined(RCC_DCKCFGR_PLLDIVR)
1382 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1383 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR());
1384#else
1385 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1386 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1387#endif /* RCC_DCKCFGR_PLLDIVR */
1388
1389 return plloutputfreq;
1390}
1391#endif /* SAI1 */
1392#endif /* RCC_PLLCFGR_PLLR */
1393
1394#if defined(RCC_PLLSAI_SUPPORT)
1395/**
1396 * @brief Return PLLSAI clock frequency used for SAI domain
1397 * @retval PLLSAI clock frequency (in Hz)
1398 */
1399uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
1400{
1401 uint32_t pllinputfreq = 0U, pllsource = 0U;
1402
1403 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1404 SAI domain clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
1405 */
1406 pllsource = LL_RCC_PLL_GetMainSource();
1407
1408 switch (pllsource)
1409 {
1410 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1411 pllinputfreq = HSI_VALUE;
1412 break;
1413
1414 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1415 pllinputfreq = HSE_VALUE;
1416 break;
1417
1418 default:
1419 pllinputfreq = HSI_VALUE;
1420 break;
1421 }
1422 return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1423 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
1424}
1425
1426#if defined(RCC_PLLSAICFGR_PLLSAIP)
1427/**
1428 * @brief Return PLLSAI clock frequency used for 48Mhz domain
1429 * @retval PLLSAI clock frequency (in Hz)
1430 */
1431uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
1432{
1433 uint32_t pllinputfreq = 0U, pllsource = 0U;
1434
1435 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1436 48M Domain clock = PLLSAI_VCO / PLLSAIP
1437 */
1438 pllsource = LL_RCC_PLL_GetMainSource();
1439
1440 switch (pllsource)
1441 {
1442 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1443 pllinputfreq = HSI_VALUE;
1444 break;
1445
1446 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1447 pllinputfreq = HSE_VALUE;
1448 break;
1449
1450 default:
1451 pllinputfreq = HSI_VALUE;
1452 break;
1453 }
1454 return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1455 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
1456}
1457#endif /* RCC_PLLSAICFGR_PLLSAIP */
1458
1459#if defined(LTDC)
1460/**
1461 * @brief Return PLLSAI clock frequency used for LTDC domain
1462 * @retval PLLSAI clock frequency (in Hz)
1463 */
1464uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
1465{
1466 uint32_t pllinputfreq = 0U, pllsource = 0U;
1467
1468 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1469 LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
1470 */
1471 pllsource = LL_RCC_PLL_GetMainSource();
1472
1473 switch (pllsource)
1474 {
1475 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1476 pllinputfreq = HSI_VALUE;
1477 break;
1478
1479 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1480 pllinputfreq = HSE_VALUE;
1481 break;
1482
1483 default:
1484 pllinputfreq = HSI_VALUE;
1485 break;
1486 }
1487 return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1488 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
1489}
1490#endif /* LTDC */
1491#endif /* RCC_PLLSAI_SUPPORT */
1492
1493#if defined(RCC_PLLI2S_SUPPORT)
1494#if defined(SAI1)
1495/**
1496 * @brief Return PLLI2S clock frequency used for SAI domains
1497 * @retval PLLI2S clock frequency (in Hz)
1498 */
1499uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
1500{
1501 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1502
1503 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1504 SAI domain clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
1505 or
1506 SAI domain clock = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR
1507 */
1508 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1509
1510 switch (plli2ssource)
1511 {
1512 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1513 plli2sinputfreq = HSE_VALUE;
1514 break;
1515
1516#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1517 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1518 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1519 break;
1520#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1521
1522 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1523 default:
1524 plli2sinputfreq = HSI_VALUE;
1525 break;
1526 }
1527
1528#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
1529 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1530 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
1531#else
1532 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1533 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR());
1534#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
1535
1536 return plli2soutputfreq;
1537}
1538#endif /* SAI1 */
1539
1540#if defined(SPDIFRX)
1541/**
1542 * @brief Return PLLI2S clock frequency used for SPDIFRX domain
1543 * @retval PLLI2S clock frequency (in Hz)
1544 */
1545uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
1546{
1547 uint32_t pllinputfreq = 0U, pllsource = 0U;
1548
1549 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1550 SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
1551 */
1552 pllsource = LL_RCC_PLLI2S_GetMainSource();
1553
1554 switch (pllsource)
1555 {
1556 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1557 pllinputfreq = HSE_VALUE;
1558 break;
1559
1560 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1561 default:
1562 pllinputfreq = HSI_VALUE;
1563 break;
1564 }
1565
1566 return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(),
1567 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
1568}
1569#endif /* SPDIFRX */
1570
1571/**
1572 * @brief Return PLLI2S clock frequency used for I2S domain
1573 * @retval PLLI2S clock frequency (in Hz)
1574 */
1575uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
1576{
1577 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1578
1579 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1580 I2S Domain clock = PLLI2S_VCO / PLLI2SR
1581 */
1582 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1583
1584 switch (plli2ssource)
1585 {
1586 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1587 plli2sinputfreq = HSE_VALUE;
1588 break;
1589
1590#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1591 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1592 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1593 break;
1594#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1595
1596 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1597 default:
1598 plli2sinputfreq = HSI_VALUE;
1599 break;
1600 }
1601
1602 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1603 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
1604
1605 return plli2soutputfreq;
1606}
1607
1608#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
1609/**
1610 * @brief Return PLLI2S clock frequency used for 48Mhz domain
1611 * @retval PLLI2S clock frequency (in Hz)
1612 */
1613uint32_t RCC_PLLI2S_GetFreqDomain_48M(void)
1614{
1615 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1616
1617 /* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1618 48M Domain clock = PLLI2S_VCO / PLLI2SQ
1619 */
1620 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1621
1622 switch (plli2ssource)
1623 {
1624 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1625 plli2sinputfreq = HSE_VALUE;
1626 break;
1627
1628#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1629 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1630 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1631 break;
1632#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1633
1634 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1635 default:
1636 plli2sinputfreq = HSI_VALUE;
1637 break;
1638 }
1639
1640 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1641 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ());
1642
1643 return plli2soutputfreq;
1644}
1645#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
1646#endif /* RCC_PLLI2S_SUPPORT */
1647/**
1648 * @}
1649 */
1650
1651/**
1652 * @}
1653 */
1654
1655#endif /* defined(RCC) */
1656
1657/**
1658 * @}
1659 */
1660
1661#endif /* USE_FULL_LL_DRIVER */
1662
1663/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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