source: S-port/trunk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c

Last change on this file was 1, checked in by AlexLir, 3 years ago
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19/* Includes ------------------------------------------------------------------*/
20#include "stm32f4xx_ll_utils.h"
21#include "stm32f4xx_ll_rcc.h"
22#include "stm32f4xx_ll_system.h"
23#include "stm32f4xx_ll_pwr.h"
24#ifdef USE_FULL_ASSERT
25#include "stm32_assert.h"
26#else
27#define assert_param(expr) ((void)0U)
28#endif /* USE_FULL_ASSERT */
29
30/** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34/** @addtogroup UTILS_LL
35 * @{
36 */
37
38/* Private types -------------------------------------------------------------*/
39/* Private variables ---------------------------------------------------------*/
40/* Private constants ---------------------------------------------------------*/
41/** @addtogroup UTILS_LL_Private_Constants
42 * @{
43 */
44#if defined(RCC_MAX_FREQUENCY_SCALE1)
45#define UTILS_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
46#endif /*RCC_MAX_FREQUENCY_SCALE1 */
47#define UTILS_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY_SCALE2 /*!< Maximum frequency for system clock at power scale2, in Hz */
48#if defined(RCC_MAX_FREQUENCY_SCALE3)
49#define UTILS_MAX_FREQUENCY_SCALE3 RCC_MAX_FREQUENCY_SCALE3 /*!< Maximum frequency for system clock at power scale3, in Hz */
50#endif /* MAX_FREQUENCY_SCALE3 */
51
52/* Defines used for PLL range */
53#define UTILS_PLLVCO_INPUT_MIN RCC_PLLVCO_INPUT_MIN /*!< Frequency min for PLLVCO input, in Hz */
54#define UTILS_PLLVCO_INPUT_MAX RCC_PLLVCO_INPUT_MAX /*!< Frequency max for PLLVCO input, in Hz */
55#define UTILS_PLLVCO_OUTPUT_MIN RCC_PLLVCO_OUTPUT_MIN /*!< Frequency min for PLLVCO output, in Hz */
56#define UTILS_PLLVCO_OUTPUT_MAX RCC_PLLVCO_OUTPUT_MAX /*!< Frequency max for PLLVCO output, in Hz */
57
58/* Defines used for HSE range */
59#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
60#define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
61
62/* Defines used for FLASH latency according to HCLK Frequency */
63#if defined(FLASH_SCALE1_LATENCY1_FREQ)
64#define UTILS_SCALE1_LATENCY1_FREQ FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
65#endif
66#if defined(FLASH_SCALE1_LATENCY2_FREQ)
67#define UTILS_SCALE1_LATENCY2_FREQ FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
68#endif
69#if defined(FLASH_SCALE1_LATENCY3_FREQ)
70#define UTILS_SCALE1_LATENCY3_FREQ FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
71#endif
72#if defined(FLASH_SCALE1_LATENCY4_FREQ)
73#define UTILS_SCALE1_LATENCY4_FREQ FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
74#endif
75#if defined(FLASH_SCALE1_LATENCY5_FREQ)
76#define UTILS_SCALE1_LATENCY5_FREQ FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
77#endif
78#define UTILS_SCALE2_LATENCY1_FREQ FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
79#define UTILS_SCALE2_LATENCY2_FREQ FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
80#if defined(FLASH_SCALE2_LATENCY3_FREQ)
81#define UTILS_SCALE2_LATENCY3_FREQ FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
82#endif
83#if defined(FLASH_SCALE2_LATENCY4_FREQ)
84#define UTILS_SCALE2_LATENCY4_FREQ FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
85#endif
86#if defined(FLASH_SCALE2_LATENCY5_FREQ)
87#define UTILS_SCALE2_LATENCY5_FREQ FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
88#endif
89#if defined(FLASH_SCALE3_LATENCY1_FREQ)
90#define UTILS_SCALE3_LATENCY1_FREQ FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
91#endif
92#if defined(FLASH_SCALE3_LATENCY2_FREQ)
93#define UTILS_SCALE3_LATENCY2_FREQ FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
94#endif
95#if defined(FLASH_SCALE3_LATENCY3_FREQ)
96#define UTILS_SCALE3_LATENCY3_FREQ FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
97#endif
98#if defined(FLASH_SCALE3_LATENCY4_FREQ)
99#define UTILS_SCALE3_LATENCY4_FREQ FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
100#endif
101#if defined(FLASH_SCALE3_LATENCY5_FREQ)
102#define UTILS_SCALE3_LATENCY5_FREQ FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */
103#endif
104/**
105 * @}
106 */
107
108/* Private macros ------------------------------------------------------------*/
109/** @addtogroup UTILS_LL_Private_Macros
110 * @{
111 */
112#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
113 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
114 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
115 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
116 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
117 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
118 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
119 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
120 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
121
122#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
123 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
124 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
125 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
126 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
127
128#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
129 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
130 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
131 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
132 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
133
134#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
135 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
136 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
137 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
138 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
139 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
140 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
141 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
142 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
143 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
144 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
145 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
146 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
147 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
148 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
149 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
150 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
151 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
152 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
153 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
154 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
155 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
156 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
157 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
158 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
159 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
160 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
161 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
162 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
163 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
164 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
165 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
166 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
167 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
168 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
169 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
170 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
171 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
172 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
173 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
174 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
175 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
176 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
177 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
178 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
179 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
180 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
181 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
182 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
183 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
184 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
185 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
186 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
187 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
188 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
189 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
190 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
191 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
192 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
193 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
194 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
195 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
196
197#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE))
198
199#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
200 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
201 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
202 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
203
204#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
205
206#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
207
208#if !defined(RCC_MAX_FREQUENCY_SCALE1)
209#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
210 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
211
212#elif defined(RCC_MAX_FREQUENCY_SCALE3)
213#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
214 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
215 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
216
217#else
218#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
219 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
220
221#endif /* RCC_MAX_FREQUENCY_SCALE1*/
222#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
223 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
224
225#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
226/**
227 * @}
228 */
229/* Private function prototypes -----------------------------------------------*/
230/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
231 * @{
232 */
233static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
234 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
235static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
236static ErrorStatus UTILS_PLL_IsBusy(void);
237/**
238 * @}
239 */
240
241/* Exported functions --------------------------------------------------------*/
242/** @addtogroup UTILS_LL_Exported_Functions
243 * @{
244 */
245
246/** @addtogroup UTILS_LL_EF_DELAY
247 * @{
248 */
249
250/**
251 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
252 * @note When a RTOS is used, it is recommended to avoid changing the Systick
253 * configuration by calling this function, for a delay use rather osDelay RTOS service.
254 * @param HCLKFrequency HCLK frequency in Hz
255 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
256 * @retval None
257 */
258void LL_Init1msTick(uint32_t HCLKFrequency)
259{
260 /* Use frequency provided in argument */
261 LL_InitTick(HCLKFrequency, 1000U);
262}
263
264/**
265 * @brief This function provides accurate delay (in milliseconds) based
266 * on SysTick counter flag
267 * @note When a RTOS is used, it is recommended to avoid using blocking delay
268 * and use rather osDelay service.
269 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
270 * will configure Systick to 1ms
271 * @param Delay specifies the delay time length, in milliseconds.
272 * @retval None
273 */
274void LL_mDelay(uint32_t Delay)
275{
276 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
277 /* Add this code to indicate that local variable is not used */
278 ((void)tmp);
279
280 /* Add a period to guaranty minimum wait */
281 if(Delay < LL_MAX_DELAY)
282 {
283 Delay++;
284 }
285
286 while (Delay)
287 {
288 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
289 {
290 Delay--;
291 }
292 }
293}
294
295/**
296 * @}
297 */
298
299/** @addtogroup UTILS_EF_SYSTEM
300 * @brief System Configuration functions
301 *
302 @verbatim
303 ===============================================================================
304 ##### System Configuration functions #####
305 ===============================================================================
306 [..]
307 System, AHB and APB buses clocks configuration
308
309 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.
310 @endverbatim
311 @internal
312 Depending on the device voltage range, the maximum frequency should be
313 adapted accordingly to the Refenece manual.
314 @endinternal
315 * @{
316 */
317
318/**
319 * @brief This function sets directly SystemCoreClock CMSIS variable.
320 * @note Variable can be calculated also through SystemCoreClockUpdate function.
321 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
322 * @retval None
323 */
324void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
325{
326 /* HCLK clock frequency */
327 SystemCoreClock = HCLKFrequency;
328}
329
330/**
331 * @brief Update number of Flash wait states in line with new frequency and current
332 voltage range.
333 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
334 * @param HCLK_Frequency HCLK frequency
335 * @retval An ErrorStatus enumeration value:
336 * - SUCCESS: Latency has been modified
337 * - ERROR: Latency cannot be modified
338 */
339ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
340{
341 uint32_t timeout;
342 uint32_t getlatency;
343 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
344 ErrorStatus status = SUCCESS;
345
346
347 /* Frequency cannot be equal to 0 */
348 if(HCLK_Frequency == 0U)
349 {
350 status = ERROR;
351 }
352 else
353 {
354 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
355 {
356#if defined (UTILS_SCALE1_LATENCY5_FREQ)
357 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
358 {
359 latency = LL_FLASH_LATENCY_5;
360 }
361#endif /*UTILS_SCALE1_LATENCY5_FREQ */
362#if defined (UTILS_SCALE1_LATENCY4_FREQ)
363 if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
364 {
365 latency = LL_FLASH_LATENCY_4;
366 }
367#endif /* UTILS_SCALE1_LATENCY4_FREQ */
368#if defined (UTILS_SCALE1_LATENCY3_FREQ)
369 if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
370 {
371 latency = LL_FLASH_LATENCY_3;
372 }
373#endif /* UTILS_SCALE1_LATENCY3_FREQ */
374#if defined (UTILS_SCALE1_LATENCY2_FREQ)
375 if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
376 {
377 latency = LL_FLASH_LATENCY_2;
378 }
379 else
380 {
381 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
382 {
383 latency = LL_FLASH_LATENCY_1;
384 }
385 }
386#endif /* UTILS_SCALE1_LATENCY2_FREQ */
387 }
388 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
389 {
390#if defined (UTILS_SCALE2_LATENCY5_FREQ)
391 if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
392 {
393 latency = LL_FLASH_LATENCY_5;
394 }
395#endif /*UTILS_SCALE1_LATENCY5_FREQ */
396#if defined (UTILS_SCALE2_LATENCY4_FREQ)
397 if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
398 {
399 latency = LL_FLASH_LATENCY_4;
400 }
401#endif /*UTILS_SCALE1_LATENCY4_FREQ */
402#if defined (UTILS_SCALE2_LATENCY3_FREQ)
403 if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
404 {
405 latency = LL_FLASH_LATENCY_3;
406 }
407#endif /*UTILS_SCALE1_LATENCY3_FREQ */
408 if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
409 {
410 latency = LL_FLASH_LATENCY_2;
411 }
412 else
413 {
414 if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
415 {
416 latency = LL_FLASH_LATENCY_1;
417 }
418 }
419 }
420#if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
421 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
422 {
423#if defined (UTILS_SCALE3_LATENCY3_FREQ)
424 if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
425 {
426 latency = LL_FLASH_LATENCY_3;
427 }
428#endif /*UTILS_SCALE1_LATENCY3_FREQ */
429#if defined (UTILS_SCALE3_LATENCY2_FREQ)
430 if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
431 {
432 latency = LL_FLASH_LATENCY_2;
433 }
434 else
435 {
436 if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
437 {
438 latency = LL_FLASH_LATENCY_1;
439 }
440 }
441 }
442#endif /*UTILS_SCALE1_LATENCY2_FREQ */
443#endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
444
445 LL_FLASH_SetLatency(latency);
446 /* Check that the new number of wait states is taken into account to access the Flash
447 memory by reading the FLASH_ACR register */
448 timeout = 2;
449 do
450 {
451 /* Wait for Flash latency to be updated */
452 getlatency = LL_FLASH_GetLatency();
453 timeout--;
454 } while ((getlatency != latency) && (timeout > 0));
455
456 if(getlatency != latency)
457 {
458 status = ERROR;
459 }
460 else
461 {
462 status = SUCCESS;
463 }
464 }
465 return status;
466}
467
468/**
469 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
470 * @note The application need to ensure that PLL is disabled.
471 * @note Function is based on the following formula:
472 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
473 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
474 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
475 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
476 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
477 * the configuration information for the PLL.
478 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
479 * the configuration information for the BUS prescalers.
480 * @retval An ErrorStatus enumeration value:
481 * - SUCCESS: Max frequency configuration done
482 * - ERROR: Max frequency configuration not done
483 */
484ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
485 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
486{
487 ErrorStatus status = SUCCESS;
488 uint32_t pllfreq = 0U;
489
490 /* Check if one of the PLL is enabled */
491 if(UTILS_PLL_IsBusy() == SUCCESS)
492 {
493 /* Calculate the new PLL output frequency */
494 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
495
496 /* Enable HSI if not enabled */
497 if(LL_RCC_HSI_IsReady() != 1U)
498 {
499 LL_RCC_HSI_Enable();
500 while (LL_RCC_HSI_IsReady() != 1U)
501 {
502 /* Wait for HSI ready */
503 }
504 }
505
506 /* Configure PLL */
507 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
508 UTILS_PLLInitStruct->PLLP);
509
510 /* Enable PLL and switch system clock to PLL */
511 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
512 }
513 else
514 {
515 /* Current PLL configuration cannot be modified */
516 status = ERROR;
517 }
518
519 return status;
520}
521
522/**
523 * @brief This function configures system clock with HSE as clock source of the PLL
524 * @note The application need to ensure that PLL is disabled.
525 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
526 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
527 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
528 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
529 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
530 * @param HSEBypass This parameter can be one of the following values:
531 * @arg @ref LL_UTILS_HSEBYPASS_ON
532 * @arg @ref LL_UTILS_HSEBYPASS_OFF
533 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
534 * the configuration information for the PLL.
535 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
536 * the configuration information for the BUS prescalers.
537 * @retval An ErrorStatus enumeration value:
538 * - SUCCESS: Max frequency configuration done
539 * - ERROR: Max frequency configuration not done
540 */
541ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
542 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
543{
544 ErrorStatus status = SUCCESS;
545 uint32_t pllfreq = 0U;
546
547 /* Check the parameters */
548 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
549 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
550
551 /* Check if one of the PLL is enabled */
552 if(UTILS_PLL_IsBusy() == SUCCESS)
553 {
554 /* Calculate the new PLL output frequency */
555 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
556
557 /* Enable HSE if not enabled */
558 if(LL_RCC_HSE_IsReady() != 1U)
559 {
560 /* Check if need to enable HSE bypass feature or not */
561 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
562 {
563 LL_RCC_HSE_EnableBypass();
564 }
565 else
566 {
567 LL_RCC_HSE_DisableBypass();
568 }
569
570 /* Enable HSE */
571 LL_RCC_HSE_Enable();
572 while (LL_RCC_HSE_IsReady() != 1U)
573 {
574 /* Wait for HSE ready */
575 }
576 }
577
578 /* Configure PLL */
579 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
580 UTILS_PLLInitStruct->PLLP);
581
582 /* Enable PLL and switch system clock to PLL */
583 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
584 }
585 else
586 {
587 /* Current PLL configuration cannot be modified */
588 status = ERROR;
589 }
590
591 return status;
592}
593
594/**
595 * @}
596 */
597
598/**
599 * @}
600 */
601
602/** @addtogroup UTILS_LL_Private_Functions
603 * @{
604 */
605/**
606 * @brief Function to check that PLL can be modified
607 * @param PLL_InputFrequency PLL input frequency (in Hz)
608 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
609 * the configuration information for the PLL.
610 * @retval PLL output frequency (in Hz)
611 */
612static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
613{
614 uint32_t pllfreq = 0U;
615
616 /* Check the parameters */
617 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
618 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
619 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
620
621 /* Check different PLL parameters according to RM */
622 /* - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz. */
623 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
624 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
625
626 /* - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/
627 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
628 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
629
630 /* - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached */
631 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
632 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
633
634 return pllfreq;
635}
636
637/**
638 * @brief Function to check that PLL can be modified
639 * @retval An ErrorStatus enumeration value:
640 * - SUCCESS: PLL modification can be done
641 * - ERROR: PLL is busy
642 */
643static ErrorStatus UTILS_PLL_IsBusy(void)
644{
645 ErrorStatus status = SUCCESS;
646
647 /* Check if PLL is busy*/
648 if(LL_RCC_PLL_IsReady() != 0U)
649 {
650 /* PLL configuration cannot be modified */
651 status = ERROR;
652 }
653
654#if defined(RCC_PLLSAI_SUPPORT)
655 /* Check if PLLSAI is busy*/
656 if(LL_RCC_PLLSAI_IsReady() != 0U)
657 {
658 /* PLLSAI1 configuration cannot be modified */
659 status = ERROR;
660 }
661#endif /*RCC_PLLSAI_SUPPORT*/
662#if defined(RCC_PLLI2S_SUPPORT)
663 /* Check if PLLI2S is busy*/
664 if(LL_RCC_PLLI2S_IsReady() != 0U)
665 {
666 /* PLLI2S configuration cannot be modified */
667 status = ERROR;
668 }
669#endif /*RCC_PLLI2S_SUPPORT*/
670 return status;
671}
672
673/**
674 * @brief Function to enable PLL and switch system clock to PLL
675 * @param SYSCLK_Frequency SYSCLK frequency
676 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
677 * the configuration information for the BUS prescalers.
678 * @retval An ErrorStatus enumeration value:
679 * - SUCCESS: No problem to switch system to PLL
680 * - ERROR: Problem to switch system to PLL
681 */
682static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
683{
684 ErrorStatus status = SUCCESS;
685 uint32_t hclk_frequency = 0U;
686
687 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
688 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
689 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
690
691 /* Calculate HCLK frequency */
692 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
693
694 /* Increasing the number of wait states because of higher CPU frequency */
695 if(SystemCoreClock < hclk_frequency)
696 {
697 /* Set FLASH latency to highest latency */
698 status = LL_SetFlashLatency(hclk_frequency);
699 }
700
701 /* Update system clock configuration */
702 if(status == SUCCESS)
703 {
704 /* Enable PLL */
705 LL_RCC_PLL_Enable();
706 while (LL_RCC_PLL_IsReady() != 1U)
707 {
708 /* Wait for PLL ready */
709 }
710
711 /* Sysclk activation on the main PLL */
712 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
713 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
714 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
715 {
716 /* Wait for system clock switch to PLL */
717 }
718
719 /* Set APB1 & APB2 prescaler*/
720 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
721 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
722 }
723
724 /* Decreasing the number of wait states because of lower CPU frequency */
725 if(SystemCoreClock > hclk_frequency)
726 {
727 /* Set FLASH latency to lowest latency */
728 status = LL_SetFlashLatency(hclk_frequency);
729 }
730
731 /* Update SystemCoreClock variable */
732 if(status == SUCCESS)
733 {
734 LL_SetSystemCoreClock(hclk_frequency);
735 }
736
737 return status;
738}
739
740/**
741 * @}
742 */
743
744/**
745 * @}
746 */
747
748/**
749 * @}
750 */
751
752/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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