| [1] | 1 | // File: STM32F405_415_407_417_427_437_429_439.dbgconf
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| 2 | // Version: 1.0.0
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| 3 | // Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
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| 4 | // refer to STM32F40x STM32F41x datasheets
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| 5 | // refer to STM32F42x STM32F43x datasheets
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| 6 |
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| 7 | // <<< Use Configuration Wizard in Context Menu >>>
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| 8 |
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| 9 | // <h> Debug MCU configuration register (DBGMCU_CR)
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| 10 | // <o.2> DBG_STANDBY <i> Debug Standby Mode
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| 11 | // <o.1> DBG_STOP <i> Debug Stop Mode
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| 12 | // <o.0> DBG_SLEEP <i> Debug Sleep Mode
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| 13 | // </h>
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| 14 | DbgMCU_CR = 0x00000007;
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| 15 |
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| 16 | // <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
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| 17 | // <i> Reserved bits must be kept at reset value
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| 18 | // <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
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| 19 | // <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
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| 20 | // <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
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| 21 | // <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
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| 22 | // <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
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| 23 | // <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
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| 24 | // <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
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| 25 | // <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
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| 26 | // <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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| 27 | // <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
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| 28 | // <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
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| 29 | // <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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| 30 | // <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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| 31 | // <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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| 32 | // <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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| 33 | // <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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| 34 | // <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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| 35 | // </h>
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| 36 | DbgMCU_APB1_Fz = 0x00000000;
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| 37 |
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| 38 | // <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
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| 39 | // <i> Reserved bits must be kept at reset value
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| 40 | // <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
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| 41 | // <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
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| 42 | // <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
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| 43 | // <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
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| 44 | // <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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| 45 | // </h>
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| 46 | DbgMCU_APB2_Fz = 0x00000000;
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| 47 |
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| 48 | // <<< end of configuration section >>>
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